JP2002251885A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory capable of enhancing read-out precision with a new configuration. SOLUTION: In a read-out circuit 10, when a transistor is in a off-state in the consequence of that read-out performed for memory transistors T01-T03 in a memory block cell block X, a switch S2 is turned on, and substrate bias voltage is applied to memory transistors T11-T13 of a memory cell block Y. In a read-out circuit 11, when a transistor is in a off-state in the consequence of that read-out is performed for memory transistors T11-T13 in a memory block cell book Y, a switch S1 is turned on, and substrate bias voltage is applied to the memory transistors T01-T03 of the memory cell block X.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device, a redundant circuit may be used to store data with high accuracy. FIG. 13 shows a general redundant circuit in a conventional nonvolatile semiconductor memory device. In the apparatus of FIG.
Three nonvolatile memory cells 71, 72, and 73 are provided for bit data (information). The data stored in the nonvolatile memory cells 71, 72, and 73 are read out by the memory readout circuits 74, 75, and 76, and the readout circuits 74, 75, and 76 determine the determination circuit 77.
Has been taken into. And the judgment circuit 7
7, it is determined whether or not the same data exists in a majority (two) or more of the three stored data (a majority decision is made), and the two or more same data are read as correct data. In this case, the memory cell 7
Even if any one of 1, 72 and 73 becomes abnormal, the reading accuracy is ensured.

However, in the above-mentioned technology, three bits of memory cells 71, 72 and 73 are required for one bit of data (information) in order to ensure the reliability of stored data. Increasing costs are a problem.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of improving readout accuracy with a novel configuration. It is to provide a device.

[0005]

According to the first aspect of the present invention, charges are injected into the floating gate electrode disposed on the semiconductor substrate of the transistor cell via the insulating film by the data writing means. Then, as a result of reading data from the transistor cells, if any of the transistor cells is in a charge injection state, a substrate bias is applied by the substrate bias applying unit.

Here, if a part of the charge injected into the floating gate electrode in one of the plurality of transistor cells for storing 1-bit data is removed, the threshold voltage changes. It is conceivable that the transistor malfunctions during data reading. On the other hand, if the result of data reading shows that the other transistor cells are in the charge injection state,
Since the substrate bias is applied by the substrate bias applying means and the threshold voltage is shifted, even in the transistor cell in which a part of the electric charge has escaped, the transistor operates normally at the time of data reading.

As a result, the readout accuracy can be improved by performing double data storage without performing triple data storage as shown in FIG. 13 of the prior art.
According to the second aspect of the present invention, when the threshold voltage is raised by injecting electric charge into the floating gate electrode and the transistor is turned off at the time of data reading, a part of the electric charge is lost in the transistor cell. In the above, the transistor is not turned off in the data reading in the state where the substrate bias is not applied, but the transistor can be turned off by reading the data in a state where the threshold voltage is raised by applying the substrate bias. .

According to the third aspect of the present invention, 1
Two transistor cells are provided for each bit, and if one transistor cell is off, a substrate bias is applied to the other transistor cell,
If the transistor cell is off with the substrate bias applied, the substrate bias is applied to one of the transistor cells. In this case, 2
If any one of the two transistor cells is off (charge injection state), a substrate bias is applied to the transistor cell from which a part of the charge has escaped (retention characteristics have deteriorated), and the threshold voltage thereof Is enhanced. Also, a substrate bias is applied to a transistor cell from which no charge has been released, and the threshold voltage is increased. Thereby, the reliability of data in the transistor cell can be improved.

According to a fourth aspect of the present invention, a transistor cell is insulated and isolated by forming a trench in a semiconductor layer of an SOI substrate, or a P-type is formed on a surface layer portion of an N-type semiconductor substrate. The transistor cell is junction-separated by forming a well island, or an N-type well layer is formed on a surface layer of a P-type semiconductor substrate, and a P-type well layer is formed on the surface layer of the well layer. When the transistor cell is junction-separated by forming the well island and a substrate bias is applied to the separated transistor cell, the threshold voltage of the transistor cell to which the bias is applied increases, and the data reading accuracy can be improved.

Further, the unit of separation is as defined in claim 5
As in the case of the eighth and eleventh embodiments, the transistor may be separated for each transistor cell, or may be separated for each of a plurality of transistor cells. When the former is separated for each transistor cell, a substrate bias can be applied only to a necessary cell. Further, in the latter case where the plurality of transistor cells are separated, a circuit for applying a substrate bias can be shared, and the device can be reduced in size.

Here, in a memory (flash memory) in which data is erased collectively for a plurality of transistor cells, the threshold voltage after erasure varies, and excessive erasure may cause a problem. In contrast, claims 6, 9,
As shown in 12, by separating each of the plurality of transistor cells and applying a substrate bias to all of the plurality of transistor cells, it becomes possible to increase the threshold voltage of the transistor cell which is excessively erased during data reading. .
Thus, when the over-erased transistor cell is unselected, the transistor can be reliably turned off, and the problem of over-erasure (current leakage via the unselected transistor) can be avoided.

Further, when a transistor cell is insulated and isolated by forming a trench in a semiconductor layer in an SOI substrate as described in claims 4 to 6, even if the erase voltage is increased, adjacent cells separated by the trench are adversely affected. Has no effect. Therefore, a high voltage can be applied at the time of erasing, and the thickness of the insulating film between the semiconductor substrate and the floating gate electrode can be increased. As a result, it is possible to suppress a leak current (charge loss) through the insulating film and deterioration of the insulating film due to a writing or erasing operation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the present embodiment.

In FIG. 1, a nonvolatile memory (for example,
EPROM) has two memory cell blocks X and Y. In each of the blocks X and Y, a plurality of memory transistors for storing bit data (memory transistors T01 to T03 and T11 to T13 for three bits in FIG. 1).
Is shown). Then, the same data is stored in each of the memory transistor T01 and the memory transistor T11. Similarly, the same data is stored in the transistor T02 and the transistor T12.
03 and the transistor T13 store the same data. That is, in this embodiment, two memory transistors are prepared for one bit, and one bit data is stored in each of the two memory transistors.

The transistor cell (memory cell) of this embodiment is formed on a semiconductor substrate such as a silicon substrate.
It has a layer polycrystalline silicon type stack structure. More specifically, as shown in FIG. 2, a P-type well island 2 is formed on the surface of an N-type semiconductor substrate (for example, a silicon substrate) 1. The + type source region 3 and the N + type drain region 4 are formed apart from each other. Further, on the semiconductor substrate 1, a floating gate electrode 6 made of polycrystalline silicon is arranged via a gate oxide film 5 as an insulating film. The floating gate electrode 6 has a rectangular shape and extends so as to pass between the source region 3 and the drain region 4. A control gate electrode 7 made of polycrystalline silicon is formed on the floating gate electrode 6 via a silicon oxide film.
Is arranged.

Data writing is performed by grounding the source region 3 and applying a high voltage (eg, 12 V) to the control gate electrode 7 to inject electrons into the floating gate electrode 6. As a result, the threshold voltage increases. On the other hand, erasing data
This is performed by applying a high voltage (for example, 12 V) to the source region 3, grounding the control gate electrode 7, and extracting electrons from the floating gate electrode 6.
Alternatively, data can be erased by irradiating UV light.

As described above, in the transistor cell of FIG. 2, the charge is injected into the floating gate electrode 6 to increase the threshold voltage and store and retain data. It is conceivable that the data leakage characteristic deteriorates due to the leak current (charge loss). Therefore, in the present embodiment, the P + -type substrate contact region 8 is formed in the surface layer of the P-type well island 2.
The threshold voltage of the memory transistor is increased by applying a substrate bias through the substrate contact region 8 to improve the data reading accuracy. In FIG. 1, peripheral circuits (data writing means and the like) for writing and erasing data are omitted, and only a circuit for reading data is shown.

More specifically, referring to FIG. 1, the memory transistors T01, T02,
T03 is connected to the memory read circuit 10, and the memory transistors T11, T12, T13 in the memory cell block Y are connected to the memory read circuit 11. The read circuit 10 has a plurality of switches S01, S02, S03, turns on the switches S01 to S03 corresponding to the selected bit, and connects the memory transistor T0 connected by the switches S01 to S03.
The stored information of 1 to T03 is read. Similarly, the read circuit 11 has a plurality of switches S11, S12, and S13, and switches S11 to S11 corresponding to the selected bit.
13 is turned on, and information stored in the memory transistors T11 to T13 connected by the switches S11 to S13 is read.

Further, in this embodiment, a substrate bias circuit 20 is provided. The substrate bias circuit 20 generates a substrate bias (for example, 5 V). The substrate bias circuit 20 is connected to the memory cell block X via the switch S1.
Are connected to the memory transistors T01 to T03. The substrate bias circuit 20 is connected to the memory transistor T11 of the memory cell block Y via the switch S2.
To T13.

Next, the operation of the circuit shown in FIG. 1 will be described. For example, when selecting the memory transistors T02 and T12 and reading the stored data, the read circuit 10 turns on the switch S02 and the read circuit 11 turns on S12.

When data is not written to the memory transistors T02 and T12 (charge is not injected), the threshold voltage of the transistors T02 and T12 is low, so that the gate voltage is applied to the word line Lw. Is applied, the transistors T02 and T12 are turned on, and an output current flows to the data line Lb via the switch S02. This output current is detected by a sense amplifier (not shown) or the like, and data “1” is read as stored information. On the other hand, when data is written to the memory transistors T02 and T12 (charge is injected),
Since the threshold voltages of the transistors T02 and T12 are high, the transistors T02 and T12 are turned off even if a gate voltage is applied to the word line Lw, and no output current flows to the data line Lb. Therefore, data “0” is read as stored information.

Here, the memory transistors T02, T1
Even if data "0" is written in each of the two, it is conceivable that the threshold voltage of one of the memory transistors (for example, the transistor T12) decreases due to the deterioration of the data holding characteristic, and the transistor turns on at the time of reading. . However, in this embodiment, if the other memory transistor (for example, the transistor T02) is off, the switch S2 is turned on by the read circuit 10. Then, a substrate bias (for example, 5 V) is applied from the substrate bias circuit 20 to the transistor T12. As a result, the threshold voltage of the memory transistor T12 increases, and the transistor T12 is turned off at the time of reading, and data "0" is read. Further, when the data of the transistor T12 becomes “0”,
The switch S1 is turned on by the read circuit 11. Then, from the substrate bias circuit 20, the memory transistor T
02, a substrate bias is applied. Thus, the threshold voltage of the transistor T02 increases, so that the transistor T02 is reliably turned off, and data reliability is improved. That is, since the threshold voltage is increased by the application of the substrate bias, the data retention characteristics when used at a high temperature for a long time are significantly improved, and the data reliability is improved.

Further, even when the holding characteristic of the memory transistor T02 deteriorates and the transistor is turned on at the time of data reading, if the memory transistor T12 is off and the stored data "0" is read, the reading circuit 11 The switch S1 is turned on, and a substrate bias is applied to the memory transistor T02. This allows
Since the threshold voltage of the memory transistor T02 increases and the transistor turns off, data “0” is read via the data line Lb.

In this embodiment, the read circuit 1
Reference numerals 0 and 11 correspond to a substrate bias applying unit. As described above, the present embodiment has the following features.

(1) Two memory transistors are prepared for one bit, and as a result of reading data from the memory transistor, if one transistor is off, a substrate bias is applied to the other transistor. did. Further, if the transistor is off while the substrate bias is applied, the substrate bias is applied to one of the transistors.
Therefore, as a result of data reading, one of the two memory transistors is turned off (charge injection state).
In this case, a substrate bias is applied to the transistor from which a part of the charge has escaped (the holding characteristic has deteriorated), and the threshold voltage thereof is increased. As a result, in a memory transistor from which a part of the electric charge has been removed, the transistor does not turn off when data is read without a substrate bias applied, but when the threshold voltage is increased by applying a substrate bias. By reading data, the transistor can be turned off. Further, the threshold voltage is increased by applying the substrate bias to the memory transistor from which the electric charge has not been released, so that the transistor is reliably turned off. In this way, the readout accuracy can be improved by performing double data storage without performing triple data storage as in FIG. 13 of the related art.

(Second Embodiment) Next, a second embodiment will be described focusing on differences from the first embodiment. FIG. 3 is a circuit diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the present embodiment. In this embodiment, a flash memory that erases all stored data at once is used.

As shown in FIG. 3, the flash memory comprises:
Similarly to the first embodiment, the memory cell block is divided into two memory cell blocks X and Y, and a plurality of memory transistors T01 to T09 and T11 to T19 are arranged in a lattice in the block X and Y. I have.

The memory transistors T01 to T09 of the memory cell block X are connected to the memory read circuit 10, and the memory transistors T11 to T09 of the memory cell block Y are connected.
T19 are connected to the memory read circuit 11. More specifically, the memory transistors T01, T0
4, T07 is connected to the switch S01 and the memory transistor T
02, T05 and T08 are connected to the switch S02, and the memory transistors T03, T06 and T09 are connected to the switch S03. Further, the memory transistor T1
1, T14 and T17 are connected to switch S11, memory transistors T12, T15 and T18 are connected to switch S12, and memory transistors T13, T16 and T19 are connected to switch S11.
13 respectively.

The substrate bias (for example, 5 V) generated by the substrate bias circuit 20 is applied to all the memory transistors T01 to T09 in the memory cell block X via the switch S1. Also,
The substrate bias from the substrate bias circuit 20 is applied to all the memory transistors T11 to T19 in the memory cell block Y via the switch S2.

Next, the operation of the circuit shown in FIG. 3 will be described. Now, consider a case where data “0” is written to the transistors T05 and T15. In this case, first, all the memory transistors T01 to T09 and T11 are erased by batch erasing of data.
After setting the storage data of T19 to "1", data "0" is written to the memory transistors T05 and T15. Specifically, similarly to the first embodiment, data erasing is performed by applying a high voltage (for example, 12 V) to the source, grounding the control gate, and extracting electrons from the floating gate. In addition, data “0”
Is performed by grounding the source, applying a high voltage (for example, 12 V) to the control gate, and injecting electrons into the floating gate.

When reading data from the memory transistor T05, a gate voltage is applied to the word line Lw connected to the transistor T05, and the switch S02 is turned on. At this time, for example, if excessive erasure has occurred in the memory transistor T02, the transistor T02 turns on, an output current flows through the data line Lb, and data "1" is erroneously read. .

On the other hand, in the present embodiment, if the memory transistor T15 of the memory cell block Y is off, the read circuit 11 turns on the switch S1. As a result, a substrate bias is applied to all the memory transistors T01 to T09 in the memory cell block X, so that the threshold voltage of the over-erased memory transistor T02 increases. As a result, the problem of excessive erasure (leakage current due to the memory transistor T02) is avoided. At this time, the threshold voltage of the memory transistor T05 also increases, so that the data "0"
Is reliably read.

Generally, since data is erased in a flash memory all at once, it is known that the threshold voltage after erasure varies, which causes a problem of excessive erasure. As a countermeasure, by applying a substrate bias to the memory transistor that has been over-erased at the time of data reading as in the present embodiment, the problem due to the over-erasing can be avoided.

Next, FIG. 4 shows a plan view of a flash memory (memory cell block X) used in the present embodiment. FIG. 5 is a longitudinal sectional view taken along line AA in FIG. 4, and FIG. 6 is a longitudinal sectional view taken along line BB in FIG.

As shown in FIGS. 5 and 6, a P-type well island 22a is formed in a surface portion of an N-type semiconductor substrate (for example, a silicon substrate) 21. As shown in FIG. 5, N + type source regions 23a and 23b and N + type drain regions 24a and 2b are formed on the surface of the P type well island 22a.
4b are formed apart from each other. Further, a P + type substrate contact region 25 is formed in the surface layer portion of the P type well island 22a so as to be separated from the N + type source region 23a.

As shown in FIGS. 4 and 5, the semiconductor substrate 2
A band-shaped LOCOS oxide film 26 is formed on the surface of the substrate 1 so as to sandwich both sides of the substrate contact region 25. As shown in FIGS. 4 and 6, a LOCOS oxide film 27 is formed on the surface of the semiconductor substrate 21 in a region between adjacent transistor cells.

Further, as shown in FIGS. 4 to 6, a floating gate electrode 31 made of polycrystalline silicon is arranged on a semiconductor substrate 21 via a gate oxide film 30 as an insulating film. This floating gate electrode 3
Reference numeral 1 denotes a rectangle which extends between the source regions 23a and 23b and the drain regions 24a and 24b. A strip-shaped control gate electrode 33 is arranged on the floating gate electrode 31 via a silicon oxide film. Control gate electrode 33 is made of polycrystalline silicon. The floating gate electrode 31 and the control gate electrode 33 are arranged in a state of completely overlapping as a planar structure. That is, the flash memory according to the present embodiment is formed in a two-layer polycrystalline silicon type stack structure. Note that a silicon oxide film is disposed around the control gate electrode 33 on the semiconductor substrate 21.

Further, as shown in FIG.
4a and 24b, a drain contact electrode 35 is provided on the substrate contact region 25, and a substrate contact electrode 36a is provided on the substrate contact region 25.
Is formed of aluminum or the like. In the present embodiment, the drain contact electrode 35 is provided in common for two memory cells.

Then, the control gate electrode 33 is connected to the word line Lw in FIG. 3, and the drain contact electrode 35 is connected to the read circuit 10 in FIG. Further, the substrate contact electrode 36a is connected to the substrate bias circuit 20 via the switch S1 in FIG. That is, the substrate contact electrode 36a has
A substrate bias is applied via the switch S1.

As described above, in this embodiment, one P
In the mold well island 22a, a plurality of memory transistors T01 to T09 (see FIG. 3) forming the memory cell block X are formed. Then, a substrate bias is applied from the substrate contact electrode 36a to the P-type well island 22a. Thereby, the memory cell block X
, A substrate bias is applied to all the memory transistors T01 to T09, and the threshold voltages of the memory transistors T01 to T09 are increased.

On the other hand, as shown in FIG. 7, the memory transistors T11 to T19 of the memory cell block Y have a P-type well island 22b different from the P-type well island 22a of the block X.
Is formed. That is, in the present embodiment, the memory cell block X and the memory cell block Y are junction-separated by forming the P-type well islands 22a and 22b on the N-type semiconductor substrate 21. Then, the substrate contact electrode 36b formed on the P-type well island 22b of the memory cell block Y is connected to the substrate bias circuit 20 via the switch S2 in FIG. As a result, all the transistors T11 in the memory cell block Y
A substrate bias is applied to T19.

As described above, this embodiment has the following features. (1) As shown in FIG. 7, by forming the well islands 22a and 22b for each of the memory cell blocks X and Y, the plurality of memory transistors T01 to T09 and the plurality of memory transistors T11 to T19 are junction-separated. I have. As described above, when the junction is separated for each of the plurality of memory transistors, the switches S1 and S2 for applying the substrate bias are used.
In addition, the wiring and the like can be shared, and the size of the device can be reduced.

(2) All the memory transistors T01 to T09, T11 to T in the memory cell blocks X and Y
By applying a substrate bias to the transistor 19, the threshold voltage of the transistor which has been overerased during data reading can be increased. Thus, when the memory transistor that has been over-erased is not selected, the memory transistor can be reliably turned off, and the problem of excessive erasure (current leakage through the non-selected transistor) can be avoided.

(Third Embodiment) Next, a third embodiment will be described focusing on differences from the first embodiment. FIG. 8 is a circuit diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the present embodiment. In this embodiment, an EEPROM capable of rewriting data in byte units
And a substrate bias can be applied only to the selected memory transistor.

As shown in FIG. 8, the memory cell block X
The read circuit 12 has switches S21 to S29, and the read circuit 13 of the memory cell block Y has switches S31 to S39. Here, the switch S2
1, S24 and S27, each transistor T01 to T01
It is switched whether or not a substrate bias is applied to 03. Also, by the switches S22, S25, S28,
Whether the storage data of each of the transistors T01 to T03 is read or not is switched. Further, switches S23, S
26 and S29, whether or not a gate voltage is applied to each of the transistors T01 to T03 is switched. Similarly, whether or not a substrate bias is applied to each of the transistors T11 to T13 is switched by the switches S31, S34, and S37. Also, switches S32 and S3
In S5, whether or not the storage data of each of the transistors T11 to T13 is read is switched. further,
The switches S33, S36, and S39 switch whether or not to apply a gate voltage to each of the transistors T11 to T13.

Next, the memory transistors T02 and T12
Is selected and the stored data is read out. In this case, the read circuit 12 includes the switch S24
To S26, the readout circuit 13 switches the switch S3
4 to S36 are turned on. At this time, if data "0" is written in the memory transistor T02, the threshold voltage is high, so that the transistor is turned off and no output current flows through the switch S25. Therefore,
The switch S2 is turned on by the read circuit 12, and a substrate bias is applied to the memory transistor T12 via the switch S34. Here, even if the retention characteristics of the memory transistor T12 are deteriorated, the threshold voltage is increased by the application of the substrate bias, and the transistor is turned off. Therefore, the read circuit 13
The storage data "0" of the memory transistor T12 is read via the switch S35, and the switch S1 is turned on. As a result, the substrate bias is applied to the memory transistor T02 via the switch S24, and the threshold voltage increases. At this time, since the switches S21 and S27 are off, the unselected memory transistors T01 and T27
03 is not applied with a substrate bias. Similarly,
Since the switches S31 and S37 are off, no substrate bias is applied to the memory transistors T11 and T13.

Next, the EEPROM in the present embodiment
9 is shown in FIG. 9, and a longitudinal sectional view taken along line CC of FIG. 9 is shown in FIG. In the present embodiment, SOI (Silicon)
An island is formed for each transistor cell using an On Insulator structure and an isolation structure formed by a trench oxide film. That is, as shown in FIG.
And an N-type semiconductor substrate 42 are bonded by bonding via a silicon oxide film (buried oxide film) 43 to form an SOI
A substrate is formed. In the N-type semiconductor substrate 42, an N + -type impurity layer 44 is formed on a contact surface with the buried oxide film 43. Further, a trench 45 is formed in the N-type semiconductor substrate 42 as a semiconductor layer, reaching the buried oxide film 43 from the surface. The trench 45 is filled with an oxide film. Then, as shown in FIG. 9, memory transistors T01 to T03 and T11 to T13 are formed in each region surrounded by the trench 45.

More specifically, as shown in FIG. 10, a P-type well island 47 is formed in each surface region of the N-type semiconductor substrate 42 surrounded by the trench 45. In the surface layer of the P-type well island 47, an N + type source region 48 is provided.
And an N + type drain region 49 are formed at a distance from each other, and further, a substrate contact region 50 is formed at a distance from the N + type drain region 49. LOCOS oxide films 51 are formed on both sides of the substrate contact region 50.

On the N-type semiconductor substrate 42, a floating gate electrode 54 made of polycrystalline silicon is arranged via a gate oxide film 53 as an insulating film. The floating gate electrode 54 is rectangular and has a source region 48.
And the drain region 49 is extended. On the floating gate electrode 54, a rectangular control gate electrode 56 is arranged via a silicon oxide film. Control gate electrode 56 is made of polycrystalline silicon. As shown in FIGS. 9 and 10, the floating gate electrode 54 and the control gate electrode 56
And are arranged in a state of completely overlapping as a planar structure. Note that a silicon oxide film is disposed around the control gate electrode 56 on the semiconductor substrate 42.

A source contact electrode 58 is formed on the source region 48, a drain contact electrode 59 is formed on the drain region 49, and a substrate contact electrode 60 is formed on the substrate contact region 50 with aluminum or the like. Then, the transistors T01 to T03, T11
From T13 to T13, the control gate electrode 56 is
Switches S23, S26, S29, S33,
It is connected to S36 and S39. Further, the source contact electrode 58 in FIG. 9 is grounded. Further, the drain contact electrode 59 is connected to the switches S22 and S2 in FIG.
5, S28, S32, S35 and S38, and the substrate contact electrode 60 is connected to the switches S21 and S in FIG.
24, S27, S31, S34, and S37.

As described above, in the SOI substrate, the memory transistors T01 to T01 are provided for each region partitioned by the trench 45.
T03, T11 to T13 are formed. Then, a substrate bias is applied to each region via the substrate contact electrode 60. Thus, whether or not to apply a substrate bias can be switched for each transistor, and the threshold voltage of only necessary transistors can be increased.

Generally, in an electrically rewritable nonvolatile memory such as an EEPROM, data erasing is performed by applying a high voltage between a floating gate and a semiconductor substrate and flowing an FN tunnel current to a gate oxide film. It is done by that. In addition, adjacent transistor cells are LO
They are separated by a COS oxide film. In this case, if the erasing voltage is too high, the leakage current through the LOCOS oxide film affects adjacent transistor cells. Therefore, conventionally, the erase voltage cannot be increased,
For example, the operation was performed at 12V. Further, since the erasing voltage cannot be increased, the gate oxide film between the floating gate and the substrate has been thinned to about 10 nm. When the gate oxide film is thinned, a leak current (charge loss) through the oxide film occurs, and the oxide film is deteriorated due to a writing or erasing operation.

On the other hand, in the present embodiment, FIG.
As shown in FIG. 0, a configuration is adopted in which adjacent transistor cells are insulated and separated by trenches 45. Therefore, even if the erasing voltage is increased to, for example, 20 V, the adjacent memory transistor is not affected, and the gate oxide film 53 is not affected.
(See FIG. 10). Thus, the deterioration of the gate oxide film 53 due to the writing or erasing operation is suppressed. It is conceivable that the variation of the threshold voltage after erasing is increased by increasing the erase voltage. However, by employing the circuit of FIG. 8, the influence of the variation of the threshold voltage can be avoided.

In this embodiment, adjacent memory transistors are insulated and isolated by one trench 45. However, the present invention is not limited to this. For example, two or more trenches may be insulated and isolated. Is also good.

As described above, this embodiment has the following features. (1) Each of the memory transistors T01 to T03, T11 to T13 is formed by forming the trench 45 in the SOI substrate.
Insulation is separated for each memory transistor, and a substrate bias is applied independently for each memory transistor. In this case, a substrate bias can be applied only to necessary memory transistors, which is practically preferable.

(2) By forming the trench 45 in the SOI substrate, each of the memory transistors T01 to T03, T
Since the insulation is separated every 11 to T13, even if the erase voltage is increased, there is no effect on the adjacent memory transistor. Therefore, a high voltage can be applied at the time of erasing, so that the thickness of the gate oxide film 53 can be increased, and a leakage current (charge loss) through the gate oxide film 53 can be obtained.
In addition, deterioration of oxide film 53 due to writing and erasing operations can be suppressed.

The present invention can be embodied in the following forms other than the above. In the third embodiment, the isolation is performed for each transistor by forming the trench 45 in the SOI substrate. However, the present invention is not limited to this, and a configuration similar to that of the second embodiment may be employed. May be adopted. That is, as shown in FIG. 11, the junction isolation between each transistor cell is performed by forming the P-type well island 47 for each cell in the surface layer portion of the N-type semiconductor substrate 62. Note that each memory transistor is formed on the P-type well island 47 with the same configuration as that of FIG. And each well island 4
A substrate bias can be independently applied to each memory transistor from each of the substrate contact electrodes 60. On the other hand, the separation for each of the memory cell blocks X and Y in the second embodiment may be performed by forming a trench in the SOI substrate.

Further, a structure as shown in FIG. 12 can be employed for separating the nonvolatile memory by junction. That is, in FIG. 12, the P-type semiconductor substrate 6
An N-type well layer 66 is formed in the surface layer portion of No. 4 and a P-type well island 47 is formed in the surface layer portion of the well layer 66.
A memory transistor is formed on the P-type well island 47 with the same configuration as that of FIG. Also in this case, the junction separation of the memory transistor can be performed, and the substrate bias can be applied to the memory transistor having the junction separated.

In each of the above embodiments, the configuration is such that it is determined whether or not a substrate bias is applied between the memory cell block X and the memory cell block Y. However, the present invention is not limited to this. . For example, if any one of the memory transistors in the memory cell blocks X and Y is in a charge injection state (transistor off), a substrate bias may be applied to both the blocks X and Y.

In the second embodiment, the circuit shown in FIG. 3 has a configuration in which a substrate bias is applied to each of the memory cell blocks X and Y. However, the present invention is not limited to this. Specifically, the configuration may be such that a substrate bias can be applied only to the memory transistor on the selected bit line (for example, when the switch S01 is turned on, the transistors T01, T04, T07).

In the above embodiments, 1-bit data is stored in two memory transistors.
It is not limited to this. For example, if 1-bit data is 3
The present invention may be embodied to store in one memory transistor. Specifically, for example, at the time of data reading, if the first memory transistor is off (charge injection state), a substrate bias is applied to the second memory transistor, and the second memory transistor is turned off ( In the case of the charge injection state), a substrate bias is applied to the third memory transistor. Further, when the third memory transistor is off (in a charge injection state), a substrate bias is applied to the first memory transistor. By doing so, the number of memory cells is the same as in the conventional device of FIG. 13, but the data reading accuracy can be improved, which is practically preferable.

In each of the above embodiments, the floating gate electrodes 6, 31, 54 and the control gate electrode 7,
Although the present invention is embodied in a so-called stack-structured nonvolatile memory in which 33 and 56 are arranged in a state of completely overlapping, the present invention is not limited to this. For example, the present invention may be embodied in a simple nonvolatile memory in which a part of a floating gate electrode and a part of a control gate electrode overlap. Of course, the present invention is not limited to the two-layer gate type nonvolatile memory, but may be embodied as a one-layer gate type nonvolatile memory.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment.

FIG. 2 is a cross-sectional view of a transistor cell.

FIG. 3 is a circuit diagram illustrating a schematic configuration of a nonvolatile semiconductor memory device according to a second embodiment.

FIG. 4 is a plan view of a flash memory.

FIG. 5 is a longitudinal sectional view taken along line AA in FIG. 4;

FIG. 6 is a longitudinal sectional view taken along line BB in FIG.

FIG. 7 is a cross-sectional view of a flash memory.

FIG. 8 is a circuit diagram illustrating a schematic configuration of a nonvolatile semiconductor memory device according to a third embodiment.

FIG. 9 is a plan view of an EEPROM.

FIG. 10 is a vertical sectional view taken along line CC in FIG. 9;

FIG. 11 is a cross-sectional view of a transistor cell in another embodiment.

FIG. 12 is a cross-sectional view of a transistor cell in another embodiment.

FIG. 13 is a block diagram showing a schematic configuration of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Well island, 5 ... Gate oxide film as insulating film, 6 ... Floating gate electrode, 10, 1
1, 12, 13 ... Readout circuit as substrate bias applying means, 21 ... Semiconductor substrate, 22a, 22b ... Well island, 30 ... Gate oxide film as insulating film, 31 ... Floating gate electrode, 41, 42 ... SOI substrate Constituent semiconductor substrate, 45 ... trench, 47 ... well island, 53
... a gate oxide film as an insulating film, 54 ... a floating gate electrode, 62 ... a semiconductor substrate, 64 ... a semiconductor substrate, 6
6 ... well layer, T01 to T09, T11 to T19 ... memory transistor.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Noriyuki Iwamori 1-1-1 Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (reference) 5B025 AA03 AB01 AC01 AD04 AD05 AD08 AD09 AE08 5F083 EP02 EP23 ER06 ER16 ER22 GA17 HA02 JA36 NA01 5F101 BA01 BB05 BC01 BD30 BD36 BE02 BE07 BF01

Claims (12)

[Claims] 1. A nonvolatile semiconductor memory device in which a plurality of transistor cells are prepared for one bit, and one bit data is stored in each of the plurality of transistor cells. Data writing means for injecting electric charge into a floating gate electrode disposed via a film; and, as a result of reading data from the transistor cell, if any of the transistor cells is in a charge injection state, a substrate bias is applied to apply a substrate bias. Means,
A non-volatile semiconductor storage device comprising: 2. The data writing means increases a threshold voltage by injecting electric charge into the floating gate electrode to turn off the transistor when reading data. The substrate bias applying means reads data from the transistor cell. 2. The non-volatile semiconductor memory device according to claim 1, wherein if any one of the transistor cells is turned off as a result of the above, a substrate bias is applied to increase the threshold voltage. 3. If two transistor cells are prepared for one bit, and the substrate bias applying means performs data reading, if one of the transistor cells is off,
Apply a substrate bias to the other transistor cell,
3. The method according to claim 2, wherein a substrate bias is applied to the one transistor cell if the transistor cell is turned off as a result of performing data reading with the substrate bias applied. Non-volatile semiconductor storage device. 4. An SOI substrate in which a semiconductor layer is formed via an insulating film on a substrate, wherein the transistor cell is insulated and separated by forming a trench reaching the insulating film in the semiconductor layer. The nonvolatile semiconductor memory device according to any one of claims 1 to 3. 5. The semiconductor device according to claim 4, wherein the trench is insulated and isolated for each transistor cell, and a substrate bias is applied independently for each transistor cell.
3. The nonvolatile semiconductor memory device according to 1. 6. The non-volatile memory according to claim 4, wherein the plurality of transistor cells are insulated and separated by the trench, and a substrate bias is applied to each of the plurality of transistor cells separated by the trench. Semiconductor storage device. 7. The non-volatile semiconductor device according to claim 1, wherein said transistor cell is junction-separated by forming a P-type well island on a surface portion of an N-type semiconductor substrate. Storage device. 8. The transistor according to claim 7, wherein the P-type well island is formed for each transistor cell to separate the junction, and a substrate bias is applied independently for each transistor cell. Nonvolatile semiconductor memory device. 9. The semiconductor device according to claim 1, wherein the P-type well island is formed for each of the plurality of transistor cells to separate the junction, and a substrate bias is applied to each of the plurality of transistor cells separated by the well island. The nonvolatile semiconductor memory device according to claim 7, wherein: 10. The transistor cell is junction-separated by forming an N-type well layer on a surface portion of a P-type semiconductor substrate and forming a P-type well island on a surface portion of the well layer. The nonvolatile semiconductor memory device according to claim 1. 11. The semiconductor device according to claim 10, wherein the P-type well island is formed for each of the transistor cells to separate the junction, and a substrate bias is independently applied to each of the transistor cells. 14. The nonvolatile semiconductor memory device according to claim 1. 12. The semiconductor device according to claim 1, wherein said P-type well island is formed for each of a plurality of transistor cells to separate junctions, and a substrate bias is applied to each of said plurality of transistor cells separated by said well islands. The nonvolatile semiconductor memory device according to claim 10, wherein: