JP2002251320A - Memory control circuit, memory control method and recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manage information that controls a memory by collecting control circuits related to the control peculiar to a memory into an independent configuration. SOLUTION: The memory control circuit for controlling memory operation is provided with a register control unit for performing write access to a particular register and initializing an operation mode that defines the memory operation, a request control unit for making an operation request to the memory on the basis of a prescribed trigger signal after being initialized by the register control unit, and a storage unit for storing the contents of initialization and the operation request with respect to the memory while separating the contents from the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory control circuit and a recording apparatus to which the memory control circuit is applied. In particular, synchronous DRAM (Synchronous DRAM)
Dynamic Random memory, hereinafter referred to as "SDRAM". ) And a memory control circuit for easily and efficiently controlling a mode set for easily performing various settings such as reading and writing for operating the memory, and controlling an operation request, and the memory. It relates to a recording device to which a control circuit is applied.

[0002]

2. Description of the Related Art Conventionally, a memory controlled by a memory control circuit is a semiconductor memory, and a typical example thereof is "SDRAM". The SDRAM is a DRAM that requires an initialization operation. To perform a normal read / write operation, it is necessary to first set a mode.

Here, the mode of the SDRAM will be briefly described. The SDRAM is a memory that receives instructions such as memory read and memory write instructions and inputs and outputs data based on the received instructions in synchronization with an externally applied clock.

The SDRAM incorporates a register called a mode register. By writing a necessary value to the mode register, a control circuit in the SDRAM reads the contents of the mode register and operates in accordance with the operation mode specified by the mode register. The SDRAM operates.

By changing the operation mode in which data is written into the mode register, the SDRAM can change the number of clocks from the input of a request to the output of data, and the number of data to be continuously input / output when inputting / outputting data. Can be changed.

Here, there are four types of modes that can be set in the mode register: “number of bursts”, “CAS latency”, “burst type”, and “opcode”.

[0007] The "burst number" is a value indicating the number of times data is input / output in response to one memory read instruction or memory write instruction. For example, when the number of bursts is designated as "4", it means that four data are sent and received for one instruction.

[0008] "CAS latency" means the number of clocks from when a CAS address (row address) for memory access is received to when the first data is output. The CAS latency is valid only during a memory read operation. Therefore, when the CAS latency is set to “3”, the first data is output three clocks after receiving the CAS address.

The "burst type" indicates a data input / output type, and there are two types, "sequential" and "interleave". The difference between sequential and interleaving is that the order of inputting and outputting data is different.

An "op code" is a register for setting whether or not to perform a burst operation in response to a write operation.

As described above, the writing of the mode in the mode register is an important initialization operation for defining the operation of the SDRAM, and is based on the configuration specific to the SDRAM. If an incorrect mode is set for the SDRAM, an incorrect operation is performed without performing the operation originally expected,
For example, writing and reading of unexpected data are performed, and the operation as a storage device cannot be guaranteed.

Furthermore, the SDRAM has a "self-refresh function". This is a function of automatically refreshing the self-refresh command by using a timer in the SDRAM by asserting a self-refresh command, and is effective in reducing power consumption. At this time, in order to exit this mode, it is necessary to assert a self-refresh end command.

In the memory control specific to the SDRAM as described above, when the connected memory is changed, how to control the mode of the memory has been a problem.

[0014]

According to the memory control circuit of the present invention, an operation mode of a memory to be controlled is set to an initial setting specified by an external request source and to a memory waveform shaping circuit in response to an operation request. Thus, a command waveform is created according to a predetermined timing, a mode is set for a memory, and input / output control of data to / from the memory is performed.

At this time, the memory control is uniformly managed by a control circuit for requesting a mode setting or a self-refresh, which is a special condition setting for operating the memory in a predetermined manner.

That is, a memory control circuit for controlling a memory operation performs a write access to a specific register,
Register control means for performing initial setting of an operation mode for defining the operation of the memory; request control means for performing an operation request to the memory based on a predetermined trigger signal after being initialized by the register control means; Storage means for storing the contents of the initial setting and operation request for the memory separately from the memory.

In the above-mentioned memory control circuit, the register control means outputs an address signal for storing data in the memory and a mode signal defining an operation mode of the memory.

In the above-mentioned memory control circuit, the register control means outputs a trigger signal for synchronizing signal transmission to the request control means.

In the above-mentioned memory control circuit, operation request signals are received from a plurality of memory access request sources that share the memory, and prioritization of processing is determined with the received operation request signals. An arbiter circuit for receiving an output signal output in accordance with the order of processing determined by the arbiter circuit, writing the content of the output signal to the memory, and generating information for driving the memory. And waveform information generating means.

In the above-mentioned memory control circuit, the storage means stores the contents of the initial setting and the operation request setting of the memory to be controlled outside the memory so that even if the memory is changed. , The contents set in the memory can be inherited.

Further, the memory control circuit further includes a refresh controller for controlling a process for erasing information stored in the memory.

Alternatively, a method for driving and controlling a memory control circuit for controlling an operation on a memory includes a method of making a specific memory register write-access and executing an initial setting of an operation mode for defining an operation of the memory. A register control step of causing the register control step to generate a predetermined trigger signal, and executing an operation request to the memory based on the trigger signal; And storing the contents of the initial setting and the operation request in a storage unit separated from the memory.

In the above memory control method, the register control step generates and outputs an address signal for storing data in the memory and a mode signal defining an operation mode of the memory. I do.

In the above-mentioned memory control method, the register control step generates and outputs a trigger signal for synchronizing signal transmission with the request control step.

In the above-mentioned memory control method, operation request signals are received from a plurality of memory access request sources sharing the memory, and prioritization of processing is determined with the received operation request signals. An arbiter step, receiving an output signal output in accordance with the order of the processing determined by the arbiter step, writing the contents of the output signal to the memory, and transmitting information for driving the memory. And generating a waveform information for generating.

Alternatively, a printing apparatus that performs printing by scanning a carriage equipped with a print head on a print medium based on information transmitted from an external device, stores the information transmitted from the external device in the print head. Recording data generating means for converting the recording data into the recording data according to the configuration; and writing and accessing a specific register to control the storage of the converted recording data in the memory; Register control means for performing an operation request to the memory based on a predetermined trigger signal after being initialized by the register control means; and setting the contents of the initial setting and the operation request to the memory to the memory. And storage means for storing separately.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing a memory control circuit according to the present invention, its peripheral circuit configuration, a memory, and an overall configuration of a CPU.

Reference numeral 101 denotes a CPU, and reference numeral 102 denotes an ASIC having a built-in memory control circuit. 103 is CPU and A
This is a CPU interface circuit which is an interface with the SIC 102.

Reference numeral 104 denotes the data processing circuit 1;
Denotes a data processing circuit 2 and 106 denotes a memory control circuit according to the present invention.

Reference numeral 107 denotes a memory to be controlled, which is controlled by the memory control circuit 106. In the case of FIG. 2, the memory is a synchronous DRAM (hereinafter referred to as "SDRAM").

FIG. 1 shows a memory control circuit 10 shown in FIG.
FIG. 6 is a block diagram showing the configuration of a sixth example in detail.

In FIG. 1, the memory control circuit 106 includes a refresh controller 201, a memory control controller 202, an arbiter circuit 203, and a waveform generation circuit 204 as constituent elements.

These components will be described individually.
The refresh controller 201 is for controlling the refresh mode of the SDRAM 107, and the memory controller 202 sets various modes for the SDRAM 107 (mode set) and further executes self-refresh control.

The arbiter circuit 203 includes the data processing circuits 104 and 105 and the refresh controller 2 described above.
01, SDRA with the memory controller 202
The access right to M107 is controlled.

Reference numeral 204 denotes a waveform shaping circuit for creating an access waveform for actually writing the operation specified by any access request source determined by the arbiter circuit 203 in the mode register of the SDRAM 107.

Next, the connection relationship in the memory control circuit 106 will be described. FIG. 3 is a diagram showing in detail a connection relationship inside the memory control circuit. The connection relation of signals between the respective block elements will be described below.

<Input Signal of Arbiter Circuit> In the connection relationship between the CPU interface circuit 103 and the arbiter circuit 203, the CPU interface circuit 103 receives address1 [24: 0] 301, write_data1 [31: 0] 302, and read_data1 [31]. : 0] 303, mode1 [6: 0] 304, request1 305, and ack1 306 are connected to the arbiter circuit 203.

In the connection relationship between the data processing circuit 1 104 and the arbiter circuit 203, the data processing circuit 1 104 outputs address2 [24: 0] 311, write_data2 [31: 0] 312, and read_data2 [31: 0]. ] 313, mode2 [6: 0] 314, request2 315, and ack2 316 are connected to the arbiter circuit 203.

Further, regarding the connection relationship between the data processing circuit 2 105 and the arbiter circuit 203, the data processing circuit 2 105 outputs address3 [24: 0] 321, write_data3 [31: 0] 322, and read_data3 [31: 0]. ] 323, mode3 [6: 0] 324, request3 325, and ack3 326 are connected to the arbiter circuit 203.

The refresh controller 201
In connection with the arbiter circuit 203, signals of address4 [24: 0] 331, mode4 [6: 0] 332, request4333, and ack4334 are connected to the arbiter circuit 203 from the refresh controller 201.

Further, the memory controller 202 and
Regarding the connection relationship with the arbiter circuit 203, signals of address5 [24: 0] 341, mode5 [6: 0] 342, request5 343, and ack5 344 are connected to the arbiter circuit 203 from the memory controller.

<Processing and Output Signal of Arbiter Circuit> As a specific operation example of the arbiter circuit, a case where the CPU interface circuit 103 performs write access to the SDRAM 107 will be described. CPU interface circuit 1
03 outputs an address 301, write data 302, and a mode signal 304 specifying write, and simultaneously transmits a signal for activating a request signal 305 to the arbiter circuit 203.

The arbiter circuit 203 permits the access, and when the access is completed, an ack1 signal (ack signal) 306 is output from the arbiter circuit 203 to the CPU interface circuit 103.

The arbiter circuit 203 includes a CPU interface circuit 103, a data processing control circuit 1104,
The data processing control circuit 2 105, the refresh controller 201, and the memory control controller 202
The priority of the access request to the RAM 7 is determined, and the arbiter circuit 20 is determined according to the determined priority.
3 as address_out [13:
0] 351, write data to write_data_out [31: 0] 352,
A trigger signal trg created from the request signal is output to the mode signal mode_out [6: 0] 354.

The output signals of these arbiters 203 become the input signals of the waveform generation circuit 204.

<Waveform Generation Circuit> The waveform generation circuit 204
The output signal from the arbiter circuit 203 is converted into an access waveform for writing a mode setting value to a specific mode register of the SDRAM 107, and the signal sd_addre
ss [13: 0] 361, sd_data [31: 0] 362, csx [2: 0] 363, rasx36
4. Output as casx365, wex366, dqm [3: 0] 367, cke368.

<Memory Controller> FIG. 4 is a diagram illustrating the memory controller 202 in detail.

Here, reference numeral 101 denotes a CPU.
The following five types of signals are sent from the CPU interface circuit 103 to the CPU interface circuit 103.

Reference numeral 401 denotes a chip select signal cpu_csx from the CPU 101; 402, an address signal cpu_address [24: 0] from the CPU 101;
Bidirectional data bus cpu_data [31: 0], 404 is CP
Read signal cpu_readx from U101, 405 is CPU
This is the write signal cpu_wrtiex from 101.

The CPU interface circuit 103 receives the signal from the CPU 101 and outputs the following six types of signals to the memory controller 202.

That is, the chip select signal block_csx
Signal 411, address signal block_address [24: 0] 412, write data block_write_data [31: 0] 413, read signal blo
ck_rpx415 and the write signal wpx416 are output to the memory controller 202 as output signals.

The CPU interface circuit 103
Is read data from the memory controller 202.
block_read_data [31: 0] 414 is input as an input signal.

<Structure of Memory Controller> FIG.
9 is a flowchart outlining the steps of memory control. Hereinafter, the contents of the memory control will be described with reference to FIGS.

In FIG. 4, the memory controller 2
02 has two main configurations, a register control circuit 420,
It comprises a request control circuit 421.

The register control circuit 420 obtains an address from an address setting register (810 in FIG. 8) prepared inside the register control circuit 420.
Signal and a mode setting register (8 in FIG. 8).
From 20), the mode signal mode5 [6: 0] 342 is output.
By performing a write operation on a specific register of the memory, initialization such as mode setting is performed, and control of the SDRAM is started (step S801).

After the initial setting, the register control circuit 420 outputs a request generation trigger request_trg 422 to the request control circuit 421 (step S).
802).

The request control circuit 421 sends request_tr
When the g422 signal is input, a requet5 343 signal for requesting an operation for the memory is output.
This requet5 343 signal is transmitted to the request control circuit 42
The requet5 343 signal is output from the request setting register (830 in FIG. 8) prepared inside the device 1 (step S803).

Such a memory control controller 20
According to the configuration 2, memory control such as mode setting as a specific condition setting and a request for a self-refresh for operating the memory in a predetermined manner can be uniformly managed.

From the arbiter circuit 203, the ack signal a
When ck5 344 returns, the request signal 343 is disabled.

In controlling the SDRAM 107, the register control circuit 420 specifies an address for mode setting in the SDRAM 107, writes the address in an internal address setting register, and uses the value of the register for mode setting.

In the SDRAM 107, a mode setting register for mode setting is designated, a request operation is performed, and the mode setting of the SDRAM is performed, so that all address information and mode information to be set are stored in the memory control controller. At 202, the AS
Since the data is written in the register of the IC, the contents of the setting can be reconfirmed by reading the register later even if the memory is changed.

The initial setting operation request (S801), operation request (S802), and other data processing requests (steps S804-1, 2-S806) correspond to the arbiter circuit 20.
3 (step S80).
7).

FIG. 5 is a state transition diagram for explaining the operation of the waveform generation circuit 204. In FIG. 5, reference numerals 501 to 507 clearly indicate the correlation between various defined states (modes).

In FIG. 5, the following seven states (modes) are defined.

Reference numeral 501 denotes a reset mode, 502 denotes a read mode, 503 denotes a write mode, 504 denotes a mode set, 505 denotes a self-refresh mode, 506 denotes a self-refresh release mode, and 507 denotes a refresh mode.

The waveform generation circuit 204 outputs the mode signal mode_ou from the arbiter circuit 203 to which the priority order has been determined.
t [6: 0] 354 is received, and based on this signal, it is determined which mode corresponds. Here, the waveform generation circuit 204 generates a unique signal waveform according to the determined mode (step S808).

FIG. 6 exemplarily shows a specific waveform realized in 7 clock cycles by the waveform generation circuit 204. The waveform generated here is the SDRA
The result is output to M107 (step S809).

FIG. 7 shows the waveforms of the waveform generation signal 204
FIG. 9 is a diagram for explaining specific 7-bit allocation of de_out [6: 0].

Mode [0] is for read / write discrimination mode [3: 1] is for data bus width designation mode [6: 4] is for memory operation function designation.

When the memory controller 202 outputs a mode setting request, the function signal ("mode [6: 4]") is set to "100" to generate a waveform required for mode setting. .

In this embodiment, the case where the memory to be controlled is an SDRAM has been described.
It goes without saying that the memory to be controlled is not limited to “SDRAM”. "EDORAM" and "FP
The present invention can be similarly applied to various memories such as a "DRAM" whose operation can be controlled by setting a mode for the memory.

In the state transition diagram of FIG. 5, seven modes are shown. However, the present invention is not limited to these modes. If more various accesses are required, the mode signals must be extended to cope with them. Is easy.

In this embodiment, the refresh controller and the memory controller have been described as having different configurations. However, a unified memory controller may be used. Also in this case, the control target is S
The present invention is not limited to the DRAM, but can be easily coped with by extending the mode signal to cope with various memory accesses.

<Second Embodiment> A recording apparatus to which the memory control described in the first embodiment is applied will be described.

The following is a description of the present invention with reference to the accompanying drawings.
The second embodiment will be described in detail below.

In the embodiments described below, a printer will be described as an example of a recording apparatus using an ink jet recording method.

In the present specification, “recording” (sometimes called “printing”) means not only the case where significant information such as characters and figures are formed, but also whether a person perceives it visually regardless of significance. Regardless of whether or not the image has been exposed so as to be able to perform the process, the case where an image, a pattern, a pattern, or the like is widely formed on a recording medium or a case where the medium is processed is also described.

The “recording medium” is not limited to paper used in a general recording apparatus, but is widely applicable to ink, such as cloth, plastic film, metal plate, glass, ceramics, wood, leather, etc. Things are also represented.

Further, “ink” (sometimes referred to as “liquid”) is to be interpreted widely as in the definition of “recording (printing)”, and by being applied on a recording medium, A liquid that can be used for forming an image, a pattern, a pattern, or the like, processing a recording medium, or processing ink (for example, coagulating or insolubilizing a colorant in ink applied to the recording medium) is used.

<Schematic Description of Apparatus Main Body> FIG. 9 shows an ink jet printer IJ which is a typical embodiment of the present invention.
It is an external appearance perspective view showing the outline of composition of RA. In FIG. 9, the carriage HC that engages with the spiral groove 5004 of the lead screw 5005 that rotates via the driving force transmission gears 5009 to 5011 in conjunction with the forward and reverse rotation of the drive motor 5013 has pins (not shown). Guide rail 50
03 reciprocates in the directions of arrows a and b. The carriage HC includes a recording head IJH and an ink tank IT.
Integrated inkjet cartridge IJC
Is installed.

Reference numeral 5002 denotes a paper holding plate,
The recording paper P is pressed against the platen 5000 over the moving direction of C. Reference numerals 5007 and 5008 denote photocouplers, which are home position detectors for confirming the presence of the carriage lever 5006 in this region and switching the rotation direction of the motor 5013.

Reference numeral 5016 denotes a member for supporting a cap member 5022 for capping the front surface of the recording head IJH.
Reference numeral 15 denotes a suction device that suctions the inside of the cap, and performs suction recovery of the recording head through the opening 5023 in the cap. 5
Reference numeral 017 denotes a cleaning blade. Reference numeral 5019 denotes a member which allows the blade to move in the front-rear direction. These members are supported by a main body support plate 5018. It goes without saying that the blade is not limited to this form and a known cleaning blade can be applied to this example.

Reference numeral 5021 denotes a lever for starting suction for recovery from suction, and a cam 5020 which engages with the carriage.
The driving force from the driving motor is controlled by a known transmission mechanism such as clutch switching.

The capping, cleaning, and suction recovery are configured so that desired operations can be performed at the corresponding positions by the action of the lead screw 5005 when the carriage comes to the area on the home position side. If a desired operation is performed at the timing, any of the embodiments can be applied.

<Description of Control Structure> Next, a control structure for executing the recording control of the above-described apparatus will be described.

FIG. 10 shows an ink jet printer IJRA.
FIG. 3 is a block diagram showing a configuration of a control circuit of FIG. In the figure showing a control circuit, 1700 is an interface for inputting a recording signal, 1701 is an MPU, 1702 is an MPU 1
ROM 701 for storing a control program to be executed by 701
A DRAM 703 stores various data (such as the recording signal and recording data supplied to the head). 17
A gate array (GA) 04 controls supply of print data to the print head IJH, and also controls data transfer between the interface 1700, the MPU 1701, and the RAM 1703. Reference numeral 1710 denotes a carrier motor for transporting the recording head IJH, and reference numeral 1709 denotes a transport motor for transporting the recording paper. Reference numeral 1705 denotes a head driver for driving the recording head, and reference numerals 1706 and 1707 denote motor drivers for driving the transport motor 1709 and the carrier motor 1710, respectively.

The operation of the above control configuration will be described. When a recording signal enters the interface 1700, the gate array 1
The recording signal is converted into recording data for printing between the 704 and the MPU 1701. And the motor driver 1
The printheads 706 and 1707 are driven, and the printhead is driven according to the print data sent to the head driver 1705 to perform printing.

Here, the control program executed by MPU 1701 is stored in ROM 1702.
An erasable / writable storage medium such as an EEPROM may be further added so that the host computer connected to the inkjet printer IJRA can change the control program.

As described above, the ink tank IT and the recording head IJH may be integrally formed to form a replaceable ink cartridge IJC. However, the ink tank IT and the recording head IJH are separated. It may be configured so that only the ink tank IT can be replaced when the ink runs out.

FIG. 11 is an external perspective view showing the structure of an ink cartridge IJC in which the ink tank and the head can be separated. In the ink cartridge IJC, as shown in FIG. 3, the ink tank IT and the recording head IJH can be separated at the position of the boundary line K. Ink cartridge IJC
Is provided with an electrode (not shown) for receiving an electric signal supplied from the carriage HC side when this is mounted on the carriage HC, and the electric signal drives the recording head IJH as described above. Ink is ejected.

In FIG. 11, reference numeral 500 denotes an ink ejection port array. The ink tank IT is provided with a fibrous or porous ink absorber for holding ink.

In the above embodiment, the description has been made assuming that the droplets ejected from the recording head are ink, and that the liquid stored in the ink tank is ink. It is not limited. For example, an ink tank may contain a processing liquid discharged to a recording medium in order to improve the fixability and water resistance of the recorded image or to improve the image quality.

The above-described embodiment is provided with a means (for example, an electrothermal converter or a laser beam) for generating thermal energy as energy used for causing ink to be ejected, particularly in an ink jet recording system. By using a method in which a change in the state of the ink is caused by energy, it is possible to achieve higher density and higher definition of recording.

The typical structure and principle are described in, for example, US Pat. Nos. 4,723,129 and 4,740.
It is preferable to use the basic principle disclosed in the specification of Japanese Patent No. 796. This method can be applied to both the so-called on-demand type and continuous type. In particular, in the case of the on-demand type, liquid (ink)
By applying at least one drive signal corresponding to the recorded information and providing a rapid temperature rise exceeding the nucleate boiling to an electrothermal transducer arranged corresponding to the sheet or the liquid path holding the Since thermal energy is generated in the electrothermal transducer and film boiling occurs on the heat-acting surface of the recording head, bubbles in the liquid (ink) corresponding to this drive signal on a one-to-one basis can be formed. It is valid.

The liquid (ink) is ejected through the ejection opening by the growth and contraction of the bubble to form at least one droplet. When the drive signal is formed into a pulse shape, the growth and shrinkage of the bubble are performed immediately and appropriately, so that the ejection of liquid (ink) having particularly excellent responsiveness can be achieved, which is more preferable.

As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further, if the conditions described in US Pat. No. 4,313,124 relating to the temperature rise rate of the heat acting surface are adopted, more excellent recording can be performed.

[0098] The configuration of the recording head is not limited to the combination of the discharge port, the liquid path, and the electrothermal converter (linear liquid flow path or right-angled liquid flow path) as disclosed in the above-mentioned specifications. The configurations described in U.S. Pat. No. 4,558,333 and U.S. Pat. No. 4,459,600, which disclose a configuration in which the heat acting surface is arranged in a bending region, are also included in the present invention. In addition, Japanese Unexamined Patent Application Publication No. 59-123670 discloses a configuration in which a common slot is used as a discharge section of an electrothermal transducer for a plurality of electrothermal transducers, and an opening for absorbing pressure waves of thermal energy is discharged. A configuration based on JP-A-59-138461, which discloses a configuration corresponding to each unit, may be adopted.

Further, as a full-line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length is determined by combining a plurality of recording heads as disclosed in the above-mentioned specification. This may be either a configuration satisfying the above requirements or a configuration as a single recording head formed integrally.

In addition, not only the cartridge type recording head in which the ink tank is provided integrally with the recording head itself described in the above embodiment but also the apparatus main body, the electrical connection with the apparatus main body is achieved. A replaceable chip-type recording head, which enables a simple connection and supply of ink from the apparatus main body, may be used.

It is preferable to add recovery means for the printhead, preliminary auxiliary means, and the like to the configuration of the printing apparatus described above, since the printing operation can be further stabilized. Specific examples thereof include capping means for the recording head, cleaning means, pressurizing or suction means, preheating means using an electrothermal transducer or another heating element or a combination thereof. It is also effective to provide a preliminary ejection mode for performing ejection that is different from printing, in order to perform stable printing.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, but may be an integral recording head or a combination of a plurality of recording heads. Alternatively, the apparatus may be provided with at least one of full colors by color mixture.

In the embodiment described above, the description is made on the assumption that the ink is a liquid. However, even if the ink solidifies at room temperature or lower, it is possible to use an ink that softens or liquefies at room temperature. Or, in the ink jet method, generally, the temperature of the ink itself is controlled within a range of 30 ° C. or more and 70 ° C. or less to control the temperature so that the viscosity of the ink is in a stable ejection range.
It is sufficient that the ink is in a liquid state when the use recording signal is applied.

In addition, in order to positively prevent the temperature rise due to thermal energy as energy for changing the state of the ink from the solid state to the liquid state,
Alternatively, in order to prevent evaporation of the ink, ink that solidifies in a standing state and liquefies by heating may be used. In any case, the application of heat energy causes the ink to be liquefied by application of the heat energy according to the recording signal and the liquid ink to be ejected, or to start to solidify when reaching the recording medium. The present invention is also applicable to a case where an ink having a property of liquefying for the first time is used.

In such a case, ink is disclosed in JP-A-54-5
No. 6847 or Japanese Patent Application Laid-Open No. Sho 60-71260, in which the porous sheet is opposed to the electrothermal converter in a state of being held as a liquid or solid substance in the concave portions or through holes of the porous sheet. It may be. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

In addition, as a form of the recording apparatus according to the present invention, in addition to one provided as an image output terminal of an information processing apparatus such as a computer as an integrated or separate apparatus, a copying apparatus combined with a reader or the like, It may take the form of a facsimile machine having functions.

[0107]

Another object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus. And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU provided in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the above-described flowchart (FIG. 8).

[0113]

As described above, according to the memory control circuit of the present invention, with respect to the memory to be controlled, the operation mode is set according to the initial setting and operation request specified by the external request source. In the waveform shaping circuit, create a command waveform according to the predetermined timing,
A mode is set for a memory, and input / output control of data to / from the memory can be performed.

It is possible to uniformly manage a mode setting as a specific condition setting and a memory control for making a self-refresh request for operating the memory in a predetermined manner.

Further, the control related to the memory-specific control can be integrated into an independent configuration, and the information for controlling the memory can be managed independently. By requesting the arbiter access rights that are independent of other circuits, even if the memory used changes, only the independent circuit will be changed, and other circuits, which are huge past design assets, will be There is an effect that changes other than the control circuit are not required.

Further, since the functions are independent, even if the memory is changed, the memory controller can be easily changed.

Further, for the arbiter circuit for controlling the access right of the memory, the control of the special memory itself and the same access right control as that of the other circuits also facilitate the design because the design contents are the same. There is also an effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a structure of a memory control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic structure of a memory control circuit according to an embodiment of the present invention.

FIG. 3 is a detailed block diagram showing a connection relation of a memory control circuit according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a detailed connection relationship of a memory control circuit according to the embodiment of the present invention.

FIG. 5 is a state transition diagram for selecting a requested mode in the waveform generation circuit.

FIG. 6 is a diagram illustrating an output waveform for a mode set generated by a waveform generation circuit.

FIG. 7 is a bit assignment diagram of a mode signal.

FIG. 8 is a flowchart outlining a memory control process.

FIG. 9 is a diagram illustrating an appearance of a printer according to a preferred embodiment of the present invention.

FIG. 10 is a block diagram illustrating a control configuration of the printer in FIG. 9;

FIG. 11 is a view showing an ink jet cartridge of the printer in FIG. 9;

[Explanation of symbols]

 101 CPU 102 ASIC 103 CPU I / F circuit 104 Data processing control circuit 1 105 Data processing control circuit 2 106 Memory control circuit 107 SDRAM 201 Refresh controller 202 Memory control controller 203 Arbiter circuit 204 Waveform generation circuit 420 Register control circuit 421 Request control circuit

Claims (13)

[Claims] 1. A memory control circuit for controlling a memory operation, comprising: a register control means for performing a write access to a specific register to initialize an operation mode for defining an operation of the memory; After the initialization, a request control unit that issues an operation request to the memory based on a predetermined trigger signal; and a storage unit that stores the contents of the initialization and the operation request to the memory separately from the memory. A memory control circuit, characterized by: 2. The memory control according to claim 1, wherein said register control means outputs an address signal for storing data in said memory and a mode signal defining an operation mode of said memory. circuit. 3. The memory control circuit according to claim 1, wherein said register control means outputs a trigger signal for synchronizing signal transmission to said request control means. 4. An arbiter circuit for receiving operation request signals from a plurality of memory access request sources sharing the memory, and determining a priority order of processing with the received operation request signals; Waveform information generating means for receiving an output signal output in accordance with the order of processing determined by the arbiter circuit, writing the content of the output signal to the memory, and generating information for driving the memory; The memory control circuit according to claim 1, further comprising: 5. The storage means stores the contents of initial setting and operation request setting of a memory to be controlled outside the memory, and stores the contents of the memory even if the memory is changed. 2. The memory control circuit according to claim 1, wherein said memory control circuit is capable of inheriting said contents. 6. The memory control circuit according to claim 1, further comprising a refresh controller that controls a process for erasing information stored in the memory. 7. The memory control circuit according to claim 1, wherein said memory includes an SDRAM. 8. A method for driving and controlling a memory control circuit for controlling an operation on a memory, the method comprising: writing access to a specific memory register to initialize an operation mode for defining an operation of the memory. A request control step of generating a predetermined trigger signal after being initialized by the register control step, and executing an operation request to the memory based on the trigger signal. A storage step for storing the contents of an initial setting and an operation request for the memory in storage means separated from the memory. 9. The method according to claim 8, wherein the register control step generates and outputs an address signal for storing data in the memory and a mode signal defining an operation mode of the memory. Memory control method. 10. The memory control method according to claim 8, wherein the register control step generates and outputs a trigger signal for synchronizing signal transmission with the request control step. 11. A process for receiving an operation request signal from a plurality of memory access request sources sharing the memory and executing a process of deciding prioritization of a process with the received operation request signal. An arbiter step, and waveform information for receiving an output signal output according to the order of processing determined by the arbiter step, writing the contents of the output signal into the memory, and generating information for driving the memory 9. The memory control method according to claim 8, further comprising: a generating step. 12. A recording apparatus for performing recording by scanning a carriage equipped with a recording head on a recording medium on the basis of information transmitted from an external device, wherein the recording device transmits the information transmitted from the external device to the recording device. A print data generating means for converting the print data into print data adapted to the configuration of the head; Register control means for performing initial setting; request control means for performing an operation request to the memory based on a predetermined trigger signal after being initialized by the register control means; and A storage device, comprising: storage means for storing data separately from a memory. 13. The recording apparatus according to claim 12, wherein the recording head is an inkjet recording head that performs recording by discharging ink.