JP2001030548A - Recorder and method for accessing data therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To share an external circuit with CPUs each having a different representation method at a time when data is represented by plural addresses. SOLUTION: In the case where representation methods at a time when data is represented by plural addresses are different between a CPU and an external circuit, data 82 is outputted to an external device through an endian conversion circuit 1712 that exchanges data stored in a first address with data stored in a second address when accessing data 81 stored in an internal register of the CPU by each address by bridging two addresses, thereby executing communication of the data between the CPU and external circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus and a data access method in the recording apparatus, and more particularly, to an area in which data stored over two addresses can be accessed for each address. TECHNICAL FIELD The present invention relates to a recording apparatus provided with a CPU having a register therein and a data access method in the recording apparatus.

[0002]

2. Description of the Related Art As an information output device in, for example, a word processor, a personal computer, a facsimile, etc., there is a printer for recording desired information such as characters and images on a sheet-like recording medium such as paper or film.

[0003] Various types of printing methods are known for printers. However, ink-jet printing is possible because non-contact printing is possible on printing media such as paper, colorization is easy, and quietness is high. In recent years, the method has attracted special attention. As a configuration, a recording head that ejects ink according to desired recording information is mounted, and recording is performed while reciprocating scanning in a direction perpendicular to the feeding direction of a recording medium such as paper. Are generally widely used because they are inexpensive and easy to miniaturize.

In such a printer, recording data and various control data are transmitted between a register in a CPU for controlling the entire printer and an external circuit. In this case, there are two methods of expressing data with a plurality of addresses: a big endian method in which high-order data is represented by a previous address, and a little endian method in which low-order data is represented by a previous address.

In general, the external circuits and buses of such a printer have a 16-bit configuration, and registers in the CPU for controlling the entire printer also have a 16-bit configuration. Data width)
It has an area that can be performed in 8-bit units for even addresses or odd addresses as well as 16 bits.

Several examples of accessing the register of the CPU will be described below with reference to the drawings. Here, it is assumed that 16-bit access is performed only for two consecutive addresses starting from an even address.

FIG. 1 shows an example of 16-bit access to an even-numbered address of a 16-bit register in a CPU.
A bit area 12 indicates 16-bit external data. The data representation method is a little endian method, in which the 0th bit represents the least significant bit and the 15th bit represents the most significant bit.

As shown, the 0th bit of the 16-bit area 11 is made to correspond to the 0th bit of the 16-bit external data 12, and the first bit of the 16-bit area 11 is set to the first bit of the 16-bit external data 12. 16 bits by associating the bits up to the 15th bit.
Access to the bit area 11 is performed.

FIG. 2 shows an example of 8-bit access to an even-numbered address of a 16-bit register in a CPU. Reference numeral 21 denotes an 8-bit area for an even-numbered address of a 16-bit register in the CPU. Are respectively shown. The data representation system is a little endian system. The 0th bit represents the least significant bit, the 7th bit in the area 21, and the 15th bit in the external data 22.

As shown in the figure, the 0th bit of the 16-bit external data 22 is made to correspond to the 0th bit of the 8-bit area 21, and the first bit of the 16-bit external data 22 is corresponded to the first bit of the 8-bit area 21. The access to the 8-bit area 21 is performed by associating the bits, and in the same manner, sequentially up to the seventh bit.

FIG. 3 shows an example of an 8-bit access to an odd address of a 16-bit register inside the CPU, 31 is an 8-bit area for an odd address of a 16-bit register inside the CPU, and 32 is an external 16-bit register. Data are shown respectively. The data representation method is a little endian method. The 0th bit represents the least significant bit, the 7th bit in the area 31, and the 15th bit in the external data 32.

As shown in the figure, the 0th bit of the 8-bit area 31 is made to correspond to the 8th bit of the 16-bit external data 32, and the 1st bit of the 8-bit area 31 is set to the 9th bit of the 16-bit external data 32. The access to the 8-bit area 31 is performed by associating the bits, and similarly in the same manner up to the seventh bit of the 8-bit area 31 in order.

FIG. 4 shows an example of 16-bit access to an even-numbered address of a 16-bit register in the CPU. Reference numeral 41 denotes a 16-bit register in the CPU.
A bit area 42 indicates 16-bit external data. The data representation method is a big endian method, in which the 0th bit represents the least significant bit and the 15th bit represents the most significant bit.

As shown, the 0th bit of the 16-bit area 41 is associated with the 0th bit of the 16-bit external data 42, and the 1st bit of the 16-bit area 41 is the first bit of the 16-bit external data 42. 16 bits by associating the bits up to the 15th bit.
Access to the bit area 41 is performed.

FIG. 5 shows an example of 8-bit access to an even-numbered address of a 16-bit register in the CPU. 51 is an 8-bit area for an even-numbered address of a 16-bit register in the CPU, and 52 is a 16-bit external address. Data are shown respectively. The data representation method is a big endian method, where the 0th bit represents the least significant bit, the 7th bit in the area 51, and the 15th bit in the external data 52.

As shown, the 0th bit of the 8-bit area 51 is made to correspond to the 8th bit of the 16-bit external data 52, and the 1st bit of the 8-bit area 51 is set to the 9th bit of the 16-bit external data 52. The access to the 8-bit area 51 is performed by associating the bits, and in the same manner, sequentially up to the seventh bit.

FIG. 6 shows an example of an 8-bit access to an odd-numbered address of a 16-bit register in a CPU. Reference numeral 61 denotes an 8-bit area for an odd-numbered address of a 16-bit register in the CPU. Data are shown respectively. The data expression method is a big endian method, in which the 0th bit represents the least significant bit, the 7th bit in the area 61, and the 15th bit in the external data 62.

As shown, the 0th bit of the 16-bit external data 62 corresponds to the 0th bit of the 8-bit area 61, and the 1st bit of the 16-bit external data 62 corresponds to the first bit of the 8-bit area 61. The access to the 8-bit area 61 is performed by associating the bits, and similarly in the same manner up to the seventh bit of the 8-bit area 61.

As described above, if the internal register of the CPU and the external data use the same representation method of expressing data by a plurality of addresses, 16-bit access is performed.
Eight-bit access to even and odd addresses can be performed without any problem.

[0020]

On the other hand, if the internal register of the CPU and the external data use different expressions when one data is represented by a plurality of addresses, data transfer may not be performed normally. .

As an example, access to even addresses in 8-bit units when a little endian CPU is connected to a big endian external circuit will be described with reference to FIG. 2 and FIG.

As shown in FIG. 2, in the little endian CPU, when transferring 8-bit data to an even address, fixed data is set in the 0th to 7th bits of the register and output. On the other hand, as shown in FIG.
The data of the 15th bit from the bit is received as final data.

As described above, the CPU uses the 0th to 7th bits as defined data, whereas the external circuit sets the 8th to 15th bits as defined data. Therefore, 8-bit write transfer to an even address cannot be performed correctly. Similarly, normal access cannot be performed for read operations and access to odd addresses.

Conventionally, for the reasons described above, it is necessary to match the data expression method of the register of the CPU with the data expression method of the external circuit. For this reason, there is a problem that an external circuit cannot be shared for CPUs having different data representation methods. Conversely, once the external circuit is designed, there is a problem that the CPU to be used cannot be freely selected.

The present invention has been made in order to solve the above-described problems. Even when the CPU that controls the entire system and the external circuit use different expressions for expressing data with a plurality of addresses, data transfer is possible. It is an object of the present invention to provide a recording apparatus and a data access method in the recording apparatus which can correctly perform the above.

[0026]

In order to achieve the above object, a recording apparatus according to the present invention performs recording by scanning a carriage equipped with a recording head on a recording medium based on information transmitted from an external device. Control means having therein a register including an area in which data stored over a first and a second address can be accessed for each address; Means provided between the control means and the external circuit for transmitting and receiving data to and from the means, and when accessing the data in the area for each address, the data stored in the first address And data order conversion means for exchanging data with data stored at the second address.

According to the data access method in the recording apparatus of the present invention which achieves the above object, it is possible to access data stored across the first and second addresses for each address. A data access method in a printing apparatus, comprising: a control unit having a register including an area therein, and performing printing by scanning a carriage equipped with a print head on a print medium based on information transmitted from an external device. When the control means accesses the data in the area for each address to transmit / receive data to / from an external circuit, the control means stores the data stored in the first address and the data stored in the second address. And a data order conversion step of exchanging the data with the data.

That is, when accessing the data stored in the register inside the control means over two addresses for each address, the data stored in the first address and the data stored in the second address are stored. The data is transmitted and received between the control means and the external circuit via the data forward conversion means for exchanging the received data.

In this way, the external circuit can be made common even when using different types of control means, that is, little endian and big endian for expressing data by a plurality of addresses. It is possible to reduce restrictions on the selection of a CPU used as a means and the design of an external circuit, thereby reducing the cost of the entire apparatus.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 10 is an external perspective view showing an outline of the configuration of an ink jet printer IJRA which is a typical embodiment of the present invention. Referring to FIG.
13 and the driving force transmission gears 5009-5
The carriage HC that engages with the spiral groove 5004 of the lead screw 5005 rotating via 011 has a pin (not shown), and is supported by the guide rail 5003 and reciprocates in the directions of arrows a and b. In the carriage HC,
An integrated ink-jet cartridge IJC containing a print head IJH and an ink tank IT is mounted.

Reference numeral 5002 denotes a paper holding plate, and a carriage H
The recording paper P is pressed against the platen 5000 over the moving direction of C. Reference numerals 5007 and 5008 denote photocouplers, which are home position detectors for confirming the presence of the carriage lever 5006 in this region and switching the rotation direction of the motor 5013.

Reference numeral 5016 denotes a member for supporting a cap member 5022 for capping the front surface of the recording head IJH.
Reference numeral 15 denotes a suction device that suctions the inside of the cap, and performs suction recovery of the recording head through the opening 5023 in the cap. 5
Reference numeral 017 denotes a cleaning blade. Reference numeral 5019 denotes a member which allows the blade to move in the front-rear direction. These members are supported by a main body support plate 5018. It goes without saying that the blade is not limited to this form and a known cleaning blade can be applied to this example.

Reference numeral 5021 denotes a lever for starting suction for recovery from suction, and a cam 5020 for engaging with the carriage.
The driving force from the driving motor is controlled by a known transmission mechanism such as clutch switching.

The capping, cleaning, and suction recovery are configured so that desired operations can be performed at the corresponding positions by the action of the lead screw 5005 when the carriage comes to the area on the home position side. If a desired operation is performed at the timing, any of the embodiments can be applied.

Next, a control configuration for executing the recording control of the above-described apparatus will be described.

FIG. 11 shows an ink jet printer IJRA.
FIG. 3 is a block diagram showing a configuration of a control circuit of FIG. In the figure showing a control circuit, 1700 is an interface for inputting a recording signal, 1701 is a CPU, 1702 is a CPU 17
ROM for storing a control program executed by 01, 17
Numeral 03 denotes a DRAM for storing various data (such as the recording signal and recording data supplied to the head). 170
Reference numeral 4 denotes a gate array (GA) that controls supply of print data to the print head IJH, and also controls data transfer between the interface 1700, the CPU 1701, and the RAM 1703. Reference numeral 1710 denotes a carrier motor for transporting the recording head IJH, and reference numeral 1709 denotes a transport motor for transporting the recording paper. Reference numeral 1705 denotes a head driver for driving the recording head, and reference numerals 1706 and 1707 denote motor drivers for driving the transport motor 1709 and the carrier motor 1710, respectively.

In this embodiment, the CPU 1701 has a register 1711 therein, and between the CPU 1701 and the external ROM 1702 and the gate array 1704, the endian conversion for converting the expression system of data represented by a plurality of addresses. A circuit 1712 is provided.

The operation of the above control configuration will be described. When a recording signal enters the interface 1700, the gate array 17
Endian conversion circuit 1 for converting a representation system in which data is represented by a plurality of addresses between CPU 04 and CPU 1701
Via 712, a raster-format print signal is converted into print data that matches the nozzle configuration of the print head. Then, the motor drivers 1706 and 1707 are driven, and the printhead is driven according to the print data sent to the head driver 1705 to perform printing.

Here, the control program executed by the CPU 1701 is stored in the ROM 1702.
An erasable / writable storage medium such as an EEPROM may be further added so that the host computer connected to the inkjet printer IJRA can change the control program.

As described above, the ink tank IT and the recording head IJH may be integrally formed to constitute a replaceable ink cartridge IJC. However, the ink tank IT and the recording head IJH are separated. It may be configured so that only the ink tank IT can be replaced when the ink runs out.

Hereinafter, the operation of the endian conversion circuit 1712 for converting the expression method when data is represented by a plurality of addresses in the present embodiment will be described.

The endian conversion circuit 171 of this embodiment
2 determines whether or not the area to be accessed is a preset area. In the case of access to the preset area, data of the 0th bit to the 7th bit and data of the 8th bit to the 15th bit are determined. The data is replaced with the corresponding data. The number of areas to be set is one or more, and a plurality of areas can be set.

FIG. 7 is a diagram showing the operation of the endian conversion circuit 1712 when accessing outside the set area. In the figure, reference numeral 71 denotes a 16-bit area of a 16-bit register in the CPU, where the 0th bit represents the least significant bit and the 15th bit represents the most significant bit. 72
Is 16-bit data external to the CPU, and
The bit indicates the least significant bit, and the fifteenth bit indicates the most significant bit.

When accessing the data area 71 of the 16-bit register, if the data area 71 is not included in the set area, the endian conversion circuit 1712
Output as it is without converting the data order. That is, the data area 71 of the 16-bit register in the CPU
The 0th bit of the non-CPU data area 72 corresponds to the 0th bit of the data area 7 of the 16-bit register in the CPU.
The access is performed by associating the first bit of 1 with the first bit of the non-CPU data area 72, and in the same manner up to the 15th bit.

Next, the operation of the endian conversion circuit 1712 when accessing the designated area will be described with reference to FIG. In the figure, reference numeral 81 denotes a 16-bit area of a 16-bit register in the CPU, where the 0th bit represents the least significant bit and the 15th bit represents the most significant bit. 82 is 16-bit data external to the CPU;
Similarly, the 0th bit represents the least significant bit, and the 15th bit represents the most significant bit.

When accessing the 8 bits from the 0th bit to the 7th bit of the data area 81 of the 16-bit register, if the data area 81 is included in the set area, the endian conversion circuit 1712 Convert the data order and output. That is, the eighth bit of the non-CPU data area 82 is made to correspond to the 0th bit of the data area 81 of the 16-bit register in the CPU, and the first bit of the data area 81 of the 16-bit register in the CPU is stored in the first bit of the non-CPU data area 82. Access is performed by associating 9 bits, and similarly in the same way up to the 7th bit.

Similarly, when accessing the 8 bits from the 8th bit to the 15th bit of the data area 81 of the 16-bit register, if the data area 81 is included in the set area, the endian conversion circuit 1712 is
Convert the data order and output. That is, CPU
The 8th bit of the data area 81 of the internal 16-bit register is made to correspond to the 0th bit of the data area 82 outside the CPU, and the CP
Access is performed by associating the ninth bit of the data area 81 of the 16-bit register in U with the first bit of the non-CPU data area 82, and similarly up to the 15th bit.

FIG. 9 is a diagram showing an example of a memory map of the register 1711 in the CPU 1701 of this embodiment.
As shown, when the register 1711 has 8-bit access areas 901 and 903 and 16-bit access areas 902 and 904, the register 1
If the endian of 711 is the same as the endian of the external circuit, it is not necessary to convert the data order for all the areas 901 to 904, so none of the areas is designated as the setting area.

On the other hand, when the endian of the register 1711 is different from the endian of the external circuit, it is not necessary to change the data order for the 16-bit access area, but it is necessary to change the data order for the 8-bit access area. Since conversion is necessary, the areas 901 and 903 are designated as setting areas.

FIG. 12 is a flowchart showing an area setting process of the endian conversion circuit 1712 of this embodiment. As shown, it is first determined whether the endian of the CPU and the external circuit are different (step S12).
1) If different, it is determined whether or not there is an additional 8-bit access area (step S122). If there is an 8-bit access area, it is designated as a setting area.

On the other hand, if it is determined in step S121 that the endian of the CPU and the external circuit are the same, and if it is determined in step S122 that there is no 8-bit access area, the data order must be converted. Since there is no fishing season, the process ends without specifying the set fishing season.

FIG. 13 is a flowchart showing the processing of the endian conversion circuit 1712 of this embodiment. As shown in the figure, it is determined whether or not the area to be accessed first is the setting area (step S131). If it is the setting area, the data order needs to be changed. It is determined whether it is the 0th bit to the 7th bit (step S132).

If the designated area is the 0th bit to the 7th bit, conversion is performed so that each data corresponds to the 8th to 15th bits (step S133). If it is determined in step S132 that the data is not the 0th bit to the 7th bit, it is determined that the designated area is the 8th bit to the 15th bit, and conversion is performed so that each data corresponds to the 0th to 7th bits. (Step S134).

If it is determined in step S131 that the area to be accessed is not the set area, the data is output as it is without converting the data order, as shown in FIG.

As described above, since the recording apparatus of the present embodiment has such an endian conversion circuit, an external circuit can be shared even when CPUs of different endians are used. Restrictions on the selection of the CPU and the design of the external circuit can be reduced, and the cost of the entire apparatus can be reduced.

[Other Embodiments] In the above embodiment, two kinds of data widths of 16 bits and 8 bits when accessing are described. However, the present invention is not limited to such a case. , 32 bits and 16 bits
It is apparent that the present invention can be similarly applied to a case where access is possible with various data widths.

In the above embodiment, the description has been made assuming that the droplets ejected from the recording head are ink, and that the liquid contained in the ink tank is ink. It is not limited. For example, an ink tank may contain a processing liquid discharged to a recording medium in order to improve the fixability and water resistance of the recorded image or to improve the image quality.

The above-described embodiment is particularly provided with a means (for example, an electrothermal converter or a laser beam) for generating thermal energy as energy used for performing ink ejection even in an ink jet recording system. By using a method in which a change in the state of the ink is caused by energy, it is possible to achieve higher density and higher definition of recording.

The typical configuration and principle are described in, for example, US Pat. Nos. 4,723,129 and 4,740.
It is preferable to use the basic principle disclosed in the specification of Japanese Patent No. 796. This method can be applied to both the so-called on-demand type and continuous type. In particular, in the case of the on-demand type, liquid (ink)
By applying at least one drive signal corresponding to the recorded information and providing a rapid temperature rise exceeding the film boiling to the electrothermal transducer arranged corresponding to the sheet or the liquid path holding the Since thermal energy is generated in the electrothermal transducer and film boiling occurs on the heat-acting surface of the recording head, bubbles in the liquid (ink) corresponding to this drive signal on a one-to-one basis can be formed. It is valid.

The liquid (ink) is ejected through the ejection opening by the growth and contraction of the bubble to form at least one droplet. When the drive signal is formed into a pulse shape, the growth and shrinkage of the bubble are performed immediately and appropriately, so that the ejection of a liquid (ink) having particularly excellent responsiveness can be achieved, which is more preferable.

As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further, if the conditions described in US Pat. No. 4,313,124 relating to the temperature rise rate of the heat acting surface are adopted, more excellent recording can be performed.

As the configuration of the recording head, in addition to the combination of the discharge port, the liquid path, and the electrothermal converter (linear liquid flow path or right-angled liquid flow path) as disclosed in the above-mentioned respective specifications, A configuration using U.S. Pat. No. 4,558,333 or U.S. Pat. No. 4,459,600, which discloses a configuration in which a heat acting surface is arranged in a bent region, is also included in the present invention. In addition, for multiple electrothermal transducers,
JP-A-59-123670 which discloses a configuration in which a common slot is used as a discharge part of an electrothermal transducer, and JP-A-59-123670 which discloses a configuration in which an opening for absorbing a pressure wave of thermal energy corresponds to a discharge part. A configuration based on 138461 may be adopted.

Further, as a full-line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length is determined by combining a plurality of recording heads as disclosed in the above-mentioned specification. This may be either a configuration satisfying the above requirements or a configuration as a single recording head formed integrally.

In addition to the cartridge type recording head in which an ink tank is provided integrally with the recording head itself described in the above embodiment, the recording head is electrically connected to the apparatus main body by being mounted on the apparatus main body. A replaceable chip-type recording head that allows for easy connection and supply of ink from the apparatus body may be used.

It is preferable to add recovery means for the printhead, preliminary auxiliary means, and the like to the configuration of the printing apparatus described above because the printing operation can be further stabilized. Specific examples thereof include capping means for the recording head, cleaning means, pressurizing or suction means, preheating means using an electrothermal transducer or another heating element or a combination thereof. It is also effective to provide a preliminary ejection mode for performing ejection that is different from printing, in order to perform stable printing.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, and the recording head may be formed integrally or by a combination of a plurality of recording heads. Alternatively, the apparatus may be provided with at least one of full colors by color mixture.

In the above-described embodiment, the description is made on the assumption that the ink is a liquid. However, even if the ink solidifies at room temperature or lower, it is possible to use an ink that softens or liquefies at room temperature. Or, in the ink jet method, generally, the temperature of the ink itself is controlled within a range of 30 ° C. or more and 70 ° C. or less to control the temperature so that the viscosity of the ink is in a stable ejection range.
It is sufficient that the ink is in a liquid state when the use recording signal is applied.

In addition, in order to positively prevent the temperature rise due to thermal energy as energy for changing the state of the ink from the solid state to the liquid state, the temperature is positively prevented.
Alternatively, in order to prevent evaporation of the ink, an ink which solidifies in a standing state and liquefies by heating may be used. In any case, the application of heat energy causes the ink to be liquefied by application of the heat energy according to the recording signal and the liquid ink to be ejected, or to start to solidify when reaching the recording medium. The present invention is also applicable to a case where an ink having a property of liquefying for the first time is used.

In such a case, the ink is disclosed in JP-A-54-5
No. 6,847, or Japanese Patent Application Laid-Open No. 60-71260, in which the porous sheet is opposed to the electrothermal converter while being held as a liquid or solid substance in the concave portion or through hole of the porous sheet. It may be. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

The present invention can be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but can be applied to a single device (for example, a copier, a facsimile). Device).

Further, an object of the present invention is to supply a storage medium (or a recording medium) on which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus, and a computer (a computer) of the system or the apparatus. It is needless to say that the present invention can also be achieved by a CPU or an MPU) reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. By executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. It goes without saying that a case where some or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing is also included.

Further, after the program code read from the storage medium is written into the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. Needless to say, the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the above-described flowcharts (shown in FIG. 12 and / or FIG. 13).

[0076]

As described above, according to the present invention, an external circuit can be used in common even when using control means having different expression systems when data is represented by a plurality of addresses. There is an effect that it is possible to reduce restrictions on the selection of a CPU to be used and the design of an external circuit, thereby reducing the cost of the entire apparatus.

[Brief description of the drawings]

FIG. 1 illustrates a 16-bit CPU for a little-endian CPU.
FIG. 4 is a diagram illustrating an example of bit register access.

FIG. 2 is a diagram illustrating an example of 8-bit register access to an even address of a little endian CPU.

FIG. 3 is a diagram illustrating an example of 8-bit register access to an odd address of a little endian CPU.

FIG. 4 is a diagram showing a 16 for a big endian CPU.
FIG. 4 is a diagram illustrating an example of bit register access.

FIG. 5 is a diagram illustrating an example of 8-bit register access to an even address of a CPU in a big endian system.

FIG. 6 is a diagram showing an example of 8-bit register access to an odd address of a CPU of a big endian system.

FIG. 7 is a first diagram illustrating an operation of the endian conversion circuit according to the embodiment;

FIG. 8 is a second diagram illustrating an operation of the endian conversion circuit according to the embodiment;

FIG. 9 is a diagram illustrating an example of a memory map according to the embodiment;

FIG. 10 is a perspective view showing the appearance of a preferred embodiment of the recording apparatus of the present invention.

FIG. 11 is a block diagram illustrating a control configuration of the printing apparatus of FIG. 10;

FIG. 12 is a flowchart illustrating a setting area designation process of the endian conversion circuit according to the embodiment;

FIG. 13 is a flowchart illustrating an operation of the endian conversion circuit according to the embodiment;

[Explanation of symbols]

11, 21, 31, 41, 51, 61, 71, 81 In-register data 12, 22, 32, 42, 52, 62, 72, 82 External data 1701 CPU 1711 Register 1712 Endian conversion circuit

Claims (13)

[Claims] 1. A printing apparatus for performing printing by scanning a carriage equipped with a print head on a print medium based on information transmitted from an external device, wherein the print apparatus extends over first and second addresses. To the stored data,
A control unit having therein a register including an area accessible for each address; an external circuit for transmitting and receiving data to and from the control unit; and an external circuit provided between the control unit and the external circuit, Data access means for exchanging data stored at the first address and data stored at the second address when accessing data in the area for each address. Recording device. 2. The recording apparatus according to claim 1, wherein the data order conversion unit does not exchange data when accessing data other than the area. 3. The recording apparatus according to claim 1, further comprising means for designating the area. 4. The register according to claim 1, wherein the register can store 8-bit data for each address, and the external circuit handles 16-bit data. Recording device. 5. The register stores data across the first and second addresses according to one of a big Indian system and a little Indian system,
5. The recording apparatus according to claim 1, wherein the external circuit transmits and receives data according to the other of the big Indian system and the little Indian system. 6. 6. The recording head includes a plurality of recording elements arranged in a direction substantially orthogonal to the scanning direction.
6. The device according to claim 1, wherein the external circuit transmits and receives data to and from the control unit, and converts information transmitted from the external device into data corresponding to the arrangement of the recording elements. The recording device according to Item. 7. The recording apparatus according to claim 1, wherein the recording head is an inkjet recording head that performs recording by discharging ink. 8. The printing head according to claim 1, wherein the printing head uses thermal energy to eject ink, and includes a thermal energy converter for generating thermal energy to be applied to the ink. Item 7. The recording device according to Item 6. 9. A control unit having therein a register including an area in which data stored across the first and second addresses can be accessed for each address,
A data access method in a recording apparatus that performs recording by scanning a carriage equipped with a recording head on a recording medium based on information transmitted from an external device, wherein the control unit controls data in the area. A data order conversion step of exchanging data stored at the first address and data stored at the second address when data is transmitted / received to / from an external circuit by accessing each address. A data access method in a recording device, characterized in that: 10. The data access method in a recording apparatus according to claim 9, wherein the data order conversion step does not exchange data when accessing data other than the area. 11. The method according to claim 9, further comprising the step of designating the area. 12. The register according to claim 9, wherein the register is capable of storing 8-bit data for each address, and the external circuit handles 16-bit data. Data access method in the recording device. 13. The register stores data over the first and second addresses according to one of a big Indian system and a little Indian system, and the external circuit stores the big Indian system and the little Indian system. 13. The data access method in a recording apparatus according to claim 9, wherein data transmission and reception are performed according to the other system.