JP2002245963A - Data collection method and time-of-flight mass spectrometer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change data collection by a TDC method and data collection by an ADC method over to each other in accordance with the pulse number in a detector signal by using a plural number of systems of TDC circuits by a level detection method. SOLUTION: Threshold value levels of comparators 2 of the TDC circuits A, B are different from each other. A change-over signal is output from a control circuit 20. The change-over signal is 0 at the time of a TDC mode and 1 at the time of an ADC mode. A shift data and a time code are written in an FIFO memory 11 and taken in a computing circuit 30 only in the case when a bit of 1 in value exists in a shift data of a shift register 10 at the time of the TDC mode. The shift data of the shift register 10 is written in the FIFO memory 11 with the time code without fail with timing of a writing signal from a dividing circuit 4 at the time of the ADC mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-of-flight mass spectrometer (Ti) for accelerating an ionized sample, measuring the difference in arrival time at a detector based on the difference in mass, and analyzing the sample.
The present invention relates to a data collection method and apparatus for me of flight mass spectrometer (TOFMS).

[0002]

2. Description of the Related Art Conventionally, a method of collecting TOF data in TOFMS includes analog-to-digital (Anal).
ogue to Digital Converter) system (this system is referred to as an ADC system in this specification) and a time-to-digital (Time to Digital) system (this system is referred to as T
DC system). The ADC method is
The A / D conversion of the spectrum is started from the time at which the ionized sample is accelerated. The TDC method is the time at which ions reach the detector starting from the time at which the ionized sample is accelerated. This is a system in which recording is performed by a stop-otch system.

The ADC method has an advantage that a large amount of ions can be handled because the A / D conversion can be performed from the pulse region to the current region of the detector. On the other hand, if the A / D conversion speed is low, the output pulse of the detector is low. When the width is narrow, the pulse is A /
In order to fail to perform D conversion, it is necessary to operate a high-speed A / D converter with a high-speed clock, which requires a large amount of memory. Even if the A / D converter is high-speed, the operation of the memory is not improved. Since the speed is low, a plurality of control circuits for connecting the A / D converter and the memory, usually eight or more, need to be operated in parallel, and there is a disadvantage that the circuit scale becomes large. Further, the high-speed A / D converter is expensive and has a disadvantage that it is more susceptible to noise than the TDC system.
On the other hand, the TDC method can be set not to count pulses below a certain threshold level, so it is strong against noise,
Also, only the time when the ion arrives at the detector is recorded,
It has the advantage of requiring less memory,
When the pulse is continuous, stop stop operation cannot keep up and count down (dead time: Dead Time).
There is a drawback that the amount of ions that can be measured is small, and it must be narrowed down by the sample introduction system. And TOFM
In S, in order to collect TOF data, one of the ADC system and the TDC system is usually mounted as a standard.

The TDC system includes a system called a leading edge system and a system called a level detection system. The leading edge method is a method in which when a pulse output from a detector has a positive polarity, a rising edge of a pulse is detected, and a time from a start pulse to a point in time when the pulse is detected is recorded. , The detector output is compared with a threshold level, and is binarized as “1” when the detector output is equal to or higher than the threshold level, and as “0” when the detector output is lower than the threshold level. This is a method of continuously inputting data into a serial shift register and recording the time at which “1” is set.

The applicant of the present invention has disclosed Japanese Patent Application No. 11-374.
No. 255 proposed a TOF data collection device based on a TDC method using a level detection method. This is T
It is an object of the present invention to increase the dynamic range of a sample that can be handled by TOFMS when collecting OF data, to enable a small memory capacity, a small circuit scale, and low-cost data collection.

Hereinafter, the configuration proposed in Japanese Patent Application No. 11-374255 will be described. FIG. 5 is a diagram showing the overall configuration of the TOFMS data collection device proposed in the above application, and FIG.
5 is an explanatory diagram of the TDC circuit A of FIG. 5 as an example, and FIGS. 7 and 8 are diagrams illustrating the relationship between a detector signal and a threshold level set for each TDC circuit.

First, referring to FIGS. 5 and 6, TOFMS
Each part of the data collection device for use will be described. The oscillating circuit (OSC) 3 starts generating a clock of a predetermined frequency upon receiving a start pulse from the TOFMS (not shown), which is the starting point of the flight time of the ions of the sample, and the TOFMS
When a stop pulse is received from, the generation of the clock is stopped. Since the time resolution of the TOFMS is determined by the clock frequency of the OSC 3, the OSC 3 generates a clock with a frequency as high as possible, for example, about 1 GHz.
The clock from the OSC 3 is supplied to the frequency dividing circuit 4 and the clock input terminal of the shift register 10 of the TDC circuits A to D. The frequency dividing circuit 4 sets the clock from the OSC 3 to 1
/ 2 ⁿ (n is a natural number) to generate a write signal (write) which is a pulse signal having a value of “1”. The write signal is supplied to the counter 5 and one input terminal of the AND circuit 13 of each TDC circuit as shown in FIG.

The counter 5 counts the number of write signals and outputs the counted value as an m-bit time code. This time code is used as an upper digit of the time from the start pulse when performing time encoding processing for obtaining the time from the start pulse at the position where the pulse is detected in the histogram calculation device 7 as described later. become. This time code needs to be generated during mass spectrometry. The value of the number of bits m is determined by the scan time from the start pulse to the stop pulse supplied from the TOFMS, the clock frequency of the OSC3, and What is necessary is just to determine based on the frequency division ratio of the frequency dividing circuit 4.

The TDC circuits A to D in FIG. 5 have the same configuration except that the threshold level of the comparator 2 is different. Therefore, the TDC circuit A will be described in more detail with reference to FIG. The TOFMS detector signal is supplied to one input of one of four comparators 2 of TDC circuits A to D via a buffer amplifier 1. Comparator 2
The other input is supplied with the digital threshold level given from the control circuit 20 after being converted into an analog signal by the DAC 15.

The comparator 2 compares the output signal level of the buffer amplifier 1 with the threshold level, and when the output level of the buffer amplifier 1 is equal to or higher than the threshold level,
If the output of the comparator 2 is "1", a pulse is detected when the output of the comparator 2 is "1". Then, the output of the comparator 2 is input to the serial-in terminal of the shift register 10.

The shift register 10 is a 2 ⁿ -bit serial-in / parallel-out shift register.
The digital signal from the comparator 2 is taken in at the timing of the clock supplied from the SC 3 to the serial shift clock terminal. When the shift register 10 receives only 2 ⁿ bits, the shift register 10 outputs the data of 2 ⁿ bits from the parallel out.

The OR circuit 12 takes the logical sum (OR) of all the 2 ⁿ bits output from the parallel out of the shift register 10, and if any one of the 2 ⁿ bits has a value of “1”. If there are any bits with a value of "1" in 2 ⁿ bits, "1" is output.

The AND circuit 13 receives the write signal from the frequency divider 4 and the output of the OR circuit 12 and calculates the logical product (AND) of the two. Therefore, both inputs are "
Only when the value is "1", the value of "1" is output from the AND circuit 13, and this is a write signal to the FIFO memory 11. In the present specification, 2 ^n- bit parallel output from the shift register 10 is performed. The data will be referred to as shift data.

The shift data from the shift register 10, the time code from the counter 5, and the output of the AND circuit 13 are input to the FIFO memory 11;
The O memory 11 writes the shift data and the time code only when the write signal output from the AND circuit 13 is “1”. That is, the shift data and the time code are written to the FIFO memory 11 only when at least one bit of the value is “1” in the shift data. Therefore, the memory capacity required for the FIFO memory 11 is (m + 2 ⁿ ) bits.

Since the write signal from the frequency ^dividing circuit 4, that is, the write signal output from the AND circuit 13, matches the number of shift bits of the shift register 10, that is, 2 ⁿ bits, If at least one bit of the value “1” is present in the shifted data to be shifted, the FIFO memory 1 is used once for 2 ⁿ shift data.
1 is to be written.

The histogram calculator 7 sends a read signal (read clock) to the FIFO memory 11 to
A time encoding method that reads data from the memory 11 and decodes the time from the start pulse of the bit whose value in the 2 ⁿ shift data data is “1” based on the read time code and 2 ⁿ shift data. Perform processing. The time encoding process is as follows. First, since the clock frequency of the OSC 3 and the ^dividing ratio of the ^dividing circuit 4 are known, the 2 ⁿ pieces of shift data are obtained from the time code value read from the FIFO memory 11.
It is possible to know from what time to what data from the start pulse. In this sense, the time code is used as the upper digit of the time from the start pulse. Then, the time from the start pulse of the bit is obtained according to the number of the bit having the value "1" in the shift data. This is the lower digit of the time from the start pulse. Then, the histogram calculation device 7 stores the time data of the detected pulse obtained as a result of the time encoding process.

When performing mass spectrometry, one sample is scanned a plurality of times. The above-described processing is performed each time, and time-encoded time data is accumulated for each scan. Then, when the measurement is completed, the histogram calculation device 7 creates a histogram by counting the accumulated time data of the detection pulse for each scan by counting the number of time data having the same time from the start pulse. This gives a spectrum. In this specification, this is referred to as spectrum development or spectrum development.

The components of the TOFMS data collection device have been described above. Next, the overall operation will be described. First, different threshold levels are set in the comparators 2 of the TDC circuits A to D, respectively.

When the OSC 3 receives the start pulse from the TOFMS, it starts oscillating the clock. At this time, the detector signal is simultaneously transmitted through the buffer amplifier 1 to each TD.
It is input to one of the comparators 2 of the C circuits A to D. The output of the buffer amplifier 1 is binarized by each comparator 2. Shift register 10 of each TDC circuit
Sequentially captures the binary signal from the comparator 2 at the timing of the clock supplied from the OSC 3 and sequentially shifts the binary signal by the clock. When the shift register 10 of each TDC circuit shifts by 2 ⁿ bits, a write signal is generated from the frequency ^dividing circuit 4 and supplied to the counter 5 and the AND circuit 13.

At this time, if at least one bit having a value of “1” is present in the 2 ⁿ -bit shift data,
Since the output of the D circuit 13 becomes “1”, the FIFO memory 11 writes the shift bit and the time code from the counter 5. If there is no bit having a value of "1" in the shift data, the output of the AND circuit 13 becomes "0", so that the FIFO memory 11 does not write the shift data and the time code. The above operation is performed by the TDC circuits A to
D is performed in each of the four TDC circuits.

The histogram calculator 7 sends a read signal to the FIFO memory 11 of each TDC circuit at predetermined intervals to read data from the FIFO memory 11, performs time encoding, and converts the obtained time data. save. The above operation is repeated for each scan, and time data is accumulated for each TDC circuit system every scan. Then, the histogram calculation device 7
Performs spectrum expansion processing.

FIGS. 7 and 8 show the relationship between the detector signal and the four threshold levels, an example of shift data written to the FIFO memory 11, and an example of a histogram. The horizontal axis in the figure is time. In the figure, for the sake of convenience, FIG. 7 and FIG. 8 are divided, but these are assumed to be continuous. FIG.
(A), level 1, level 2, level 3,
Level 4 is the threshold level of the comparator 2 of the TDC circuit A, TDC circuit B, TDC circuit C, and TDC circuit D in FIG. FIGS. 7 and 8 show a case where n = 4.

Assuming that the detector signals are as shown in FIGS. 7A and 8B, the 16-bit shift data written in the FIFO memories 11 of the TDC circuits A to D is as shown in FIG. (B) and FIG. 8 (b), and the histogram created by the histogram calculation circuit 7 is as shown in FIGS. 7 (c) and 8 (c). From FIG. 7C and FIG. 8C, it can be seen that information on the height and width of each pulse of the detector signal is obtained. That is, the arrival time of the pulse from the detector, the pulse height, and the pulse width are measured simultaneously.
This is spectral expansion.

Although four TDC circuits are used in FIG. 5, two or more TDC circuits may be used. Of course, more than four TDC circuits may be used, and the more TDC circuits are used, the closer the spectrum developed to the actual spectrum.

As described above, according to the configurations shown in FIGS. 5 and 6, the detector signals are discriminated at a plurality of threshold levels by using a plurality of TDC circuits, and each discriminated signal is discriminated. Input to each serial-in / parallel-out shift register, and read out the time from clock start and shift data on condition that there is a discriminated signal input to the shift register every time a certain number of bits are shifted by the shift clock. Recording, the arrival time, pulse width, and pulse height of the pulse from the detector can be measured simultaneously, the dynamic range of the sample that can be handled by TOFMS is increased, and less memory, smaller circuit scale, and lower cost are used. It is possible to collect data at

[0026]

As described above, in the TDC system, the presence or absence of a pulse in a detector signal is detected by binarizing the detector signal at a threshold level. Since the time from the start pulse of the detected pulse is recorded, there is an advantage that the data amount is small.However, when there are many pulses in the detector signal, the data amount becomes large, and furthermore, the spectrum expansion is performed. Takes a long time, so the advantage that the data amount is small is lost. Furthermore, since the TDC method detects the presence or absence of a pulse in the detector signal, the TD
Data obtained by the C circuit basically does not have information in the pulse height direction. On the other hand, the ADC method has a large data amount, but the obtained digital data includes information in the pulse height direction. Then, when the number of pulses in the detector signal is small, the TDC method is advantageous. However, when the number of pulses is large, the data amount is large even in the TDC method, and it takes time for spectrum expansion. It can be said that it is more advantageous. If the amount of data is large, the amount of data can be converted to ADC using the TDC method.
There is no difference in the system, and according to the ADC system, T
In the DC method, information on the pulse height that cannot be obtained basically can be obtained.

In the TDC system, basically, information on the pulse height cannot be obtained as described above.
As shown in FIG.
If the threshold levels of the comparators of the DC circuit are different from each other, information on the pulse height can also be obtained. For example, the height of the time position of the arrow indicated by x in FIG.
The level 4 bit, that is, the value at that position of the shift data obtained by the TDC circuit D is the most significant bit, and the level 1
, That is, the value at the position of the shift data obtained by the TDC circuit A is represented as “0011” as the least significant bit, and indicates the pulse height at the position.
That is, in this case, the pulse height can be expressed in four stages, which corresponds to a 2-bit ADC. As described above, it is understood that a function equivalent to that of the ADC method can be provided by using a plurality of TDC circuits and making the threshold levels of the comparators different from each other.

Therefore, the present invention uses a plurality of TDC circuits based on the level detection system, and enables switching between data collection based on the TDC system and data collection based on the ADC system in accordance with the number of pulses in the detector signal. It is an object of the present invention to provide a data collection method and apparatus for a time-of-flight mass spectrometer capable of exhibiting the advantages of both the system and the ADC system.

[0029]

In order to achieve the above object, a data collection method for a time-of-flight mass spectrometer according to the present invention has a plurality of different detector signals. Each signal binarized by a threshold level is input to each serial-in / parallel-out shift register, and each time a shift clock shifts a predetermined number of bits to output shift data, the ion of the sample is changed. A time code indicating a time from a start pulse serving as a starting point of a flight time, and a data collection method for a time-of-flight mass spectrometer in which a write signal to a memory is generated, wherein a bit of a predetermined value is included in the shift data. A first mode in which the shift data and the time code at that time are written into the memory on condition that the shift data and the time code at that time are stored. Wherein the second mode for writing always the memory when the signal write and de are generated have been made can be switched. The data collection device for a time-of-flight mass spectrometer according to the present invention is described in claim 2.
As described, a comparator that binarizes a detector signal based on a threshold level, and a serial that receives a signal binarized by the comparator and outputs shift data as a parallel output every predetermined number of bits shifted by a shift clock An in-parallel out shift register, a frequency divider that divides the shift clock and generates a write signal when the shift register shifts the predetermined number of bits, and a write signal generated from the frequency divider. A counter for counting and generating a time code indicating a time from a start pulse which is a starting point of a flight time of ions of the sample, a first logic circuit for calculating a logical sum of all bits of the shift data, , A second logic circuit that calculates the logical product of the frequency divider circuit, and a signal of a predetermined value output from the second logic circuit. A data collection device for a time-of-flight mass spectrometer, comprising a plurality of TDC circuits each including a memory for writing shift data from the shift register and a time code from the counter. The threshold levels of the comparators are different from each other, and a switching signal generating means for switching the mode is provided. A switching signal from the switching signal generating means is input to a first logic circuit of each TDC circuit, The first logic circuit is characterized in that the logical sum of all bits of the shift data and the switching signal is calculated. The data collection device for a time-of-flight mass spectrometer according to claim 3, wherein the value of the switching signal is binarized by a comparator of a predetermined TDC circuit in a plurality of TDC circuits. Is set automatically based on

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a first embodiment of a data collection device for a time-of-flight mass spectrometer according to the present invention. In FIG. 1, components equivalent to those shown in FIG. 6 are denoted by the same reference numerals, and redundant description will be minimized.

In FIG. 1, two TDC circuits, a TDC circuit A and a TDC circuit B, are provided. Here, it is assumed that the frequency dividing ratio of the frequency dividing circuit 4 is 1/8. It is assumed that the threshold level 1 is given to the comparator 2 of the TDC circuit A from the control circuit 20, and the threshold level 2 larger than the threshold level 1 is given to the comparator 2 of the TDC circuit B.

First, the configuration of the configuration shown in FIG. 1 that is different from the conventional TOFMS data collection device shown in FIG. 6 will be described. In this TOFMS data collection device,
The operator starts data collection from an input device (not shown).
It sets whether to use the DC method or the ADC method. When it is determined that the number of pulses in the detector signal is small, the TDC method may be set. When it is determined that the number of pulses is large, the ADC method may be set. Less than,
The mode of collecting data by the TDC method is called TDC mode, and the mode of collecting data by the ADC method is AD mode.
It is called C mode.

The control circuit 20 sets the value of the switching signal to "1" when the ADC mode is set, and sets the switching signal to "0" when the TDC mode is set.
This switching signal is supplied to the OR circuit 12 of the two TDC circuits.
Is input to the arithmetic circuit 30. The OR circuit 12 also receives 2 ⁿ -bit, in this case, 8-bit shift data from the parallel out of the shift register 10. Therefore, in this device, the OR circuit 12 takes the logical sum of the shift data of the shift register 10 and all the bits of the switching signal, and at least one of the bits has a value of "".
Only when there is a bit of “1”, a signal with a value of “1” is output.The operation of the arithmetic circuit 30 is switched based on a switching signal.This point will be described later. Is the same as

The operation will be described below. Now TD
Assuming that the C mode is set, the control circuit 20 outputs the value of the switching signal as “0”.

When the OSC 3 receives the start pulse from the TOFMS, it starts oscillating the clock. At this time, the detector signal is simultaneously transmitted through the buffer amplifier 1,
It is input to one of the comparators 2 of the TDC circuits A and B. The output of the buffer amplifier 1 is binarized by each comparator 2. The shift register 10 of each TDC circuit sequentially takes in the binary signal from the comparator 2 at the timing of the clock supplied from the OSC 3,
It is shifted sequentially by the clock. And each TD
In the shift register 10 of the C circuit, predetermined bits,
Here, when shifting by 8 bits, a write signal is generated from the frequency dividing circuit 4, and the counter 5 and the AND circuit 1
3 is supplied.

At this point, if at least one bit of the value "1" is present in the shift data output to the parallel out of the shift register 10 of the TDC circuit A, the output of the OR circuit 12 becomes "1". Therefore, the FIFO memory 11 writes the shift data and the time code in response to the write signal from the AND circuit 13. However, if there is no bit having a value of “1” in the shift data, the write signal is not output from the AND circuit 13, so that the FIFO memory 11
Does not write shift data and time code.

Similarly, at this point, even one of the shift data in the shift register 10 of the TDC circuit B has a value of “1”.
, The output of the OR circuit 12 becomes “1”, so that the write signal from the AND circuit 13
The O memory 11 writes the shift data and the time code. However, when there is no bit having a value of “1” in the shift data, the write signal is not output from the AND circuit 13, so that the FIFO memory 11 does not write the shift data and the time code. And the arithmetic circuit 3
0 is the FIFO memory 1 of each TDC circuit every predetermined cycle.
1 to read data from the FIFO memory 11, perform time encoding, and save the obtained time data. That is, in the case of the TDC mode, the same operation as the conventional histogram calculation device is performed.

The above operation is repeated for each scan.
The arithmetic circuit 30 includes a TDC circuit A,
Time data is accumulated for each system of B. And
The arithmetic circuit 30 performs a spectrum expansion process based on the accumulated time data. As is apparent from the above, when the value of the switching signal is "0", the same operation as the above-described conventional operation is performed.

FIG. 2 shows a relationship between the detector signal and the two threshold levels in the TDC mode, and an example of shift data written in the FIFO memory 11. 2 is the same as that shown in FIGS. 7 (b) and 8 (b), but FIG. 2 shows an example according to the configuration of FIG.

FIG. 2A shows an example of two threshold levels and a detector signal. In FIG. 2A, "level1", "le
"vel2" is a threshold level set in the comparator 2 of the TDC circuits A and B, respectively. The horizontal axis represents a write signal (write) output from the frequency divider 4.
Is also shown. If the detector signal is as shown in FIG. 2A, the FIFO memory 1 of each TDC circuit
The shift data written to 1 and taken into the arithmetic circuit 30 is as shown in FIG. In FIG. 2B, “level1” and “level2” are T
The shift data is written to the FIFO memories 11 of the DC circuits A and B. The time code is omitted. As can be easily understood from FIG. 2B, the amount of data recorded in the arithmetic circuit 30 is small in the TDC mode. Therefore, the time required for time encoding and spectrum expansion in the arithmetic circuit 30 can be shortened.

The above is the operation in the TDC mode. Next, the operation in the ADC mode will be described. AD
When the C mode is set, the control circuit 20 outputs the value of the switching signal as “1”. Thereby, each TDC
The output of the OR circuit 12 of the circuit is always "1",
The O memory 11 always outputs
The time code from the counter 5 and the shift register 10
Write shift data from.

Also, in this case, the arithmetic circuit 30
On the basis of the shift data fetched from the IFO memory 11, processing in a conventionally well-known ADC method is performed to restore a spectrum.

When the OSC 3 receives the start pulse from the TOFMS, it starts oscillating the clock. At this time, the detector signal is simultaneously transmitted through the buffer amplifier 1,
It is input to one of the comparators 2 of the TDC circuits A and B. The output of the buffer amplifier 1 is binarized by each comparator 2. The shift register 10 of each TDC circuit sequentially takes in the binary signal from the comparator 2 at the timing of the clock supplied from the OSC 3,
It is shifted sequentially by the clock. And each TD
In the shift register 10 of the C circuit, predetermined bits,
Here, when shifting by 8 bits, a write signal is generated from the frequency dividing circuit 4, and the counter 5 and the AND circuit 1
3 is supplied.

In this case, since "1" is always output from each OR circuit 12, a write signal is always output from the AND circuit 13. Therefore, the shift register 1 of the TDC circuit A at the time when the write signal is generated
The shift data of 0 and the time code generated by the counter 5 at that time are always written to the FIFO memory 11 every time a write signal is generated. Similarly, the shift data of the shift register 10 of the TDC circuit B at the time when the write signal is generated and the time code at that time are written to the FIFO memory 11 of the TDC circuit B.

Then, the arithmetic circuit 30 sends a read signal to the FIFO memory 11 of each TDC circuit at a predetermined cycle, reads shift data and time code from the FIFO memory 11, and stores them. At the time of storing the shift data, the time axis is made coincident, and the bit fetched from the FIFO memory 11 of the TDC circuit A is set as the lower bit, and the bit fetched from the FIFO memory 11 of the TDC circuit B is set as the upper bit, and the 2-bit data is stored. It is only necessary to store the data in the order in which the data is fetched from the FIFO memory 11 of each TDC circuit. This is because the order fetched from the FIFO memory 11 is the same as the time order from the start pulse of the detector signal.

The above operation is repeated for each scan. As a result, the shift data from the TDC circuits A and B are accumulated in the arithmetic circuit 30 every two scans in this case in two bits. And the arithmetic circuit 30
Is based on the accumulated shift data,
The same processing as that performed in the C method is performed to restore the spectrum shape. In this ADC mode, since the spectrum can be restored using only the shift data, no time code is used for the spectrum restoration.

FIG. 3 shows a relationship between a detector signal and two threshold levels in the ADC mode, and an example of shift data written in the FIFO memory 11. FIG. 3A shows an example of two threshold levels and a detector signal. FIG. 3 (a)
, “Level1” and “level2” are threshold levels set in the comparator 2 of the TDC circuits A and B, respectively. The horizontal axis also shows the timing of the write signal output from the frequency dividing circuit 4. When the detector signal is as shown in FIG. 3A, the shift data written in the FIFO memory 11 of each TDC circuit and taken into the arithmetic circuit 30 is as shown in FIG. 3C.
In FIG. 3C, “level1” and “level2” are shift data which are taken into the arithmetic circuit 30 from the TDC circuits A and B and recorded. For example, as described above, the bits output from the TDC circuit A and recorded, that is, the bits binarized at the threshold level 1 are the lower bits, the bits output from the TDC circuit B and recorded,
That is, if the bits binarized at the threshold level 2 are recorded as the upper bits, the intensity of the detector signal at the time position indicated by y in FIG. 3C is represented by “01” and two bits. Will be.

FIG. 3B shows, for comparison, shift data recorded in the TDC mode when the detector signal is as shown in FIG. 3A. In FIG. 3B, “level1” and “level2” are respectively
From the FIFO memories 11 of the TDC circuits A and B to the arithmetic circuit 3
This is shift data that is taken into 0. Comparing FIG. 3B and FIG. 3C, the data amount is smaller in the TDC mode, but when the number of pulses in the detector signal is large, AD
It can be seen that there is not much difference from the case of the C mode. Considering the time required for time encoding processing and spectrum expansion processing in the TDC mode and the time required for spectrum restoration in the ADC mode, when there are many pulses in the detector signal, A
The DC mode is more advantageous than the TDC method.

Although two TDC circuits are provided in FIG. 1, it goes without saying that more TDC circuits may be provided. Then, as described above, FIG.
If four TDC circuits are provided and four threshold levels are set as shown in FIG.
DC can be performed.

The above is the first embodiment. Next, the second embodiment of the data acquisition apparatus for a time-of-flight mass spectrometer according to the present invention will be described.
The configuration of this embodiment will be described with reference to FIG. In the configuration shown in FIG. 1, the operator sets the TDC mode in advance,
Whether the mode is set to the DC mode is set. In the second embodiment, whether the mode is set to the TDC mode or the ADC mode can be automatically set. for that reason,
The configuration shown in FIG. 4 includes a comparison circuit 40 and a counter 41. Others are the same as those shown in FIG.

In this apparatus, first, a prescan is performed.
In this case, the operator may issue a prescan instruction from an input device (not shown). When a pre-scan instruction is given, the control device 20 instructs each unit to perform a pre-scan operation. Specifically, at the time of pre-scan, the control circuit 20 operates the counter 41 and the comparison circuit 40, and makes the operation circuit 30 inoperative.

The counter 41 takes in the output of the comparator 2 of the TDC circuit A at the time of the pre-scan, and counts the number having the value "1". On the other hand, the comparison circuit 40
, A threshold value is given, and the threshold value is compared with the count value of the counter 41 to determine the value of the switching signal. Specifically, when the count value of the counter 41 is equal to or greater than the threshold value, the ADC mode is set and the value of the switching signal is set to “1”. When the count value is less than the threshold value, the TDC mode is set and the switching signal is set. The value is output as "0". The switching signal is supplied to the OR circuit 12 of each TDC circuit.
Is supplied to the arithmetic circuit 30. That is, in this embodiment, TD is determined based on the number of pulses detected by the TDC circuit A.
It is determined whether to use the C mode or the ADC mode.

When the value of the switching signal is determined in this manner, the comparison circuit 40 and the counter 41 are disabled by the control circuit 20 during the subsequent scan for mass spectrometry. does not change.
Operation in ADC mode when the value of the switching signal is "1", TDC when the value of the switching signal is "0"
The operation in the mode is the same as that in the first embodiment described above, and the description is omitted.

As described above, according to the data collection device for a time-of-flight mass spectrometer described in the first and second embodiments, one TOFMS data collection device can operate in the TDC mode. It is possible to switch between the ADC mode and the TDC mode when the number of pulses in the detector signal is small or predicted to be small, and it is predicted that the number of pulses in the detector signal is large or large. In this case, the ADC mode can be set, and the advantages of both the TDC method and the ADC method can be exhibited.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a data collection device for a time-of-flight mass spectrometer according to the present invention.

FIG. 2 shows a relationship between a detector signal and two threshold levels in a TDC mode in the configuration shown in FIG.
FIG. 3 is a diagram illustrating an example of shift data written in an O memory.

FIG. 3 shows a relationship between a detector signal and two threshold levels in an ADC mode in the configuration shown in FIG. 1, an example of shift data written to a FIFO memory 11, and TDC.
It is a figure showing comparison with the time of mode.

FIG. 4 is a diagram showing a configuration of a second embodiment of a data collection device for a time-of-flight mass spectrometer according to the present invention.

FIG. 5 is a diagram showing an overall configuration of a data collection device for a time-of-flight mass spectrometer proposed by the present applicant.

FIG. 6 is an explanatory diagram exemplifying a TDC circuit A in FIG. 5;

FIG. 7 is a diagram illustrating a relationship between a detector signal and a threshold level set for each TDC circuit.

FIG. 8 is a diagram illustrating a relationship between a detector signal and a threshold level set for each TDC circuit.

[Explanation of symbols]

1 ... buffer amplifier, 2 ... comparator, 3 ... OSC,
4 frequency dividing circuit, 5 counter, 7 histogram operation device, 10 shift register, 11 FIFO memory, 1
2 OR circuit, 13 AND circuit, 15 DAC, 20
... Control circuit, 30 ... Operation circuit, 40 ... Comparison circuit, 41 ...
counter.

Claims (3)

[Claims] 1. A detector signal is binarized by a plurality of threshold levels different from each other, each binarized signal is input to each serial-in / parallel-out shift register, and a predetermined number of bits are shifted by a shift clock. Each time the shift data is output, the time code indicating the time from the start pulse which is the starting point of the flight time of the ions of the sample, and the data collection method for a time-of-flight mass spectrometer in which a write signal to the memory is generated. A first mode in which the shift data and the time code at that time are written into the memory on condition that there is a bit of a predetermined value in the shift data; and the shift data and the time code at that time. And a second mode for writing to the memory whenever a write signal is generated. Time-of-flight mass spectrometer data collection method. 2. A comparator for binarizing a detector signal according to a threshold level, and a serial signal which receives a signal binarized by the comparator and outputs shift data as a parallel out every predetermined number of bits shifted by a shift clock. An in-parallel out shift register, a frequency divider that divides the shift clock and generates a write signal when the shift register shifts the predetermined number of bits, and a write signal generated from the frequency divider. Count,
A counter for generating a time code indicating a time from a start pulse serving as a starting point of a flight time of ions of the sample, a first logic circuit for calculating a logical sum of all bits of the shift data, and a first logic circuit. A second logic circuit for calculating a logical product of the frequency dividing circuit; and when a signal of a predetermined value is output from the second logic circuit, shift data from the shift register and time code from the counter. A data collection device for a time-of-flight mass spectrometer having a plurality of TDC circuits each including a memory for writing the data, wherein threshold levels of respective comparators of the plurality of TDC circuits are different from each other, and a mode is switched. Switching signal generating means, and the switching signal from the switching signal generating means
A data collection device for a time-of-flight mass spectrometer, which is input to a first logic circuit of a C circuit, wherein the first logic circuit calculates a logical sum of shift data and all bits of a switching signal. 3. The method according to claim 1, wherein the value of the switching signal is a plurality of TDs.
3. The data collection device for a time-of-flight mass spectrometer according to claim 2, wherein the data is automatically set based on a signal binarized by a comparator of a predetermined TDC circuit in the C circuit.