JP2002237596A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield by employing the optimum processes of the TFT in the active matrix type liquid crystal display fabricated by using the TFT, in order to reduce the production cost, while forming a GOLD structure. SOLUTION: A first impurity region 104 is formed in a region, where only TaN 103 is formed on a gate insulating layer 102 and a second impurity region 105 is formed outside of the region 104 in a semiconductor layer 101. A channel region 107 is formed in a region where the TaN 103 and a W106 are formed. This method provides the conditions with which the first impurity region 104 and the second impurity region 105 can be formed at the same time, in the step of impurity doping.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal having a thin film transistor (hereinafter referred to as TFT) in which an active layer in which a channel region is formed on a substrate having an insulating surface is formed of a polysilicon layer, and a pixel portion. The present invention relates to a method for manufacturing a display device.

[0002]

2. Description of the Related Art The recognition of liquid crystal displays (liquid crystal televisions) has been dramatically improved in recent years. It was in 1995 that large TVs of the 10-inch class and above appeared for the first time. In the next five years, LCDs have become a place where many consumers know. However, in order to raise awareness of the market, it is premised that "type 1 = 10,000 yen" is realized.

The liquid crystal display of the active matrix drive type is becoming mainstream due to the difference in operation speed. Among them, TFTs having an active layer of a semiconductor film having a crystal structure (hereinafter, referred to as a crystalline semiconductor) (typically, crystalline silicon or polycrystalline silicon) are preferably used. This is because the TFT using the crystalline semiconductor has high field-effect mobility, so that various functional circuits can be formed on the same glass substrate, and a TAB (Tape) is formed around the pixel region.
Automated bonding (COM) method and COG (Chip on Glass)
This is because it is not necessary to mount a driver IC or the like using the method.

As described above, the TF using the crystalline semiconductor
Although the advantage of T is great, the functional circuit is formed on the basis of a CMOS circuit composed of an n-channel TFT and a p-channel TFT, and thus has the disadvantage of increasing the number of steps. Obviously, the increase in the number of steps not only causes an increase in the manufacturing cost but also lowers the manufacturing yield. Among them, with the increase in processes,
It is better that the movement of the substrate from device to device is small. For example, if a substrate is put into one device once, the substrate is processed, and then processed by another device after being released to the atmosphere, the amount of work and the moving distance of the substrate increase, resulting in an increase in time loss. Decrease manufacturing yield. Obviously, the larger the substrate, the greater the burden as described above.

[0005] On the other hand, in order to improve the reliability of a TFT, it is a major problem to reduce off-current or prevent deterioration. TF for reducing off-current value
Low-concentration drain (LDD: Lightly Dope
d Drain) structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration.
We call it an area. As means for preventing deterioration of the on-current value due to hot carriers, in addition to the above, an LDD region is formed in a portion which is arranged so as to overlap with a gate electrode via a gate insulating film, that is, a so-called GOLD (Gate-dragging).
In Overlapped LDD) structures are known. With such a structure, it is known that a high electric field near the drain is relieved, hot carrier injection is prevented, and deterioration is effectively prevented.

[0006]

As described above, it is required to form a TFT using a crystalline semiconductor on a large-sized substrate and to reduce the production cost. At the same time, as described above, it is desired to form a GOLD (Gate-drain Overlapped LDD) structure to increase reliability. However, in order to form this GOLD structure, it is necessary to insert a patterning step or an etching step between the LDD region and the formation of the source and drain. The present invention is a technique for reducing the production cost while forming the GOLD structure. That is, in an active matrix type liquid crystal display manufactured using a TFT, an object is to realize an improvement in yield by making a TFT process appropriate.

[0007]

SUMMARY OF THE INVENTION According to the present invention, a method of forming a gate electrode having a two-layer structure of TaN and W in a top gate type TFT and examining a method of forming the GOLD structure is studied. The above object is achieved by optimizing. Note that the gate electrode is T
The reason why the two-layer structure of aN and W is used is that oxidation resistance and workability of the lower layer TaN and conductivity and workability of the upper layer W are considered. The present invention is applicable even if the gate electrode is formed of another conductive material having good conductivity and workability and capable of forming the shape of the gate electrode in FIG. The shape of the gate electrode in FIG. 1 is formed by a difference in etch rate between two conductive materials (the rate at which a film is etched under specific etching conditions is referred to as an etch rate in this specification).

[0008] The shape of the gate electrode having the two-layer structure of TaN and W formed according to the present invention, the gate insulating film, the semiconductor layer, the first impurity region in the semiconductor layer, and the semiconductor layer A second impurity region in
1 (hereinafter, an impurity region indicates a region in a semiconductor layer). In the semiconductor layer 101, the gate insulating film 102
In the upper layer, a first impurity region 104 is formed in a region where only TaN 103 is formed, and a second impurity region 105 is formed outside the first impurity region 104. In the semiconductor layer 101,
A channel region 107 is formed in a region where TaN103 and W106 are formed.

The present invention is characterized in that after forming the shape of the gate electrode by dry etching, an impurity is added to form the first impurity region and the second impurity region.

The inventor of the present invention has found that the step of alternately performing dry etching and doping a plurality of times on a substrate to form the structure of FIG. 1 can be performed only once by applying the present invention. I noticed. That is, it means that the movement of the substrate from one apparatus to another can be reduced, and it is considered that this greatly contributes to the reduction in the number of steps.

The present invention proposes three methods for adding the impurities. The three are shown below.

In the first impurity doping method, an impurity is added to a semiconductor layer under the first impurity doping condition in doping.

In a second impurity doping method, doping is performed by adding an impurity to a semiconductor layer under a second impurity doping condition, and then by adding a third impurity doping condition different from the second impurity doping condition. Is added to the semiconductor layer.

The first and second impurity doping conditions or the third impurity doping condition depend on the material or thickness of the gate insulating film, device operating conditions, and the like. To determine an appropriate range. In addition, the acceleration voltage and the dose at the time of adding the impurities need to be determined accordingly.

Using such means, the present invention provides a first step of forming a crystalline semiconductor layer, a second step of forming a gate insulating film on the crystalline semiconductor layer, A third step of forming a gate electrode over the insulating film, and a fourth step of adding an impurity to the crystalline semiconductor layer, in the method for manufacturing a semiconductor device, wherein in the fourth step, A first impurity region and a second impurity region are simultaneously formed in the crystalline semiconductor layer.

In another aspect of the invention, a first step of forming a crystalline semiconductor layer, and
A second step of forming a gate insulating film, a third step of forming a gate electrode on the gate insulating film, and a fourth step of adding an impurity to the crystalline semiconductor layer. In the method for manufacturing a semiconductor device, in the fourth step, a first impurity region and a second impurity region are continuously formed in the crystalline semiconductor layer.

In another aspect of the invention, a first step of forming a crystalline semiconductor layer, and
A second step of forming a gate insulating film, a third step of forming a gate electrode on the gate insulating film, and a fourth step of adding an impurity to the crystalline semiconductor layer. In the method for manufacturing a semiconductor device, the gate electrode includes a first conductive layer and a second conductive layer, and in the fourth step, a first impurity region and a second impurity region are formed in the crystalline semiconductor layer. Are simultaneously formed.

In another aspect of the present invention, a first step of forming a crystalline semiconductor layer, and
A second step of forming a gate insulating film, a third step of forming a gate electrode on the gate insulating film, and a fourth step of adding an impurity to the crystalline semiconductor layer. In the method for manufacturing a semiconductor device, the gate electrode includes a first conductive layer and a second conductive layer, and in the fourth step, a first impurity region and a second impurity region are formed in the crystalline semiconductor layer. Are continuously formed.

In another aspect of the present invention, a first step of forming a crystalline semiconductor layer, and
A second step of forming a gate insulating film, a third step of forming a gate electrode on the gate insulating film, and a fourth step of adding an impurity to the crystalline semiconductor layer. In the method for manufacturing a semiconductor device, the gate electrode includes a first conductive layer and a second conductive layer, and in the fourth step, a first impurity region and a second impurity region are simultaneously formed in the semiconductor layer. The first impurity region is formed in a region overlapping with the first conductive layer via the gate insulating film.

In another aspect of the present invention, a first step of forming a crystalline semiconductor layer, and
A second step of forming a gate insulating film, a third step of forming a gate electrode on the gate insulating film, and a fourth step of adding an impurity to the crystalline semiconductor layer. In the method for manufacturing a semiconductor device, the gate electrode includes a first conductive layer and a second conductive layer, and in the fourth step, a first impurity region and a second impurity region are continuous with the semiconductor layer. The first impurity region is formed in a region overlapping with the first conductive layer via the gate insulating film.

The first conductive layer and the second conductive layer include, for example, TaN and W, respectively.
The present invention is applicable even if the gate electrode is formed of another conductive material having good conductivity and workability and capable of forming the shape of the gate electrode in FIG.

[0022]

Embodiments of the present invention will be described below.

FIG. 1 shows the shape of the TFT until the gate electrode is formed in the TFT process of the present invention. Figure 1
The step of adding P as an impurity will be described with reference to a TFT having the above-mentioned shape as an example. Hereinafter, the first conductive layer and the second conductive layer are TaN and W, respectively, as an example.

The first impurity doping condition, the second impurity doping condition, and the third impurity doping condition for adding P are as follows: the TaN, the W, and the gate insulating film Determined by film thickness. This is because P accelerated in doping is decelerated when passing through a film formed above the semiconductor layer, and reaches the semiconductor layer with an acceleration voltage and a concentration distribution depending on the film thickness. If the accelerating voltage is high, it passes through the semiconductor layer, and if it is low, it does not reach the semiconductor layer.

In order to evaluate this concentration distribution characteristic, an SiO ₂ film was formed on a Si wafer by thermal CVD at 400 ° C. to a thickness of 300 nm, and several kinds of acceleration voltages were changed. Was examined. FIG. 2 shows that the acceleration voltage of P is 60 eV to 90 eV.
The concentration distribution of P added to SiO ₂ at a dose of 1.5 × 10 ¹⁵ atomic / cm ² was obtained from the above experiment. The horizontal axis indicates the depth direction from the surface, and the vertical axis indicates the concentration of added P. Thus, at each acceleration voltage, the concentration of P added tends to decrease as the depth from the surface increases.

Based on this result, the film thickness of the gate insulating film and the T
The first impurity addition condition, the second impurity addition condition, and the third impurity addition condition were determined for the aN film thickness, the first impurity concentration, and the second impurity concentration.

When the thickness of the gate insulating film below the region where the TaN is formed is 110 nm, the first impurity concentration is 1 × 10 ¹⁸ to 4 × 1 in order to reduce the off-current value.
0 ¹⁸ atomic / cm ³ and the second impurity concentration is 3 × 10 ¹⁹ to
It has been known from experiments so far that 1 × 10 ²¹ atomic / cm ³ can provide good device characteristics.

The following is an example of determining the conditions for adding each impurity in each of the above-described methods for adding impurities.

The first impurity doping method will be described below. The concentration of P added to the second impurity region is 1.7 × 10 ²⁰ atoms, which is appropriate for reducing the off-current value.
ic / cm ³ . At this time, a 90-nm gate insulating film is formed above the second impurity region. In Table 1, it is assumed that the gate insulating film is formed to have a thickness of 90 nm and the semiconductor layer is formed to have a thickness of 50 nm.
2 shows the result of calculating the averaged P concentration from FIG.

[0030]

[Table 1]

That is, according to Table 1, the accelerating voltage of 80 kV,
And 1.7 × at a dose of 1.5 × 10 ¹⁵ atomic / cm ^2.
10 ²⁰ atomic / cm ³ will be added. Therefore, 80 kV is set as a first impurity addition condition.

On the other hand, FIG. 3 shows that when the gate electrode and the gate insulating film have the structure shown in FIG. 1, P is 1.5 × 10 ¹⁵ atomic / cm 2.
⁴ shows the result of calculating the dependency of the concentration of P added to the first impurity region on the thickness of the TaN film when adding at a dose of ² . In addition, in the calculation of FIG.
Since it is enormous to prepare and analyze samples corresponding to the film thickness condition and each accelerating voltage condition, the calculation in FIG.
Was estimated for the stopping power of TaN against P when passing through TaN (the ability to block passage is referred to as stopping power), and the value was used. FIG. 9 shows TaN with several thicknesses on the upper layer of SiO ₂ .
5 shows the concentration distribution in the depth direction in SiO ₂ when P is added and P is added. The horizontal axis in FIG. 9 is SiO ₂
In the depth direction from the surface, when looking at the lateral movement of the concentration distribution due to the TaN film thickness at a depth of 100 nm or more, it can be estimated that the stopping power of SiO ₂ against P is 2 to 3 times. it can. In the present specification, the S
The stopping power of iO ₂ for P was doubled. Similarly,
The stopping power of Si against P when P passes through Si and S
The stopping power of iO ₂ for P was estimated as equal.

From the results shown in FIG.
Table 2 shows the thickness of the TaN film and the concentration of P added to the first impurity region when the thickness was 0 nm.

[0034]

[Table 2]

In FIG. 1, TaN of 30 nm is formed above the first impurity region. Referring to Table 1, 2.1 × 10 ¹⁸ atomic / cm ³ is added at 80 kV. That is, when the impurity is added at 80 kV, the first impurity region and the second impurity region are simultaneously formed in the semiconductor layer in the same step.

Subsequently, the second impurity doping method will be described below. Here, the concentration of P to be added to the first impurity region is, for example, 2.0 × 10 ¹⁸ atomic / cm ³ ,
The concentration of P to be added to the second impurity region is 1.2 ×
It is set to 10 ²⁰ atomic / cm ³ .

In the structure shown in FIG.
On the other hand, TaN of 30 nm is formed.
According to the previous experiments, the accelerating voltage of 90 kV, and
5 × 10¹³atomic / cm^TwoIf P is added at a dose of
2.0 × 10¹⁸atomic / cm^ThreeIs added at a density of
won. Therefore, the acceleration voltage of 90 kV and 5 × 10
¹³atomic / cm^TwoDose as the second impurity addition condition.
You.

At this time, above the second impurity region,
A 90-nm gate insulating film is formed. 90k
The impurity added at an acceleration voltage of V and a dose of 5 × 10 ¹³ atomic / cm ² has 1 × 1 in the second impurity region.
Approximately 0 ¹⁸ to 1 × 10 ¹⁹ atomic / cm ³ is added. This concentration is sufficiently smaller than 1.2 × 10 ²⁰ atomic / cm ³ which is the concentration of P to be added to the second impurity region.

Therefore, an accelerating voltage of 60 kV and 3 × 1
If P is added at a dose of 0 ¹⁵ atomic / cm ² , 1 × 10 ²⁰ atomic / cm ³ to 1 × 10 ²¹ atomic is added to the second impurity region.
/ cm ³ . The acceleration voltage of 60 kV and the dose of 3 × 10 ¹⁵ atomic / cm ² are the third impurity addition conditions.

[0040] In a third doping conditions, P is added to the first impurity region is ^{1.2 × 10 1 7 atomic / cm} 3 or so, the P should be added to the first impurity region It is much smaller than the concentration. Therefore, according to the second impurity doping method, it is easy to individually set the impurity concentrations of the first impurity region and the second impurity region in the crystalline semiconductor layer and to form them continuously.

As the acceleration voltage under the third impurity addition condition is set to be lower than the acceleration voltage of 90 kV, the P added to the first impurity region under the third impurity addition condition is increased.
Is small, and it becomes easier to individually set the impurity concentrations. However, since the change in the impurity concentration in the depth direction becomes sharp, the dependence of the impurity concentration on the thickness of the TaN film and the gate insulating film due to the in-plane distribution is likely to occur. Therefore, an appropriate acceleration voltage should be set.

Before and after the addition of P, the gate insulating film and the Ta
Since the N film thickness does not change, even if the order of the second impurity addition condition and the third impurity addition condition is changed, the N impurity is added to the first impurity region and the second impurity region. Impurity concentrations are the same. Therefore, the second impurity doping condition is set to an acceleration voltage of 60 kV and 3 × 10 ¹⁵ atomic / cm ^2.
And the third impurity doping condition is 90 kV
The same result can be obtained with an acceleration voltage of 5 × and a dose of 5 × 10 ¹³ atomic / cm ² .

The advantage of the first impurity doping method is that P can be added to the first impurity region and the second impurity region in a single addition. On the other hand, a disadvantage is that when the TaN film thickness and the gate insulating film thickness are uneven in the substrate surface, the amount of impurities added to the first impurity region and the second impurity region is also largely uneven. It is in. Therefore, it can be suitably used when the TaN film thickness and the gate insulating film thickness are uniform in the plane.

The advantage of the second impurity doping method is that the amount of P added to the first impurity region and the second impurity region can be controlled respectively. This is because, in this addition method, the impurity region to be added is different depending on the second impurity addition condition and the third impurity addition condition. Also,
For example, as can be seen from FIG. 3, as the depth of the layer to which the impurity is added becomes deeper from the surface, the change in the impurity concentration in the depth direction becomes gentler as the acceleration voltage increases.
By utilizing this characteristic, even if the in-plane TaN film thickness and the gate insulating film thickness are uneven in the substrate surface, it is easy to make the impurity amount in the in-plane impurity region uniform by changing the dose amount or the acceleration voltage. . On the other hand, a disadvantage is that a total of two additions are required to add an impurity to each impurity region. Therefore, when the TaN film thickness and the gate insulating film thickness are not uniform, or when the amount of impurity added to the first impurity region or the second impurity region is insufficient by the first impurity adding method, It can be suitably used.

The thickness of the gate insulating film formed above the second impurity region varies depending on the dry etching conditions for forming the gate electrode having the two-layer structure of TaN and W. Thus, when the thickness of the gate insulating film is reduced, the dose can be reduced, and the productivity is improved.

However, when the thickness of the gate insulating film is different as described above, the accelerating voltage should be appropriately set each time in the above-described impurity doping method. For example, when the thickness of the gate insulating film is small, it is preferable that the third impurity addition condition be a lower acceleration voltage. This is because, when the structure in which the thickness of the gate insulating film is small is doped with an impurity in the second impurity region at a high accelerating voltage, the second impurity region is amorphized and recrystallization becomes difficult.

With the two impurity doping methods described above, the first impurity concentration can be added to the first impurity region, and the second impurity concentration can be added to the second impurity region.

[0048]

[Embodiment 1] A detailed description will be given by the following embodiment. Here, an example until a TFT is formed on an insulating surface is shown in FIG. Here, an example is shown in which the thickness and film quality of TaN and the gate insulating film in the substrate surface are uniform, and P is added by the first impurity addition method.

In FIG. 4A, a glass substrate or a quartz substrate is used for a substrate 401. When using a glass substrate, to prevent impurity diffusion from the substrate on the substrate surface,
A base film 402 made of an insulating film is formed.

Next, 25 to 80 nm (preferably 30 to 80 nm)
Semiconductor layer 403 having a thickness of 60 nm) and having an amorphous structure.
Is formed by a known method such as a plasma CVD method or a sputtering method, and a crystallization step is performed to produce a crystalline semiconductor layer from an amorphous semiconductor layer. As a crystallization method, a laser annealing method, a thermal annealing method (solid phase growth method), or a rapid thermal annealing method (RTA method) can be applied. In the case of using the laser annealing method, if the thickness of the semiconductor layer is large, the heat capacity at the time of laser irradiation increases and damage to the substrate also increases.

Then, a resist pattern is formed on the crystalline semiconductor layer by using a photolithography technique,
The crystalline semiconductor layer is divided into islands by dry etching, and an island-shaped semiconductor layer 404 is formed as illustrated in FIG. For the purpose of controlling the threshold voltage (Vth) of the TFT, an impurity element imparting p-type is added to the island-shaped semiconductor layer 404 at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atomic / cm ^3. May be added to the entire surface of the semiconductor layer.

The gate insulating film 405 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. When a plasma CVD method or a sputtering method is used in this embodiment, good characteristics can be obtained by treating the surface of the semiconductor layer in an H ₂ atmosphere before film formation.

Then, as shown in FIG. 4C, a TaN film 406 for forming a gate electrode on the gate insulating film and a W
A film 407 is formed. In this embodiment, TaN is formed to a thickness of 30 nm, and W is formed to a thickness of 300 to 400 nm. The TaN film is formed by a sputtering method, and a Ta target is sputtered with Ar and N ₂ . When a W film is formed, it is formed by a sputtering method using W as a target.

Next, a resist mask is formed, and a first etching process for forming a gate electrode is performed.
This process will be described with reference to FIG. There is no limitation on the etching method, but preferably, ICP (Inductively Coupled Plas) is used.
ma: Inductively coupled plasma) Using an etching method, CF ₄ and Cl ₂ are mixed as an etching gas, and RF of 500 W is applied to a coil-type electrode at a pressure of 0.5 to ₂ Pa, preferably 1 Pa.
(13.56 MHz) Power is supplied to generate plasma.
100W RF (13.56MH) also on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, the W film and Ta
The N film is etched to the same extent.

Under the above etching conditions, the TaN film 502 and the WN film are formed by the effect of the bias voltage applied to the substrate side by making the shape of the resist mask appropriate.
The end of the film 503 has a tapered shape having an angle of 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%.

Next, a second etching process is performed. Similarly, using an ICP etching method, CF ₄ , Cl ₂ and O ₂ are mixed as an etching gas, and RF power (13.56 MHz) of 500 W is supplied to the coil type electrode at a pressure of 1 Pa to generate plasma. Do. 50W RF on substrate side (sample stage)
(13.56 MHz) power is applied, and a lower self-bias voltage is applied than in the first etching process. When the W film is anisotropically etched under such conditions and the TaN film as the first conductive layer is anisotropically etched at a lower etching rate, as shown in FIG. A second shape gate electrode is formed. Gate insulating film, T
The region 505 which is not covered with the aN film 504 is further etched by about 20 to 50 nm to form a thinned region.

In this embodiment, as the gate electrode material, T
Although aN and W have been described, other conductive materials may be used as long as the shape as shown in FIG. 5B is formed. For example, Ta, Mo,
WN, crystalline silicon, Ti, Nb, or 4A-6
From Group A, two suitable metals or alloys having different etch rates may be used.

Then, as shown in FIG. 5C, P is added by the first impurity addition method. The doping may be performed by an ion doping method or an ion implantation method. In the present embodiment, since the thickness of the gate insulating film is 90 nm, the conditions of the ion doping method shown in Table 1 indicate that the accelerating voltage is 8
0 kV and a dose of 1.5 × 10 ¹⁵ atomic / cm ² . Then, the first impurity region 506 and the second impurity region 507 are formed in a self-aligned manner. First impurity region 506
To about 2.0 × 10 ¹⁸ atomic / cm ³ .
P of about 1.7 × 10 ²⁰ atomic / cm ³ is added to the second impurity region 507.

The first impurity region thus formed
Reference numeral 506 denotes an LDD region, which increases reliability.
Depending on the thickness of the gate insulating film and the length of the first impurity region in the source-drain direction, there is an optimum value for reducing the electric field when the TFT is driven and lowering the electron temperature of the carriers in the semiconductor layer. The concentration should be considered according to the TFT.

FIG. 6A shows a cross section of the TFT in which the LDD region 601 is formed. Thereafter, as shown in FIG. 6B, the first interlayer insulating film 60 is formed on the gate electrode and the gate insulating film by sputtering or plasma CVD.
Form 2. The first interlayer insulating film 602 is a silicon oxide film,
The insulating film may be formed using a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. Here, a 500-nm-thick silicon oxynitride film was formed by plasma CVD.

Thereafter, a step of activating the impurity element imparting n-type added at an appropriate concentration is performed. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. However, when the substrate does not have heat resistance, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

Subsequent to the activation step, the atmosphere gas is changed, and the atmosphere gas is changed to 300 to 100% in an atmosphere containing 3 to 100% hydrogen.
A heat treatment is performed at 450 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When the activation and hydrogenation steps are completed,
As shown in FIG. 6C, a second interlayer insulating film 603 made of an organic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used.

As described above, by forming the second interlayer insulating film 603 from an organic insulating material, the surface can be satisfactorily planarized. Further, since the organic resin material 603 generally has a low dielectric constant, the parasitic capacitance can be reduced.
However, since it is hygroscopic and is not suitable as a protective film, it may be used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 602 as in this embodiment. .

Thereafter, a contact hole reaching the source region or the drain region formed in each island-like semiconductor layer is formed. The formation of the contact hole is performed by a dry etching method. In this case, the etching gas is C
First, the second interlayer insulating film 603 made of an organic resin material is etched using a mixed gas of F ₄ , O ₂ , and He, and then the first interlayer insulating film 602 is formed by using CF ₄ and O ₂ as the etching gas. Etch.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed, and a source wiring and a drain wiring 604 are formed by etching. In this embodiment, a Ti film is formed, a titanium nitride (TiN) film is formed thereon, and Al is further formed.
Further, a Ti film or a W film was formed to have a four-layer structure, and the entire thickness was 500 nm.

Thereafter, a resist mask pattern is formed, and the source wiring and the drain wiring 60 are formed by etching.
Form 4.

Thereafter, a transparent conductive film 605 is formed on the entire surface,
A pixel electrode is formed by a patterning process and an etching process. The pixel electrode is formed on the second interlayer insulating film 605 made of an organic resin material, and has a portion overlapping with the drain wiring of the pixel TFT to form an electrical connection.

The material of the transparent conductive film 605 is indium oxide (In ₂ O ₃ ) or indium oxide tin oxide alloy (In ₂ O _3).
—SnO ₂ ; ITO) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. ITO
When forming the substrate, if the substrate is kept at room temperature and crystallization is not performed by flowing hydrogen or water as a sputtering gas, the etching treatment can be performed with an acid-based solution such as hydrofluoric acid. In this case, in a later step, the substrate can be heat-treated at 160 to 300 ° C. for one hour or more to crystallize the ITO and increase the transmittance.

Through the above steps, a substrate having an n-channel TFT can be completed.

[Embodiment 2] In Embodiment 1, the n-channel type T
Although an example in which an FT is formed has been described, this embodiment shows an example in which a p-channel TFT is formed on the same substrate. Examples of the p-type impurity include boron (B) and As. In this embodiment, an example in which boron is added as a p-type impurity will be described.

FIG. 6 is a cross-sectional view of the substrate at the stage when the portion to be an n-channel TFT and the portion to be an n-channel TFT have been formed up to the formation of the gate electrode as shown in the first embodiment.

Here, P is added by the first impurity addition method shown in the first embodiment. Then, an n-channel TFT
Is added to the island-shaped semiconductor layer forming the p-type TFT and the island-shaped semiconductor layer forming the p-channel TFT. That is, as in the first embodiment, the first impurity region contains 2.0 × 10 ¹⁸ atomic atoms.
/ cm ³ of P is added, and 1.7 is added to the second impurity region.
P of about × 10 ²⁰ atomic / cm ³ is added.

Next, as shown in FIG.
Is formed by forming a resist mask and covering the entire surface. If the resist is formed with a thickness of 500 nm, the amount reaching the element when adding impurities is smaller than the amount added to the first impurity region. In this embodiment, it is formed with a thickness of 1000 nm.

Then, a high-concentration p-type impurity region serving as a source region and a drain region is formed in the island-shaped semiconductor layer forming the p-channel TFT. Here, an impurity element imparting p-type is added as a gate electrode mask, and a high-concentration p-type impurity region is formed in a self-aligned manner. The impurity region formed here is formed by an ion doping method using diborane (B ₂ H ₆ ). The boron concentration of the high concentration p-type impurity region that does not overlap with the gate electrode is 3 × 10 ²⁰ to 3 × 10 ^20.
It is adjusted to 10 ²¹ atomic / cm ³ . In addition, the impurity region overlapping with the first gate electrode is formed as a low-concentration p-type impurity region substantially because the impurity element is added through the gate insulating film and the first gate electrode. × 10 ¹⁹ atomic / cm ³ or more.

The high concentration p-type impurity region and the low concentration p
P is added to the p-type impurity region in the previous step, and 1 × 10 ²⁰ to 1 × 10 ²¹ is added to the high-concentration p-type impurity region.
At a concentration of atomic / cm ³ , 1 ×
Although it is contained at a concentration of 10 ¹⁶ to 1 × 10 ¹⁹ atomic / cm ³ , by adjusting the concentration of boron (B) added in this step to 1.5 to 3 times the P concentration, p No problem occurred because the channel type TFT functions as a source region and a drain region.

Thereafter, by performing processing as in the step after the impurity addition in the first embodiment, it is possible to form a CMOS circuit. In the second embodiment, as compared with the first embodiment, the number of steps of forming a resist on the n-channel TFT and doping the p-channel TFT is increased.

[Embodiment 3] In this embodiment, Embodiments 1 and 2
Another method for manufacturing a crystalline semiconductor layer for forming an active layer of a TFT of the active matrix substrate shown in FIG.
For the crystalline semiconductor layer, a crystallization method using a catalytic element disclosed in JP-A-7-130652 can be applied.

At this time, in the same manner as in the first embodiment, a base film and a semiconductor layer having an amorphous structure
It is formed with a thickness of 80 nm. In this embodiment, the amorphous silicon film is formed with a thickness of 55 nm. And 1 in weight conversion
A layer containing a catalyst element is formed by spin coating in which an aqueous solution containing 0 ppm of a catalyst element is applied by rotating a substrate with a spinner. In this embodiment, nickel (Ni) is used as the catalyst element.

In the crystallization step, first,
Heat treatment is performed at 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atomic% or less. If the hydrogen content of the amorphous silicon film has this value from the beginning after film formation, this heat treatment is not always necessary. And
Using a furnace annealing furnace, thermal annealing is performed at 550 to 600 ° C. for 1 to 8 hours in a nitrogen atmosphere. Through the above steps, a crystalline semiconductor layer made of a crystalline silicon film can be obtained.

However, when a catalyst element that promotes silicon crystallization is used in the crystallization step, a very small amount (about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atomic / cm ³ ) of catalyst is contained in the island-shaped semiconductor layer. Element remains. Of course, the TFT can be completed in such a state, but it is more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing a gettering action by phosphorus (P).

For functioning as source and drain regions
P concentration is 3 × 10¹⁹atomic / cm ^ThreeJust enough
However, for good gettering at P, 1.5 × 10
²⁰atomic / cm^ThreeThe above is preferred. Therefore, Embodiment 1 and Embodiment
In Step 2, P is added to the second impurity region at this concentration or more.
Add.

The gettering process using phosphorus (P) for this purpose can be performed simultaneously with the activation process described in the first embodiment. Phosphorus required for gettering (P)
May be substantially the same as the impurity concentration of the high-concentration n-type impurity region.
The catalyst element can be segregated from the channel formation region of the FT and the p-channel TFT to the impurity region containing phosphorus (P) at the concentration. As a result, a catalyst element of about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atomic / cm ³ segregated in the impurity region. The TFT thus manufactured has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved.

[Embodiment 4] TFT shown in Embodiments 1-3
When this is applied to a large-sized liquid crystal display, the uniformity of the thickness and film quality of TaN and the gate insulating film in the substrate surface is reduced, and the in-plane display may be uneven. At this time, the impurity may be added by the second impurity adding method, in which the impurity concentrations of the first impurity region and the second impurity region are more easily controlled than by the first impurity adding method.

In this case, P after the gate electrode is formed
In the addition step, an accelerating voltage of 90 kV and 5 × 10
P was added at a dose of ¹³ atomic / cm ² ,
an accelerating voltage of 60 kV smaller than an accelerating voltage of kV, and 3
P is added at a dose of × 10 ¹⁵ atomic / cm ² . Under these conditions, the first impurity region has a density of 2.0 × 10 ¹⁸ atomic / c.
P is added at a concentration of m ³ , and 1.2 P is added to the second impurity region.
P is added at a concentration of × 10 ²⁰ atomic / cm ³ .

P added at an appropriate dose at the acceleration voltage of 90 kV is accelerated at a lower accelerating voltage and compared with P added at an appropriate dose in the depth direction of the impurity concentration. Changes slow down. Therefore, a relatively good impurity concentration can be obtained even when the uniformity of the film thickness and film quality is low.

In the P addition step, the above-mentioned 6
The same result can be obtained by adding under the condition of the acceleration voltage of 90 kV after adding under the condition of the acceleration voltage of 0 kV.

In the first impurity doping method, 90
In the case where P is added at a high accelerating voltage such as kV, if the dose is set so that the impurity concentration of the first impurity region is appropriate, it is possible to getter a catalytic element such as Ni as shown in the third embodiment. Of P added to the source and drain regions is not sufficient.

[Embodiment 5] In this embodiment, an example in which an active matrix type liquid crystal display device is manufactured from the active matrix substrates manufactured in Embodiments 1 to 4 will be described.

FIG. 8 shows an active matrix type liquid crystal display device of this embodiment. In this configuration, a pair of glass substrates are arranged to face each other, an alignment film is formed in a gap 800, and a liquid crystal layer is sealed. An image signal wiring 802, a scanning signal wiring 803, and a TFT 804 disposed between the two wirings are arranged on the TFT substrate 801 formed in the first or second embodiment. And a drive circuit is formed around it. T
The FT is created in the first embodiment or the second embodiment, and functions as a switching element for writing a pixel signal to a pixel electrode.

The peripheral drive circuit is constituted by a MOS inverter formed by combining TFTs, and is built on the same substrate as a driver circuit. The image signal driving circuit 805 includes a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit. The scanning signal driving circuit 806 includes a shift register circuit, a level shifter circuit, and a buffer circuit. In forming these circuits, when a so-called CMOS in which an n-channel TFT and a p-channel TFT are combined is used, the area of the circuit can be reduced and the characteristics can be improved. For example, the sampling circuit is driven by alternately inverting the polarity and needs to reduce the off-state current value. Therefore, the sampling circuit is preferably formed using a p-channel TFT and an n-channel TFT.

On the other hand, a glass substrate 807 serving as a counter substrate has a counter electrode and a color filter 808 formed on the liquid crystal layer side. The color filter is divided into red, green, and blue segments corresponding to each pixel electrode. Have been. An image can be displayed by sandwiching the active matrix type liquid crystal display device having the above structure between the two polarizing plates 809 and allowing light to enter.

[0093]

As is clear from the above description, by using the present invention, the yield can be improved and the number of steps can be reduced in the manufacture of a semiconductor device having a GOLD structure.

According to the present invention, the moving distance of the substrate in the process is shortened, and the above-mentioned effect is particularly large for a large substrate.

[0095]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 2 is a diagram showing the concentration distribution of P when P is added to SiO ₂ .

FIG. 3 shows P when P is added to SiO ₂ ＼TaN.
Diagram showing the concentration distribution of

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 8 is a cross-sectional view showing that the TFT of the present invention is applied to an active matrix liquid crystal display.

FIG. 9 shows P when P is added to SiO ₂ ＼TaN.
FIG.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/28 301 H01L 29/78 616A 21/768 21/90 C 29/40 J 29/78 617L (72 ) Inventor Takuya Matsuo 22-22 Nagaike-cho, Abeno-ku, Osaka-shi F-term in Sharp Co., Ltd. (reference) BB16 BB17 BB18 BB32. DD02 DD03 EE01 EE04 EE09 EE14 EE23 EE44 FF12 FF28 FF30 FF35 GG02 GG13 GG25 GG32 GG34 GG43 GG45 HJ01 HJ04 HJ07 HJ12 HJ13 HJ23 HL01 HL 03 HL04 HL12 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN34 NN35 NN72 PP02 PP03 PP34 PP35 QQ04 QQ11 QQ24 QQ25 QQ28

Claims (8)

[Claims] A first step of forming a crystalline semiconductor layer;
A second step of forming a gate insulating film on the crystalline semiconductor layer, a third step of forming a gate electrode on the gate insulating film, and adding an impurity to the crystalline semiconductor layer. And a fourth step in which the first impurity region and the second impurity region are simultaneously formed in the crystalline semiconductor layer in the fourth step. A method for manufacturing a semiconductor device. 2. A first step of forming a crystalline semiconductor layer,
A second step of forming a gate insulating film on the crystalline semiconductor layer, a third step of forming a gate electrode on the gate insulating film, and adding an impurity to the crystalline semiconductor layer. And a fourth step in which the first impurity region and the second impurity region are continuously formed in the crystalline semiconductor layer in the fourth step. Of manufacturing a semiconductor device. 3. A first step of forming a crystalline semiconductor layer,
A second step of forming a gate insulating film on the crystalline semiconductor layer, a third step of forming a gate electrode on the gate insulating film, and adding an impurity to the crystalline semiconductor layer. And a fourth step of fabricating the semiconductor device, wherein the gate electrode comprises a first conductive layer and a second conductive layer, and in the fourth step, the first Wherein the impurity region and the second impurity region are simultaneously formed. 4. A first step of forming a crystalline semiconductor layer,
A second step of forming a gate insulating film on the crystalline semiconductor layer, a third step of forming a gate electrode on the gate insulating film, and adding an impurity to the crystalline semiconductor layer. And a fourth step of fabricating the semiconductor device, wherein the gate electrode comprises a first conductive layer and a second conductive layer, and in the fourth step, the first A method of manufacturing a semiconductor device, wherein an impurity region and a second impurity region are continuously formed. 5. A first step of forming a crystalline semiconductor layer,
A second step of forming a gate insulating film on the crystalline semiconductor layer, a third step of forming a gate electrode on the gate insulating film, and adding an impurity to the crystalline semiconductor layer. And a fourth step, wherein the gate electrode comprises a first conductive layer and a second conductive layer, and in the fourth step, the first impurity is added to the semiconductor layer. A region and a second impurity region are formed simultaneously, and the first impurity region is formed in a region overlapping with the first conductive layer via the gate insulating film. Method. 6. A first step of forming a crystalline semiconductor layer,
A second step of forming a gate insulating film on the crystalline semiconductor layer, a third step of forming a gate electrode on the gate insulating film, and adding an impurity to the crystalline semiconductor layer. And a fourth step, wherein the gate electrode comprises a first conductive layer and a second conductive layer, and in the fourth step, the first impurity is added to the semiconductor layer. A semiconductor device, wherein a region and a second impurity region are continuously formed, and the first impurity region is formed in a region overlapping with the first conductive layer via the gate insulating film. Method of manufacturing. 7. The method for manufacturing a semiconductor device according to claim 3, wherein the first conductive layer is TaN, and the second conductive layer is W. . 8. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device.