JP2002237485A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the quantity of side etching of a wiring layer and to suppress the narrowing of the wiring width of the wiring layer and an irregularity in the wiring width in a method of manufacturing a semiconductor device. SOLUTION: In the method of manufacturing the semiconductor device, a first etching gas is used to etch the wiring layer by a first etching process, the etching of the wiring layer is performed until the wiring layer on a wiring region, where a required etching quantity is minimum, comes just-etched and when the wiring layer is in the state of overetching, a second etching gas of which the etching speed is slower than that of the first etching gas is used to etch the wiring layer by a second etching process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a wiring layer, and more particularly to a method for manufacturing a semiconductor device having a wiring layer having a large thickness.

[0002]

2. Description of the Related Art In recent years, LSIs (Large Scale Integrated
With the increase in the frequency of semiconductor devices such as circuits (large-scale integrated circuits), the number of cases in which a dielectric element that has not been mounted conventionally is mounted in a semiconductor device is increasing. As such a dielectric element, for example, a spiral inductor in which a wiring layer of an Al + Al alloy is formed in a spiral shape,
It is the most common in terms of manufacturing and cost.

When such a dielectric element is formed in a semiconductor device, the characteristic (Q value) of the dielectric element depends on the film thickness, wiring width, wiring space, and dielectric constant of the semiconductor substrate constituting the dielectric element. Etc. In particular, the thickness of the wiring layer is
Since the Q value of the dielectric element is greatly affected, in order to form a high-performance (high Q value) dielectric element,
It is desirable to configure the wiring layer to be thick.

Further, when a dielectric element is formed on a semiconductor device using a silicon substrate, since the silicon substrate is a dielectric, a so-called mutual dielectric phenomenon occurs between the silicon substrate and the dielectric element formed thereon. Easy to occur. In this case, the characteristics of the dielectric element formed in the semiconductor device using the silicon substrate are affected by the energy loss caused by the mutual dielectric phenomenon, and as a result, a dielectric element having desired characteristics is formed. It becomes difficult. In order to suppress such a mutual dielectric phenomenon, it is necessary to reduce the spread of the magnetic field from the dielectric element. For this purpose, it is desirable to increase the thickness of the wiring layer forming the dielectric element.

In general, such a dielectric element is formed by dry-etching a wiring layer of, for example, an Al + Al alloy with an etching gas obtained by mixing a chlorine-based gas and a chlorine gas. is there.

FIGS. 11 to 13 are cross-sectional views illustrating the semiconductor device 100 in an etching step for forming such a dielectric element. Note that the semiconductor device 100 has wiring regions 100a and 100b having different etching amounts (etching amounts necessary for sufficiently etching the wiring layers 103a and 103b).
11A is a cross-sectional view of the wiring layer 103a, and FIG.
13B illustrate cross-sectional views of the wiring layer 103b.

When forming a dielectric element, first, as shown in FIG. 11, for example, silicon oxide layers 102a and 102b such as thermal oxide films are formed on silicon substrates 101a and 101b, which are semiconductor substrates. A on the top
Wiring layers 103a and 103b of l + Al alloy or the like are formed. Thereafter, photoresists 104a and 104b are applied to the upper surfaces of the wiring layers 103a and 103b, and the photoresists 104a and 104b are patterned into a shape of a dielectric element by a method such as photolithography.

When the patterning of the photoresists 104a and 104b is completed, the photoresist 10
Etching is performed using 4a and 104b as an etching mask. Here, the required etching amount of the wiring region 100a is smaller than the required etching amount of the wiring region 100b, and the wiring layer 103a in the wiring region 100a has a smaller etching amount than the wiring layer 103b in the wiring region 100b, and the just-etched state ( (A state in which the wiring layer is sufficiently etched and excessive etching is not performed). FIG. 12 shows the wiring layer 1
03a illustrates a state in which the just-etched state has been reached. As shown in FIG. 12B, in this state,
The amount of etching of the wiring layer 103b in the wiring region 100b is not sufficient, and an etching residue 103ba remains above the silicon oxide layer 102b in the etching region.

When a mixed gas of chlorine-based gas and chlorine gas is used as an etching gas, Cl radicals contained in the etching gas and photoresists 104a and 104b are used.
Reacts with each other to form a carbon-based polymer as a reactant. The carbon-based polymer thus formed is released into the chamber of the etching apparatus, and further adheres to the etching sidewalls of the wiring layers 103a and 103b. The carbon-based polymer adhered to the etched side walls of the wiring layers 103a and 103b is used to protect the side walls that protect the etched side walls from the etching gas.
a, 105ab, 105ba, 105bb and suppresses side etching of the wiring layers 103a, 103b.

After reaching the just-etched state (over-etched state), the wiring layers 103a, 103b
Is continued, and as shown in FIG. 13B, when the etching of the wiring layer 103b in the wiring region 100b is completed, the etching process ends.

[0011]

However, in this over-etched state, the object to be etched in the wiring region 100a does not exist other than the etching side wall of the wiring layer 103a, and the object to be etched in the semiconductor device 100 as a whole also decreases. It will be. Therefore, the distribution amount of chlorine radicals in the etching gas to the wiring layers 103a and 103b to be etched increases, and as a result, the side etching amount of the wiring layer 103a increases, and the wiring width of the wiring layer 103a decreases. In addition, there is a problem that the variation in the wiring width becomes large.

It is also known that, during the above-described etching process, the silicon oxide layer 102a is decomposed by sputter etching using an etching gas to generate oxygen radicals. In the over-etched state, the silicon oxide layer 102a in the wiring region 100a is exposed on the surface, so that the amount of generated oxygen radicals increases.
The erosion of 05aa, 105ab, 105ba, 105bb will be promoted. Sidewall protective films 105aa, 105
The erosion of ab, 105ba, 105bb is caused by the wiring layer 103.
There is a problem that the side etching amount of the wiring layers 103a and 103b is increased, and as a result, the wiring width of the wiring layers 103a and 103b is reduced, and the variation of the wiring width is increased.

[0013] The above-described problem is caused by the problem of the wiring layer 103.
This is particularly noticeable when the thicknesses of a and 103b are configured to be large. This is because the film thickness of the wiring layers 103a and 103b is large,
If the area of the etched side wall is large, the side wall protective film 10
This is because the thickness of 5aa, 105ab, 105ba, 105bb becomes thinner, and the protection thereof becomes weaker.

Further, as a means for solving the above-mentioned problem, a method of adding CH ₂ F ₂ or the like having a function as a protective film deposition gas to an etching gas, thereby depositing a sidewall protective film on an etching sidewall. There is. This method has an advantage that a stable sidewall protective film can be formed without being affected by the film thickness of the wiring layers 103a and 103, but particles (foreign particles adhering to the surface) are formed on the surface of the semiconductor device 100. ) To cause short-circuiting of the wiring and the like. further,
There is also a problem that the maintenance period of the equipment must be shortened.

The present invention has been made in view of such a point, and a method of manufacturing a semiconductor device capable of reducing a side etching amount of a wiring layer and suppressing a reduction in a wiring width of the wiring layer. The purpose is to provide.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the amount of side etching of a wiring layer and reducing variations in wiring width of the wiring layer.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the amount of side etching of a wiring layer without adding a protective film deposition gas to an etching gas. .

[0018]

According to the present invention, there is provided a method for manufacturing a semiconductor device having a wiring layer, the method comprising the steps of: first etching a wiring layer using a first etching gas; And a second etching step of etching the wiring layer using a second etching gas having an etching rate lower than that of the first etching gas. Is done.

Here, in the second etching step,
The second etching speed is lower than the first etching gas.
The etching rate of the over-etched state is reduced by etching the wiring layer using the etching gas described above, and the amount of side etching of the wiring layer is reduced.

In the present invention, preferably, the second
Is a gas obtained by mixing an additive gas having lower etching characteristics than the first etching gas with the first etching gas.

In the present invention, the additive gas is preferably a gas having a mass number of 40 or less. In the present invention, preferably, the first etching gas is a mixed gas of a chloride gas and a chloride gas.

In the present invention, preferably, the second
Is a gas obtained by mixing an additive gas having a mass number of 40 or less with the first etching gas. In the present invention, the additive gas is preferably mixed at a ratio of 10% or more and 50% or less with respect to the total flow rate of the second etching gas.

In the present invention, preferably, the additive gas is an argon gas. In the present invention,
Preferably, the thickness of the wiring layer is not less than 1.5 μm and 4.0.
μm or less.

In the present invention, preferably, the wiring layer forms a dielectric element. In the present invention, preferably, the wiring layer has two or more types of wiring regions having different etching amounts.

In the present invention, preferably, the first
In the etching step, the wiring layer is etched until the wiring layer in the minimum etching required wiring area, which is the wiring area where the required etching amount is the smallest, is in a just-etched state. After the wiring layer in the region has just been etched, the wiring layer is etched.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. The method for manufacturing a semiconductor device in this embodiment mode uses a first etching gas, a first etching step of etching a wiring layer, and a second etching gas having a lower etching rate than the first etching gas. There is a second etching step for etching the wiring layer.

First, the flow of the method for manufacturing a semiconductor device according to the present embodiment will be described. FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to this embodiment.

Step S1: This step is performed in the first step.
Is illustrated. As described above, the semiconductor device has, for example, two or more types of wiring regions having different etching amounts for the wiring layers. In the first etching step, among these wiring regions, for example, the wiring layer is etched until the wiring layer in the wiring region having the smallest required etching amount (minimum etching required wiring region) is in the just-etched state.

As an etching apparatus used in this step,
For example, an RF bias applying type magnetic field microwave etching apparatus, which is an etching apparatus that decomposes an etching gas into plasma by an interaction between a microwave and an electromagnetic field and performs etching by radicals generated by the plasma, can be used without any particular limitation. can do. Further, an etching gas used in the present step (first etching gas)
Also, for example, a mixed gas of a chloride gas and a chloride gas, as a specific example, a mixed gas of BCl ₃ and Cl ₂ ,
It can be used without particular limitation.

Step 2: In the first etching step of step S1, it is determined whether or not the wiring layer in the minimum etching required wiring area has reached the just-etched state. Here, for example, the etching rate corresponding to the etching conditions such as the type of the etching gas and the flow rate of the etching gas into the etching apparatus is determined in advance, and the etching for the film thickness of the wiring layer in the minimum required wiring area is performed. The time (just etching required time) is calculated, and the etching is performed depending on whether or not the etching time in the first etching step has reached the just etching required time.

Here, if it is determined that the wiring layer in the minimum required etching amount wiring region has reached the just-etched state, the process proceeds to step S3. On the other hand, when it is determined that the state has not reached the just etching state, the first etching process in step S1 is continued.

Step S3: This step is performed in the second
Is illustrated. In the second etching step, for example, the wiring layer is etched after the wiring layer in the above-described minimum etching required wiring area is brought into the just-etched state (over-etched state).

As the etching apparatus used in this step,
For example, an RF bias application type magnetic field microwave etching apparatus used in the first etching step can be used without any particular limitation.

In this step, for example, an etching gas (second etching gas) having an etching rate lower than that of the first etching gas used in the first etching step is used. If the second etching gas is a gas having an etching rate lower than that of the first etching gas, a gas obtained by mixing the first etching gas with an additive gas having lower etching characteristics than the first etching gas, such as, in particular, Can be used without restriction. When a mixed gas of the first etching gas and the additional gas is used as the second etching gas, the additional gas is the total flow rate of the second etching gas (the amount of the second etching gas introduced into the etching apparatus). 10%
As described above, it is desirable to mix at a ratio of 50% or less.
This is because if the mixing ratio of the additive gas is too low, the etching rate of the second etching gas increases, and the side etching of the wiring layer during overetching cannot be sufficiently suppressed. If it is too high, the etching rate of the second etching gas decreases,
This is because the processing time in the second etching step increases.

It is desirable that the total flow rate of the first etching gas and the total flow rate of the second etching gas are the same. This is because, for example, when a magnetic field microwave etching apparatus or the like is used as an etching apparatus and an etching process is performed with continuous plasma (without interrupting the discharge between the first etching step and the second etching step), If the flow rate of the etching gas differs between the first etching step and the second etching step, the gas pressure in the etching apparatus fluctuates between these steps, and the plasma discharge in the etching apparatus becomes unstable. It is because. When the plasma discharge becomes unstable as described above, there arises a problem that the etching rate varies and the variation of the wiring width of the wiring layer also increases.

The additive gas is a gas having a small mass number,
For example, a gas having a mass number of 40 or less is desirable. This is because the mass number of the additive gas is large,
The amount of sputter etching by the etching gas on the silicon oxide layer formed on the semiconductor substrate increases,
This is because the amount of oxygen radicals generated by the decomposition of the silicon oxide layer increases, and the erosion amount of the sidewall protective film increases. Specific examples of such additional gas include, for example, argon (Ar) gas, nitrogen (N ₂ ) gas, helium (He) gas, and the like.

Next, a specific example of a method for manufacturing a semiconductor device according to the present embodiment will be described. As described above, the method for manufacturing a semiconductor device according to this embodiment includes the first etching step and the second etching step. Hereinafter, these steps will be described step by step. In the following specific example, a dielectric element or the like such as a spiral inductor is formed on the upper surface of the semiconductor device 1.

FIGS. 2 to 5 are cross-sectional views illustrating the semiconductor device 1 etched in the method of manufacturing a semiconductor device according to the present embodiment. In addition, the semiconductor device 1 has wiring regions 1a and 1b having different etching amounts, and FIG.
5A are cross-sectional views of the wiring layer 1a, and FIG.
FIGS. 5A to 5B illustrate cross-sectional views of the wiring layer 1b. In the following, the wiring region 1a is defined as a minimum etching required wiring region.

When forming a dielectric element, for example, first,
As illustrated in FIGS. 2A and 2B, silicon oxide layers 3a and 3b such as thermal oxide films in a dry atmosphere at 850 ° C. are formed on silicon substrates 2a and 2b as semiconductor substrates.
Are formed, and wiring layers 4a and 4b of Al + Al alloy or the like are formed on the upper surface. The formation of the wiring layers 4a and 4b here is performed, for example, by CVD (Chemical Vapor).
The wiring layers 4a and 4b are, for example, 1.5 μm or more and 4.0 μm by the Deposition method, the sputtering method or the like.
It is performed by depositing to the following thickness.

When the wiring layers 4a and 4b are formed, for example, the wiring layers 4a and
The etching process of b is performed. (First Etching Step) First, for example, as a pre-process of the etching process, a photoresist 5 is formed on the upper surface of the wiring layer.
a and 5b are formed.

The photoresists 5a and 5b are formed, for example, by applying photoresists 5a and 5b such as positive photoresists on the upper surfaces of the wiring layers 4a and 4b by a known method, and further applying the photoresists 5a and 5b. For example, by photolithography using a g-line (wavelength: 436 nm) stepper or the like to pattern it into a shape of a dielectric element or the like (FIGS. 2A and 2B).

After the photoresists 5a and 5b are formed, the wiring layers 4a and 4b are formed by the first etching process.
The etching process of b is performed. In a specific example of the first etching step, for example, the etching process of the semiconductor device 1 is performed under the etching conditions 11 illustrated in FIG. Specifically, as illustrated in FIG. 6A, for example, BCl is used as the first etching gas.
Using a mixed gas of ₃ and Cl ₂ , the flow rates into the etching apparatus were 20 sccm (BCl ₃ ) and 60
sccm (Cl ₂ ), and the gas pressure is, eg, 1.07 Pa (8 mTorr). As an etching apparatus, for example, an RF bias application type magnetic field microwave etching apparatus or the like is used. Set each to ℃.

The etching process in the first etching step is performed, for example, in a state where the above-mentioned etching conditions are kept constant. The etching process is performed, for example, in the wiring region 1a which is the minimum required wiring region.
Is performed until the wiring layer 4a is just etched.

FIG. 3 shows the result of the first etching step.
FIG. 9 is a cross-sectional view of the semiconductor device 1 illustrating a state where the wiring layer 4a is in a just-etched state. FIG. 3 (a),
In this state, as illustrated in FIG.
Is sufficiently etched, but the etching of the wiring layer 4b in the wiring region 1b is not sufficient, and the etching residue 4ba remains on the upper surface of the silicon oxide layer 3b. .

As described above, during this etching process, for example, the Cl radicals contained in the first etching gas react with the photoresists 5a and 5b to form a carbon-based polymer as a reactant. Becomes The carbon-based polymer thus formed is released, for example, into the chamber of the etching apparatus, and further adheres to the etching side walls and the like of the wiring layers 4a, 4b as illustrated in FIGS. I do. The carbon-based polymer adhered to the etching side walls of the wiring layers 4a and 4b functions as side wall protection films 6aa, 6ab, 6ba and 6bb for protecting the side walls for protecting the etching side walls from the etching gas.

When the wiring layer 4a in the wiring region 1a, which is the minimum required amount of wiring, is brought into the just-etched state, the process proceeds to the second etching step. (Second Etching Step) In a specific example of the second etching step, the semiconductor device 1 is etched under the etching conditions 12 illustrated in FIG. 6B, for example. Specifically, as exemplified in FIG. 6B, for example, as a second etching gas, a mixed gas of BCl ₃ and Cl ₂ is added to argon (Ar) as an additional gas.
Using a mixed gas, the flow rate into the etching apparatus was set to 10 sccm (BCl ₃ ) and 60 s, respectively.
ccm (Cl ₂ ), 10 sccm (Ar), and
The gas pressure is, for example, 1.07 Pa (8 mTorr)
And Further, as the etching apparatus, for example, an RF bias application type magnetic field microwave etching apparatus or the like is used, and for example, the microwave is 300 mA, and the RF Po is used.
The wafer temperature is set to 55 W, and the wafer temperature, which is the temperature of the semiconductor device during the etching process, is set to 35 ° C.

The etching process in the second etching step is performed, for example, in a state where the above-described etching conditions are kept constant. The etching process is performed, for example, by completely etching the remaining portion 4ba of the wiring region 1b. 4B, and the process is terminated in a state where the remaining etching portion 4ba is completely etched as shown in FIG. 4B.

Here, in the second etching step, as described above, the second etching gas having a lower etching rate than the first etching gas, specifically, for example, the first etching gas is used.
A part of BCl ₃ constituting the etching gas (mixed gas of BCl ₃ and Cl ₂ ) is added to argon (A
r) by the second etching gas replaced by gas,
Since the etching treatment is performed, chlorine radicals in this step can be diluted. Thereby, even in the over-etching state where the etching target of the semiconductor device 1 as a whole is decreasing, the distribution amount of chlorine radicals in the etching gas to the wiring layers 4a and 4b to be etched is increased. As a result, the amount of side etching of the wiring layer 4a can be reduced. Such an effect is particularly prominent when the thickness of the wiring layer 4a is increased, for example, when the thickness of the wiring layer 4a is 1.5 μm or more and 4.0 μm or less.

Further, by using, for example, an argon (Ar) gas having a mass number of 40 or less as an additional gas to be added to the second etching gas, the amount of etching of the silicon oxide layer 3a by the etching gas can be reduced. It is possible to reduce the amount of oxygen radicals generated by the decomposition of the silicon oxide layer. Thereby, the side wall protective films 6aa, 6aa
The amount of erosion of ab, 6ba, 6bb can be reduced, and side etching of the wiring layer 4a can be suppressed.

FIG. 7 shows the mixing ratio of Ar gas to the mixed gas of BCl ₃ and Cl _2, and using the mixed gas,
5 is a graph illustrating the relationship between the etching rate when an Al + Al alloy wiring layer is etched.

As illustrated in FIG. 7, the etching rate of the Al + Al alloy is 2.64 μm / etching rate under the etching condition 11 of the first etching step illustrated in FIG.
In contrast, under the etching condition 12 of the second etching step illustrated in FIG.
m / min. This indicates that the etching rate in the second etching step is lower than that in the first etching step by 0.56 μm.

The etching rate illustrated in FIG.
It was calculated by the following method. FIG. 8 is a flowchart illustrating the procedure for measuring the etching rate.
10 is a cross-sectional view illustrating the semiconductor device 20 in the measurement process.

The procedure for calculating the etching rate will be described below with reference to FIGS. Step S10: First, as illustrated in FIG. 9A, a silicon oxide layer 23 is formed on a silicon substrate 22, and a wiring layer 24 is further formed on an upper surface thereof. Further, a photoresist 25 in which the shape of the dielectric element is patterned is formed on the upper surface of the wiring layer 24.

Next, as illustrated in FIG. 9B, etching is performed until the wiring layer 24 is in a just-etched state. Further, by this step, the side wall protective films 26a and 26b are formed on the etched side walls of the wiring layer 24.

Step S11: As illustrated in FIG. 10A, the photoresist 25 is removed by a known method.

Step S12: Wiring layer 2 as initial film thickness
The thickness t1 of No. 4 is measured (FIG. 10A). Step S13: FIG.
(B), the entire surface of the semiconductor device 20 is etched.

Step S14: The film thickness t2 of the wiring layer 24 after the entire surface is etched in step S13 is measured (FIG. 10B).

Step S15: The difference between the initial film thickness t1 measured in step S12 and the film thickness t2 after the entire surface etching measured in step S14 is determined, and thereby the etching rate for the etching conditions in step S13 is determined.

The etching rate obtained in this way is different from the actual etching rate in the first etching step and the second etching step described above.
This measurement condition is that the etching area is small,
It can be said that the etching target of the semiconductor device as a whole is in a state close to the over-etching state where the number of etching targets is decreasing,
The measurement results are expected to be close to actual conditions.

When the etching of the remaining etching portion 4ba is completed, next, as illustrated in FIGS. 5A and 5B, the side wall protective films 6aa, 6ab, 6ba, 6bb and the photoresists 5a, 5b are known. And the formation of the dielectric element is completed.

As described above, in the present embodiment, for example, in the first etching step, the first etching gas is used to form the wiring region 1a which is the minimum required wiring region.
The wiring layers 4a and 4b are etched until the first wiring layer 4a is in the just-etched state. During over-etching, the second etching step uses a second etching gas having a lower etching rate than the first etching gas. The wiring layers 4a and 4b are etched by reducing the side etching amount of the wiring layer 4a,
It is possible to suppress a reduction in the wiring width of the wiring layer 4a.

Similarly, in the first etching step, the first etching gas is used, and the wiring layers 4a and 4b in the wiring region 1a, which is the minimum required amount of wiring, are brought into the just-etched state. In the over-etching, in the second etching step, the wiring layer 4a is etched using a second etching gas having a lower etching rate than the first etching gas.
Since the etching of the wiring layer 4b is performed, the amount of side etching of the wiring layer 4a can be reduced, and the variation in the wiring width of the wiring layer 4a can be suppressed.

Similarly, in the first etching step, the first etching gas is used to form the wiring layers 4a, 4b until the wiring layer 4a in the wiring area 1a, which is the minimum required wiring area, is brought into the just-etched state. In the over-etching, the wiring layer 4 is formed by using a second etching gas having a lower etching rate than the first etching gas in the second etching step.
a and 4b, the wiring layer 4 can be formed without adding a protective film deposition gas to the etching gas.
a can be reduced.

The present invention is not limited to the above embodiment. For example, in the present embodiment, the present invention is applied to a semiconductor device having a wiring region having a different required etching amount, but several kinds of semiconductor devices having wiring layers having different required etching amounts are simultaneously etched. At this time, the present invention may be applied.

[0065]

As described above, according to the present invention, in the first etching step, the first etching gas is used to etch the wiring layer, and in the second etching step, the wiring layer is etched more than the first etching gas. Since the wiring layer is etched using the second etching gas having a low etching rate, the amount of side etching of the wiring layer can be reduced, and the wiring width of the wiring layer can be suppressed from being reduced.

Further, in the first etching step, the wiring layer is etched using the first etching gas, and in the second etching step, the second etching gas having a lower etching rate than the first etching gas is used. Is used to etch the wiring layer, so that the amount of side etching of the wiring layer can be reduced and the variation in the wiring width of the wiring layer can be suppressed.

Further, by the first etching step,
The wiring layer is etched using the first etching gas, and the wiring layer is etched using the second etching gas having a lower etching rate than the first etching gas in the second etching step. In addition, the amount of side etching of the wiring layer can be reduced without adding a protective film deposition gas to the etching gas.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device.

FIG. 2 is a cross-sectional view illustrating a semiconductor device that has been etched in a method for manufacturing a semiconductor device;

FIG. 3 is a cross-sectional view illustrating a semiconductor device that has been etched in a method for manufacturing a semiconductor device;

FIG. 4 is a cross-sectional view illustrating a semiconductor device that has been etched in a method for manufacturing a semiconductor device;

FIG. 5 is a cross-sectional view illustrating a semiconductor device that has been etched in a method for manufacturing a semiconductor device.

FIG. 6 is a diagram illustrating etching conditions.

FIG. 7 is a graph illustrating the relationship between the mixing ratio of Ar gas to the mixed gas of BCl ₃ and Cl ₂ and the etching rate when the Al + Al alloy wiring layer is etched using the mixed gas. .

FIG. 8 is a flowchart illustrating a procedure for measuring an etching rate.

FIG. 9 is a cross-sectional view illustrating a semiconductor device in a process of measuring an etching rate.

FIG. 10 is a cross-sectional view illustrating a semiconductor device in a process of measuring an etching rate.

FIG. 11 is a cross-sectional view illustrating the semiconductor device in an etching step for forming a dielectric element.

FIG. 12 is a cross-sectional view illustrating a semiconductor device in an etching step for forming a dielectric element.

FIG. 13 is a cross-sectional view illustrating a semiconductor device in an etching step for forming a dielectric element.

[Explanation of symbols]

1, 20, 100 ... Semiconductor devices, 1a, 1b, 100
a, 100b ... wiring area, 2a, 2b, 22, 101
a, 101b: silicon substrate, 3a, 3b, 23, 10
2a, 102b... Silicon oxide layers, 4a, 4b, 24,
103a, 103b ... wiring layer, 6aa, 6ab, 6b
a, 6bb, 26a, 26b, 105aa, 105a
b, 105ba, 105bb ... sidewall protective film, 4ba, 1
03ba: etching residue, 11, 12: etching conditions

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F004 AA03 AA09 BB13 BB14 CA02 CA03 DA04 DA11 DA22 DA23 DA25 DA30 DB09 EB02 5F033 HH08 HH09 PP06 PP15 QQ08 QQ11 QQ15 QQ21 QQ33 QQ35 QQ73 QQ76 RR04 SS25 SS00 WW04 WW00 WW00 XX21 5F038 AZ04 EZ15 EZ20

Claims (11)

[Claims] 1. A method for manufacturing a semiconductor device having a wiring layer, wherein: a first etching step of etching the wiring layer using a first etching gas; and an etching rate lower than that of the first etching gas. A second etching step of etching the wiring layer using a second etching gas. 2. The gas according to claim 1, wherein the second etching gas is a gas obtained by mixing the first etching gas with an additive gas having an etching characteristic lower than that of the first etching gas. Of manufacturing a semiconductor device. 3. The method according to claim 2, wherein the additional gas is a gas having a mass number of 40 or less. 4. The method according to claim 1, wherein the first etching gas is a mixed gas of a chloride gas and a chloride gas. 5. The method according to claim 4, wherein the second etching gas is a gas obtained by mixing an additional gas having a mass number of 40 or less with the first etching gas. . 6. The method according to claim 1, wherein the additive gas is 10% of a total flow rate of the second etching gas.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the components are mixed at a ratio of not less than 50% and not more than 50%. 7. The method according to claim 5, wherein the additive gas is an argon gas. 8. The method according to claim 1, wherein the thickness of the wiring layer is 1.5 μm or more and 4.0 μm or less. 9. The method according to claim 1, wherein the wiring layer forms a dielectric element. 10. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring layer has two or more types of wiring regions having different etching amounts. 11. The first etching step includes: etching the wiring layer until the wiring layer in the minimum etching required wiring area, which is the wiring area having the smallest required etching amount, is in a just-etched state; 11. The method of manufacturing a semiconductor device according to claim 10, wherein in the second etching step, the wiring layer is etched after the wiring layer in the minimum etching required amount wiring region is brought into a just-etched state. .