JP2002232069A - Method of manufacturing optical semiconductor device - Google Patents
Method of manufacturing optical semiconductor deviceInfo
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- JP2002232069A JP2002232069A JP2001026728A JP2001026728A JP2002232069A JP 2002232069 A JP2002232069 A JP 2002232069A JP 2001026728 A JP2001026728 A JP 2001026728A JP 2001026728 A JP2001026728 A JP 2001026728A JP 2002232069 A JP2002232069 A JP 2002232069A
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- region
- mesa
- growth
- linear
- stripe structure
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、光情報通信等で用
いられる光半導体装置の製造方法に関する。The present invention relates to a method for manufacturing an optical semiconductor device used for optical information communication and the like.
【０００２】[0002]
【従来の技術】近年、光通信はその大容量、超高速化に
より、多くの情報通信網が用いられている。このような
光通信網では、発光素子や受光素子などに光半導体部品
が広く利用されており、その研究開発が盛んに行われて
いる。光半導体部品の研究開発は、半導体レーザ（Ｌ
Ｄ）やフォトダイオード（ＰＤ）のような個別部品は勿
論のこと、ＬＤやＰＤ、半導体増幅器（ＳＯＡ）、電界
吸収型光変調器（ＥＡ）など半導体で作製可能な光デバ
イスを半導体基板上にモノリシック集積することも精力
的に行われている。モノリシック集積では各々の機能に
最適化された活性層構造及び導波路構造を用いること、
これらを高い結合効率を保ったまま接続することが重要
な課題の一つである。2. Description of the Related Art In recent years, many information communication networks have been used for optical communication due to its large capacity and ultra-high speed. In such an optical communication network, optical semiconductor components are widely used for light-emitting elements, light-receiving elements, and the like, and research and development thereof are being actively conducted. The research and development of optical semiconductor components is based on semiconductor lasers (L
Optical devices that can be made of semiconductors, such as LDs, PDs, semiconductor amplifiers (SOAs), and electro-absorption optical modulators (EAs), as well as individual components such as D) and photodiodes (PDs), are mounted on a semiconductor substrate. Monolithic integration is also being actively pursued. In monolithic integration, use active layer structure and waveguide structure optimized for each function,
One of the important issues is to connect them while maintaining high coupling efficiency.
【０００３】一方、ＬＤなどの電流注入素子では、低消
費電力を実現するために作動電流の低減が要求され、こ
のためには注入効率を改善することが必須である。有機
金属気相エピタキシャル（ＭＯＶＰＥ）法による選択成
長で作製された埋め込み構造は、強い電流狭窄効果を得
ることができるため、ＬＤなどの単体素子で広く用いら
れている。On the other hand, current injection elements such as LDs require a reduction in operating current in order to achieve low power consumption, and for this purpose, it is essential to improve injection efficiency. A buried structure manufactured by selective growth by a metal organic vapor phase epitaxy (MOVPE) method can obtain a strong current confinement effect, and is therefore widely used in a single element such as an LD.
【０００４】しかしながら、モノリシック集積素子のよ
うに異種の導波路層をもち、導波路構造も埋め込み構造
やハイメサ構造、リッジ構造など様々な構造が混在する
場合には、単体素子での作製方法をそのまま用いること
が困難になる。[0004] However, in the case of having a different kind of waveguide layer such as a monolithic integrated device, and various structures such as a buried structure, a high-mesa structure, and a ridge structure are mixed in the waveguide structure, the manufacturing method of a single device is directly used. It becomes difficult to use.
【０００５】従来の半導体装置における異種の導波路構
造の接続方法（製造方法）を図７に基づいて説明する。
ここでは、一例として、埋め込み構造をもつＬＤとハイ
メサ構造をもつアレイ導波路格子（ＡＷＧ）を突き合わ
せる場合について説明する。[0005] A connection method (manufacturing method) of a different type of waveguide structure in a conventional semiconductor device will be described with reference to FIG.
Here, as an example, a case where an LD having a buried structure and an arrayed waveguide grating (AWG) having a high mesa structure are matched will be described.
【０００６】図７(a) に示すように、まずInP 基板１上
にＬＤ活性層２とp-InP クラッド層３を形成し、図中右
半分をウェットエッチングで除去した後、ＡＷＧ導波路
層４とi-InP クラッド層５を順次ＭＯＶＰＥ法により形
成する。ＭＯＶＰＥ法では誘電体膜（SiO2）を用いた選
択成長が可能なため、このような構造を作製することが
可能となる。この後、ＬＤは埋め込み構造を作製するた
めに、［０１１］方向に平行なメサストライプ構造を形
成してＭＯＶＰＥ成長を行う。このとき、ＡＷＧ領域は
埋め込み構造を必要としないので、メサストライプ上部
と同様に誘電体膜を形成しておくことが考えられる。図
７(b) には選択成長後の状態を示してある。As shown in FIG. 7A, first, an LD active layer 2 and a p-InP clad layer 3 are formed on an InP substrate 1, and the right half in the figure is removed by wet etching. 4 and the i-InP cladding layer 5 are sequentially formed by the MOVPE method. In the MOVPE method, since selective growth using a dielectric film (SiO 2 ) is possible, such a structure can be manufactured. Thereafter, the LD forms a mesa stripe structure parallel to the [011] direction and performs MOVPE growth to produce an embedded structure. At this time, since the AWG region does not require a buried structure, it is conceivable to form a dielectric film in the same manner as the upper portion of the mesa stripe. FIG. 7B shows the state after the selective growth.
【０００７】しかし、この場合、ＡＷＧ領域の誘電体膜
の面積が埋め込み成長時の材料分子のマイグレーション
距離より十分に大きくなり、ＡＷＧ領域の誘電体膜の上
に多結晶状の異常成長を引き起こすため、現実的ではな
い。そこで、図８(a) に示すように、図７(a) と同様な
メサストライプ構造を形成し、ＡＷＧ領域の誘電体膜を
除去してＭＯＶＰＥ成長を行うことで埋め込み構造を作
製することが考えられる。図８(b) には選択成長後の状
態を示してある。However, in this case, the area of the dielectric film in the AWG region becomes sufficiently larger than the migration distance of the material molecules at the time of burying growth, and polycrystalline abnormal growth occurs on the dielectric film in the AWG region. , Not realistic. Therefore, as shown in FIG. 8A, it is possible to form a buried structure by forming a mesa stripe structure similar to that of FIG. 7A, removing the dielectric film in the AWG region and performing MOVPE growth. Conceivable. FIG. 8B shows the state after the selective growth.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、図８に
示した場合にもＡＷＧ領域の端面で異常成長などが生じ
るため問題となる。以下その問題について詳細に説明す
る。However, even in the case shown in FIG. 8, a problem arises because abnormal growth or the like occurs on the end face of the AWG region. Hereinafter, the problem will be described in detail.
【０００９】一般にGaInAsP 系のＬＤは（１００）面を
表面としたInP 基板に作製される。また、メサストライ
プは［０１１］方向（逆メサ方向）に平行とし、このメ
サストライプを選択ＭＯＶＰＥ成長により埋め込む。こ
れは、ＭＯＶＰＥ成長工程が異方性により（１１１Ｂ）
面での成長レートが（１００）面の成長レートより低い
ため、図に示したように良好な選択成長を再現性よく得
られることができるためである。Generally, a GaInAsP-based LD is manufactured on an InP substrate having a (100) plane as a surface. The mesa stripe is parallel to the [011] direction (the reverse mesa direction), and the mesa stripe is embedded by selective MOVPE growth. This is because the MOVPE growth process is anisotropic (111B).
Because the growth rate on the plane is lower than the growth rate on the (100) plane, good selective growth can be obtained with good reproducibility as shown in the figure.
【００１０】しかしながら、［０１−１］方向（順メサ
方向）に平行とした場合には、逆メサ方向への成長レー
トが（１００）面の成長レートと同等であるため、図８
(b)中のIX矢視方向視を表す図９に示すように、マスク
上に被る方向へも成長が進行する。これは、メサストラ
イプとＡＷＧ領域とのマスク端面部分に相当する。これ
により、端面からの成長がメサストライプ脇でも発生
し、ここを起点として成長されるため端面付近のメサス
トライプ上にも成長される。この成長層は、メサ幅が３
μｍ以下と狭いことから容易に側面のからの成長層と接
合され、端面付近では複数の結晶面方位が露出する。こ
のような、面方位の定まらないマスク上の成長領域では
異常成長を誘発し、誘電体膜上にもInP が成長される。
この結果、この部分には電極構造を作製することが不可
能となるので、ＬＤの場合には大きな吸収損失領域とな
り、特性を大幅に劣化させる。[0010] However, when the growth rate is parallel to the [01-1] direction (forward mesa direction), the growth rate in the reverse mesa direction is equal to the growth rate of the (100) plane.
As shown in FIG. 9 showing the view in the direction of the arrow IX in FIG. This corresponds to the mask end surface portion between the mesa stripe and the AWG region. As a result, the growth from the end face also occurs on the side of the mesa stripe, and the growth is performed from this point as a starting point, so that the growth also occurs on the mesa stripe near the end face. This growth layer has a mesa width of 3
Since it is as narrow as μm or less, it is easily bonded to the growth layer from the side, and a plurality of crystal plane orientations are exposed near the end face. In such a growth region on the mask where the plane orientation is not determined, abnormal growth is induced, and InP is also grown on the dielectric film.
As a result, it becomes impossible to form an electrode structure in this portion, so that in the case of LD, a large absorption loss region is obtained, and the characteristics are significantly deteriorated.
【００１１】本発明は上記状況に鑑みてなされたもの
で、特性を損なうことなく高性能なモノリシック集積素
子を実現できる光半導体装置の製造方法を提供すること
を目的とする。The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing an optical semiconductor device that can realize a high-performance monolithic integrated element without deteriorating characteristics.
【００１２】[0012]
【課題を解決するための手段】上記目的を達成するため
の本発明の光半導体装置の製造方法は、半導体基板上に
形成された平面構造を持つ平面領域と、該平面領域に接
続された誘電体膜を持つメサストライプ構造のストライ
プ領域とを有する光半導体装置の製造方法であって、前
記ストライプ領域を、直線メサストライプ構造を持つ第
１直線領域と、該第１直線領域に接してメサ幅が徐々に
変化するメサストライプ構造を持つ遷移領域と、前記遷
移領域に接すると共に前記平面領域に接して直線メサス
トライプ構造を持つ第２直線領域とで構成し、前記スト
ライプ領域の横と前記平面領域の上に有機金属気相エピ
タキシャル法により結晶を選択成長させる工程を有する
ことを特徴とする。In order to achieve the above object, a method of manufacturing an optical semiconductor device according to the present invention comprises a planar region having a planar structure formed on a semiconductor substrate, and a dielectric connected to the planar region. A method of manufacturing an optical semiconductor device having a mesa stripe structure having a body film, wherein the stripe region is formed of a first straight region having a straight mesa stripe structure and a mesa width in contact with the first straight region. And a second linear region having a linear mesa stripe structure in contact with the transition region and the planar region, wherein the transition region has a mesa stripe structure that gradually changes. Characterized by a step of selectively growing crystals by metalorganic vapor phase epitaxy.
【００１３】そして、前記第１直線領域の直線メサスト
ライプ構造のメサ幅が３μｍ以下とされ、前記第２直線
領域の直線メサストライプ構造のメサ幅がメサ深さの
１．５倍から５倍とされ、長さがメサ深さの１倍から２
倍とされ、前記遷移領域のメサ幅が、前記第１直線領域
に接するメサ幅から前記第２直線領域に接するメサ幅ま
で徐々に広がり変化し、広がり角度が１０度から４５度
に設定されていることを特徴とする。The mesa width of the straight mesa stripe structure in the first straight region is 3 μm or less, and the mesa width of the straight mesa stripe structure in the second straight region is 1.5 to 5 times the mesa depth. And the length is 1 to 2 times the mesa depth
And the mesa width of the transition region gradually expands from the mesa width contacting the first linear region to the mesa width contacting the second linear region, and the spread angle is set from 10 degrees to 45 degrees. It is characterized by being.
【００１４】[0014]
【発明の実施の形態】図１乃至図３には本発明の一実施
形態例に係る光半導体装置の製造方法の工程説明を示し
てあり、図１は選択成長前の状態、図２は選択成長後の
状態、図３は図２中のIII 矢視である上面からの状態で
ある。1 to 3 show process steps of a method for manufacturing an optical semiconductor device according to an embodiment of the present invention. FIG. 1 shows a state before selective growth, and FIG. FIG. 3 shows the state after the growth, as viewed from the top as viewed in the direction of arrow III in FIG.
【００１５】ここでは、一例として（１００）面を表面
としたInP 基板で説明する。図中、１１はInP 基板、１
２はＬＤ活性層、１３はp-InP クラッド層、１４はＡＷ
Ｇ導波路層、１５はi-InP クラッド層である。ＬＤでは
光導波モードのシングルモード条件を満たす必要がある
ため、導波路幅を３μｍ以下としている。一般にメサス
トライプは１．５μｍ程度で、良好な埋め込み構造を得
るために逆メサ方向に対して平行に形成される。Here, an InP substrate having a (100) plane as a surface will be described as an example. In the figure, 11 is an InP substrate, 1
2 is an LD active layer, 13 is a p-InP cladding layer, 14 is AW
The G waveguide layer 15 is an i-InP cladding layer. Since the LD needs to satisfy the single mode condition of the optical waveguide mode, the waveguide width is set to 3 μm or less. Generally, the mesa stripe is about 1.5 μm, and is formed parallel to the reverse mesa direction to obtain a good buried structure.
【００１６】一方、選択成長工程では半絶縁性半導体で
あるFeをドーピングしたInP により埋め込む方法があ
る。この方法を用いると、素子容量が大幅に低減できる
ため光素子の高速動作が容易に実現できる。このとき、
十分な絶縁抵抗を得るためには適当な埋め込み層厚が必
要となり、一般的な埋め込み層厚は約３μｍ以上であ
る。これが第１直線領域としての第１直線導波路２１に
対応する。これに続いて、遷移領域２２及び第２直線領
域としての第２直線導波路２３が配置される。このメサ
ストライプ上に誘電体膜が配置され、これを選択成長用
マスクとして選択成長を行い、以下に示した埋め込み構
造を得る。On the other hand, in the selective growth step, there is a method of filling the semiconductor with InP doped with Fe which is a semi-insulating semiconductor. When this method is used, the element capacity can be greatly reduced, and thus the optical element can be easily operated at high speed. At this time,
To obtain a sufficient insulation resistance, an appropriate buried layer thickness is required, and a typical buried layer thickness is about 3 μm or more. This corresponds to the first straight waveguide 21 as the first straight region. Following this, a transition region 22 and a second linear waveguide 23 as a second linear region are arranged. A dielectric film is arranged on the mesa stripe, and selective growth is performed using the dielectric film as a mask for selective growth to obtain a buried structure shown below.
【００１７】第１直線導波路２１では、逆メサ方向に対
し平行に作製されたメサストライプと同様な良好な埋め
込み構造が得られる。In the first straight waveguide 21, a good buried structure similar to a mesa stripe manufactured parallel to the reverse mesa direction can be obtained.
【００１８】遷移領域２２では、上記で述べた順メサ方
向と逆メサ方向に平行なメサストライプの成分が共存す
るため、マスク上に被る方向への成長も進行する。この
際、マスク上への成長は１の方向（逆メサ方向）に向か
って進行するが、第１直線導波路２１の方向へは（１１
１Ｂ）面での成長抑制により進行しない。また、遷移領
域２２の第１直線導波路２１のメサ幅と同じ領域へもマ
スク上への成長は進行しない。In the transition region 22, since the components of the mesa stripe parallel to the forward mesa direction and the reverse mesa direction coexist, the growth in the direction covering the mask also proceeds. At this time, the growth on the mask proceeds in one direction (the reverse mesa direction), but in the direction of the first linear waveguide 21, (11
It does not proceed due to growth suppression on the 1B) plane. Also, the growth on the mask does not progress to the same region of the transition region 22 as the mesa width of the first straight waveguide 21.
【００１９】これは、従来例では、誘導体膜の端面が直
近に位置しており、端面からの成長と両側面からの成長
が接合して複数の結晶面方位が形成されて異常成長を誘
発していたのに対し、本発明では、誘電体膜の端面を第
２直線導波路２３まで遠ざけているいることにより異常
成長が誘発されないこと、遷移領域２２のメサ幅が第２
直線導波路２３のメサ幅まで徐々に広くなることから、
万一、マスク上に成長膜厚分の成長が進行した場合でも
第１直線導波路２１のメサ幅より内側まで到達しないこ
とによるものである。This is because, in the conventional example, the end face of the derivative film is located in the immediate vicinity, and the growth from the end face and the growth from both side faces are joined to form a plurality of crystal plane orientations, which induces abnormal growth. In contrast, according to the present invention, since the end face of the dielectric film is kept away from the second linear waveguide 23, abnormal growth is not induced, and the mesa width of the transition region 22 is reduced to the second linear waveguide 23.
Since the width gradually increases to the mesa width of the linear waveguide 23,
This is because even if the growth of the growth thickness proceeds on the mask, the first straight waveguide 21 does not reach the inside of the mesa width.
【００２０】また、遷移領域２２の広がり角が大きくな
ると、側面での逆メサ方向への成長成分は増加し、順メ
サ方向への成長成分が減少する。良好な埋め込み形状を
得るためには、逆メサ方向の成長成分は少ない方が好ま
しいので、広がり角は両成長成分が１：１となる４５度
より小さいことが望ましい。広がり角は１０度から４５
度に設定される。When the divergence angle of the transition region 22 increases, the growth component in the reverse mesa direction on the side surface increases, and the growth component in the forward mesa direction decreases. In order to obtain a good buried shape, it is preferable that the growth component in the reverse mesa direction is small. Therefore, it is desirable that the spread angle is smaller than 45 degrees at which both growth components become 1: 1. Spread angle from 10 degrees to 45
Set to degree.
【００２１】第２直線導波路２３では、側面において逆
メサ方向に対し平行に作製されたメサストライプと同様
な良好な埋め込み構造が得られる。端面においては順メ
サ方向と平行なメサストライプの場合と同様にマスク上
に被る方向、即ち、逆メサ方向に成長が進行する。これ
は、成長層厚と同程度以下であるので、第２直線導波路
２３の長さは成長層厚、即ち、メサ深さの２倍以下であ
れば十分である。In the second straight waveguide 23, a good buried structure similar to a mesa stripe formed on the side surface in parallel to the reverse mesa direction can be obtained. On the end face, the growth proceeds in the direction over the mask, that is, in the reverse mesa direction, as in the case of the mesa stripe parallel to the forward mesa direction. Since this is not more than the thickness of the growth layer, it is sufficient if the length of the second straight waveguide 23 is not more than twice the thickness of the growth layer, that is, the depth of the mesa.
【００２２】第２直線導波路２３の長さはメサ深さの１
倍から２倍に設定される。端面と側面の境界付近では、
マスク上に被る方向の成長がみられるが、もう一方の側
面との距離が成長層厚より十分広くなるようメサ幅が成
長層厚、即ち、メサ深さの１．５倍以上で５倍以下とな
っているため、従来例のように、側面からの成長層と接
合することがなく、マスク上が完全に覆われることや複
数の結晶面方位が形成されて不安定となり、異常成長を
誘発してInP が成長することがない。The length of the second straight waveguide 23 is 1 of the mesa depth.
It is set from double to double. Near the boundary between the end face and the side face,
The growth in the direction of covering the mask is observed, but the mesa width is set to be 1.5 times or more and 5 times or less the growth layer thickness, that is, the mesa depth so that the distance from the other side surface is sufficiently larger than the growth layer thickness. Therefore, unlike the conventional example, there is no bonding with the growth layer from the side, the mask is completely covered, and multiple crystal plane orientations are formed, making the crystal unstable and inducing abnormal growth. InP does not grow.
【００２３】このように本発明を用いると、直上に誘電
体膜を持ったメサストライプ形状の埋め込み領域と誘電
体膜を持たない乗り上げ成長領域が混在する光半導体装
置において、選択成長用誘電体膜を用いた選択埋め込み
ＭＯＶＰＥ成長時に、メサストライプ上への成長や誘電
体膜上へのInP の異常成長が抑制される。この結果、Ｌ
Ｄなどの場合に大きな吸収損失領域となる異常成長領域
が発生することなく、素子特性を損なわずに異種の素子
構造をモノリシック集積することができる。As described above, according to the present invention, a selective growth dielectric film can be used in an optical semiconductor device in which a mesa stripe-shaped buried region having a dielectric film directly above and a climbing growth region having no dielectric film are mixed. During the selective buried MOVPE growth using GaN, the growth on the mesa stripe and the abnormal growth of InP on the dielectric film are suppressed. As a result, L
In the case of D or the like, a heterogeneous device structure can be monolithically integrated without generating an abnormal growth region which becomes a large absorption loss region and without deteriorating device characteristics.
【００２４】（実施例）以下に本発明の実施例について
図４乃至図６を参照して説明する。尚、実施例における
成長は全てＭＯＶＰＥ法によるものである。図４乃至図
６には本発明の一実施例に係る光半導体装置の製造方法
の工程説明を示してある。(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. The growth in the examples is all based on the MOVPE method. 4 to 6 show process steps of a method for manufacturing an optical semiconductor device according to one embodiment of the present invention.
【００２５】まず、図４(a) に示すように、（１００）
面を表面としたｎ型 (n-)InP基板３１に多重量子井戸
（ＭＱＷ）層３２とｐ型(p-)InP クラッド層３３、p-In
GaAsキャップ層３４を全面に成長する。SiO2膜３５をス
パッタ法により全面に形成し、図４(b) に示すように、
フォトリソグラフィー法とCF4/H2-RIEによりＬＤ領域以
外のSiO2膜３５を除去する。SiO2膜３５をマスクとし
て、p-InGaAsキャップ層３４、(p-)InP クラッド層３３
及びＭＱＷ層３２を順次ウェットエッチングにより除去
する。First, as shown in FIG.
A multi-quantum well (MQW) layer 32 and a p-type (p-) InP cladding layer 33, p-In
A GaAs cap layer 34 is grown on the entire surface. An SiO 2 film 35 is formed on the entire surface by sputtering, and as shown in FIG.
The SiO 2 film 35 other than the LD region is removed by photolithography and CF4 / H 2 -RIE. Using the SiO 2 film 35 as a mask, the p-InGaAs cap layer 34 and the (p-) InP clad layer 33
And the MQW layer 32 are sequentially removed by wet etching.
【００２６】図４(c) に示すように、再度SiO2膜３５を
選択成長用マスクとしてＡＷＧ導波路層３６とｉ型(i-)
InP クラッド層３７、InGaAsキャップ層３８を順次選択
成長する。図４(d) に示すように、SiO2膜３５をウェッ
トエッチングにより除去した後、再度SiO2膜３５を形成
する。フォトリソグラフィー法とCF4/H2-RIEによりスト
ライプを形成する。この際、ストライプはＬＤ領域を第
１直線領域（図１に示した第１直線導波路２１）と対応
させ、ストライプ幅を１．５μｍとし、ＡＷＧ領域に遷
移領域（図１で示した遷移領域２２）及び第２直線領域
（図１で示した第２直線導波路２３）を対応させて第２
直線領域のストライプ幅を１０μｍとし、遷移領域は
１．５μｍから１０μｍまで直線的にストライプ幅を変
化させる。[0026] Figure 4 as shown in (c), AWG waveguide layer 36 and the i-type as a selective growth mask an SiO 2 film 35 again (i-)
An InP cladding layer 37 and an InGaAs cap layer 38 are selectively grown sequentially. As shown in FIG. 4 (d), after the SiO 2 film 35 is removed by wet etching to form the SiO 2 film 35 again. A stripe is formed by photolithography and CF4 / H 2 -RIE. At this time, in the stripe, the LD region corresponds to the first linear region (the first linear waveguide 21 shown in FIG. 1), the stripe width is 1.5 μm, and the transition region (the transition region shown in FIG. 1) is in the AWG region. 22) and the second linear region (the second linear waveguide 23 shown in FIG. 1) in correspondence with the second linear region.
The stripe width of the linear region is 10 μm, and the stripe width of the transition region is linearly changed from 1.5 μm to 10 μm.
【００２７】図５(a) に示すように、SiO2膜３５をマス
クとしてCF4/H2-RIEによりドライエッチングを行い、深
さ３μｍのメサストライプ構造２６を形成する。図５
(b) に示すように、フォトリソグラフィー法とCF4/H2-R
IEにより、第１直線領域４１から遷移領域４２、第２直
線領域４３の端面までの領域以外のSiO2膜３５を除去す
る。これにより、図１に示した本発明の誘電体膜の構造
を形成できる。As shown in FIG. 5A, dry etching is performed by CF 4 / H 2 -RIE using the SiO 2 film 35 as a mask to form a 3 μm deep mesa stripe structure 26. FIG.
As shown in (b), photolithography and CF4 / H 2 -R
By IE, the SiO 2 film 35 other than the region from the first straight region 41 to the transition region 42 and the end face of the second straight region 43 is removed. Thereby, the structure of the dielectric film of the present invention shown in FIG. 1 can be formed.
【００２８】図５(c) に示すように、SiO2膜３５を選択
成長用マスクとしてFeドーピングされた(Fe-)InP埋め込
み層３９を選択成長する。この際、上記で述べた本発明
の効果により、第１直線領域４１と遷移領域４２、及び
第２直線領域４３の端面から３μｍ以上離れた領域のス
トライプ幅１．５μｍの範囲内では異常成長が抑制され
る。図５(d) に示すように、SiO2膜３５をウェットエッ
チングにより除去した後、再度SiO2膜３５を形成する。
フォトリソグラフィー法とCF4/H2-RIEによりＡＷＧ領域
に乗り上げ成長された(Fe-)InP埋め込み層３９を除去す
る。As shown in FIG. 5C, the (Fe-) InP buried layer 39 doped with Fe is selectively grown using the SiO 2 film 35 as a mask for selective growth. At this time, due to the effect of the present invention described above, abnormal growth occurs within a range of a stripe width of 1.5 μm in a region 3 μm or more away from the end face of the first linear region 41, the transition region 42, and the second linear region 43. Is suppressed. As shown in FIG. 5D, after removing the SiO 2 film 35 by wet etching, the SiO 2 film 35 is formed again.
Grown rides AWG region by photolithography and CF4 / H 2 -RIE (Fe-) removing the InP buried layer 39.
【００２９】図６(a) に示すように、SiO2膜３５をウェ
ットエッチングにより除去した後、再度SiO2膜３５を形
成する。前記SiO2膜３５をフォトリソグラフィー法とCF
4/H2-RIEによりＡＷＧ導波路形状に形成する。図６(b)
に示すように、SiO2膜３５をマスクとしてBr2-RIE によ
るドライエッチングによりハイメサ構造２７を形成す
る。図６(c) に示すように、ＬＤ部にAuZnNi電極２８を
形成すると共に、裏面の全面にAuGeNi電極２９を形成
し、劈開により素子端面を形成する。As shown in FIG. 6 (a), after the SiO 2 film 35 is removed by wet etching to form the SiO 2 film 35 again. The SiO 2 film 35 is formed by photolithography and CF.
AWG waveguide is formed by 4 / H 2 -RIE. Fig. 6 (b)
As shown in FIG. 7, a high mesa structure 27 is formed by dry etching with Br 2 -RIE using the SiO 2 film 35 as a mask. As shown in FIG. 6C, an AuZnNi electrode 28 is formed on the LD portion, an AuGeNi electrode 29 is formed on the entire back surface, and an element end face is formed by cleavage.
【００３０】このように、直上にSiO2膜３５を持ったメ
サストライプ構造２６の埋め込み領域とSiO2膜３５を持
たない乗り上げ成長領域であるＡＷＧ領域が混在する光
半導体装置において、選択埋め込みＭＯＶＰＥ成長時
に、メサストライプ構造２６上への成長やSiO2膜３５上
へのInP の異常成長が抑制される。この結果、ＬＤなど
の場合に大きな吸収損失領域となる異常成長領域が発生
することなく、素子特性を損なわずに異種の素子構造を
モノリシック集積することができる。As described above, in the optical semiconductor device in which the buried region of the mesa stripe structure 26 having the SiO 2 film 35 immediately above and the AWG region which is the overgrowth region having no SiO 2 film 35 are mixed, the selective buried MOVPE growth is performed. At times, the growth on the mesa stripe structure 26 and the abnormal growth of InP on the SiO 2 film 35 are suppressed. As a result, a heterogeneous device structure can be monolithically integrated without generating an abnormal growth region that becomes a large absorption loss region in the case of an LD or the like and without deteriorating device characteristics.
【００３１】上記実施例では、InP 基板上での製造方法
を例に挙げて説明したが、結晶構造と成長工程の異方性
が同様であれば、例えば、本発明はGaAs基板上で製造を
行うことも可能である。In the above embodiment, the manufacturing method on an InP substrate has been described as an example. However, if the crystal structure and the anisotropy of the growth process are the same, for example, the present invention can be used for manufacturing on a GaAs substrate. It is also possible to do.
【００３２】[0032]
【発明の効果】本発明の光半導体装置の製造方法は、半
導体基板上に形成された平面構造を持つ平面領域と、平
面領域に接続された誘電体膜を持つメサストライプ構造
のストライプ領域とを有する光半導体装置において、ス
トライプ領域を、直線メサストライプ構造を持つ第１直
線領域と、第１直線領域に接してメサ幅が徐々に変化す
るメサストライプ構造を持つ遷移領域と、遷移領域に接
すると共に前記平面領域に接して直線メサストライプ構
造を持つ第２直線領域とで構成したので、有機金属気相
エピタキシャル法による結晶を選択成長時に、メサスト
ライプ構造の上や誘電体膜の上への結晶成長を抑制する
ことができる。この結果、特性を損なうことなく異種の
素子構造をモノリシック集積することができ、高性能な
モノリシック集積素子を実現できる光半導体装置の製造
方法とすることが可能となる。According to the method of manufacturing an optical semiconductor device of the present invention, a planar region having a planar structure formed on a semiconductor substrate and a stripe region having a mesa stripe structure having a dielectric film connected to the planar region are formed. The optical semiconductor device has a stripe region, a first linear region having a linear mesa stripe structure, a transition region having a mesa stripe structure in which the mesa width gradually changes in contact with the first linear region, and a transition region. Since it is composed of the second linear region having a linear mesa stripe structure in contact with the planar region, the crystal is grown on the mesa stripe structure or on the dielectric film at the time of selective growth of the crystal by the metalorganic vapor phase epitaxial method. Can be suppressed. As a result, heterogeneous element structures can be monolithically integrated without deteriorating characteristics, and a method of manufacturing an optical semiconductor device capable of realizing a high-performance monolithic integrated element can be realized.
【図１】本発明の一実施形態例に係る光半導体装置の製
造方法の工程説明図。FIG. 1 is a process explanatory view of a method for manufacturing an optical semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態例に係る光半導体装置の製
造方法の工程説明図。FIG. 2 is a process explanatory view of a method for manufacturing an optical semiconductor device according to an embodiment of the present invention.
【図３】本発明の一実施形態例に係る光半導体装置の製
造方法の工程説明図。FIG. 3 is a process explanatory view of a method for manufacturing an optical semiconductor device according to an embodiment of the present invention.
【図４】本発明の一実施例に係る光半導体装置の製造方
法の工程説明図。FIG. 4 is a process explanatory view of a method for manufacturing an optical semiconductor device according to one embodiment of the present invention.
【図５】本発明の一実施例に係る光半導体装置の製造方
法の工程説明図。FIG. 5 is a process explanatory view of a method for manufacturing an optical semiconductor device according to one embodiment of the present invention.
【図６】本発明の一実施例に係る光半導体装置の製造方
法の工程説明図。FIG. 6 is a process explanatory view of a method for manufacturing an optical semiconductor device according to one embodiment of the present invention.
【図７】従来の光半導体装置の製造方法の説明図。FIG. 7 is an explanatory diagram of a conventional method for manufacturing an optical semiconductor device.
【図８】従来の光半導体装置の製造方法の説明図。FIG. 8 is an explanatory view of a conventional method for manufacturing an optical semiconductor device.
【図９】従来の光半導体装置の製造方法の説明図。FIG. 9 is an explanatory view of a conventional method for manufacturing an optical semiconductor device.
２１ 第１直線導波路 ２２ 遷移領域 ２３ 第２直線導波路 ２６ メサストライプ構造 ２７ ハイメサ構造 ２８ AuZnNi電極 ２９ AuGeNi電極 ３１ (n-)InP基板 ３２ 多重量子井戸（ＭＱＷ）層 ３３ (p-)InP クラッド層 ３４ p-InGaAsキャップ層 ３５ SiO2膜 ３６ ＡＷＧ導波路層 ３７ (i-)InP クラッド層 ３８ InGaAsキャップ層 ３９ InP 埋め込み層 ４１ 第１直線領域 ４２ 遷移領域 ４３ 第２直線領域Reference Signs List 21 first straight waveguide 22 transition region 23 second straight waveguide 26 mesa stripe structure 27 high mesa structure 28 AuZnNi electrode 29 AuGeNi electrode 31 (n-) InP substrate 32 multiple quantum well (MQW) layer 33 (p-) InP clad Layer 34 p-InGaAs cap layer 35 SiO 2 film 36 AWG waveguide layer 37 (i-) InP clad layer 38 InGaAs cap layer 39 InP buried layer 41 first linear region 42 transition region 43 second linear region
───────────────────────────────────────────────────── フロントページの続き (72)発明者 須崎 泰正 東京都千代田区大手町二丁目３番１号 日 本電信電話株式会社内 Ｆターム(参考） 5F073 AA22 AA74 AB21 BA01 CA12 DA05 DA22 DA25 EA29 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasumasa Suzaki 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5F073 AA22 AA74 AB21 BA01 CA12 DA05 DA22 DA25 EA29
Claims (2)
つ平面領域と、該平面領域に接続された誘電体膜を持つ
メサストライプ構造のストライプ領域とを有する光半導
体装置の製造方法であって、 前記ストライプ領域を、直線メサストライプ構造を持つ
第１直線領域と、該第１直線領域に接してメサ幅が徐々
に変化するメサストライプ構造を持つ遷移領域と、前記
遷移領域に接すると共に前記平面領域に接して直線メサ
ストライプ構造を持つ第２直線領域とで構成し、 前記ストライプ領域の横と前記平面領域の上に有機金属
気相エピタキシャル法により結晶を選択成長させる工程
を有することを特徴とする光半導体装置の製造方法。1. A method for manufacturing an optical semiconductor device, comprising: a planar region having a planar structure formed on a semiconductor substrate; and a stripe region having a mesa stripe structure having a dielectric film connected to the planar region. A first linear region having a linear mesa stripe structure, a transition region having a mesa stripe structure in which a mesa width gradually changes in contact with the first linear region; A second linear region having a linear mesa stripe structure in contact with the region, and a step of selectively growing a crystal by metalorganic vapor phase epitaxy on the side of the stripe region and on the planar region. Manufacturing method of an optical semiconductor device.
３μｍ以下とされ、 前記第２直線領域の直線メサストライプ構造のメサ幅が
メサ深さの１．５倍から５倍とされ、長さがメサ深さの
１倍から２倍とされ、 前記遷移領域のメサ幅が、前記第１直線領域に接するメ
サ幅から前記第２直線領域に接するメサ幅まで徐々に広
がり変化し、広がり角度が１０度から４５度に設定され
ていることを特徴とする光半導体装置の製造方法。2. The mesa width of the straight mesa stripe structure of the first straight region is 3 μm or less, and the mesa width of the straight mesa stripe structure of the second straight region is 1.5 times the mesa depth. The length is 1 to 2 times the mesa depth, and the mesa width of the transition region is from the mesa width contacting the first straight line region to the mesa width contacting the second straight line region. A method for manufacturing an optical semiconductor device, wherein the spread gradually changes and the spread angle is set from 10 degrees to 45 degrees.
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| US10554013B2 (en) | 2015-02-12 | 2020-02-04 | Furukawa Electric Co., Ltd. | Semiconductor laser apparatus |
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