JP2002217331A - Semiconductor chip, wiring board and their manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip, its manufacturing method and a semiconductor device in which the thickness of the semiconductor device, the area of a substrate or the wiring length between semiconductor chips is not increased even if a plurality of semiconductor chips are placed, in layers, on a wiring board. SOLUTION: The semiconductor chip comprises a semiconductor substrate 13, a first external electrode 21 formed on the first surface 14 of the semiconductor substrate 13, a second external electrode 22 formed on the second surface 17 of the semiconductor substrate 13, and a through hole 16 made through the semiconductor substrate 13. The through hole 16 is made in an inclining face 15 formed to have an obtuse internal angle with respect to the second surface 17 and the first external electrode 21 is connected electrically with the second external electrode 22 through a conductive pattern 19 formed via the inner wall of the through hole 16 and the inclining face 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip in which external electrodes on both surfaces of a semiconductor substrate are electrically connected by a conductive pattern formed through a side surface of the semiconductor substrate.
The present invention relates to a wiring board, a method for manufacturing the same, and a semiconductor device using the semiconductor chip.

[0002]

2. Description of the Related Art In recent years, as electronic devices such as computers and communication devices have become smaller and more sophisticated, semiconductor devices have been required to be smaller, denser and faster. For this reason, a multi-chip type semiconductor device has been proposed in which a plurality of semiconductor chips are mounted on a wiring board to form a module, and the size and the density are increased.

[0003] The conventional semiconductor device will be described below by form.

FIGS. 60 to 64 are cross-sectional views showing a conventional semiconductor device.

First, as shown in FIG. 60, a plurality of semiconductor chips 2 are mounted on a wiring board 1 by a flip chip method, and electrodes of the semiconductor chip 2 and connection electrodes of the wiring board 1 are electrically connected by metal bumps 3. The plurality of semiconductor chips are connected to one wiring board and mounted on a plane.

Next, as shown in FIG. 61, a plurality of semiconductor chips 5 are stacked on a wiring board 4, and the electrodes of each semiconductor chip 5 and the connection electrodes of the wiring board 4 are electrically connected by metal wires 6. As a result, the mounting area of the semiconductor chip on the wiring board is smaller than that in the case where the semiconductor chips are arranged on a plane.

Further, as shown in FIG. 62, the electrode-shaped surfaces of two semiconductor chips 7 are opposed to each other, and the electrodes of each semiconductor chip 7 are electrically connected by metal bumps 8 to form a substrate-less laminated structure. It has become.

Further, as shown in FIG.
A plurality of semiconductor devices mounted on the wiring board 11 via the metal bumps 10 by a flip-chip method,
The wiring of each wiring board 11 is
Are electrically connected to each other.

As described above, the conventional semiconductor devices have been described according to their forms. However, each of the conventional semiconductor devices realizes a semiconductor device composed of a plurality of semiconductor chips. A form mounted on a plane, a form laminated on a wiring board, a form in which semiconductor chips are electrically connected to each other by metal bumps with a circuit forming surface facing each other, and a mounted body having a semiconductor chip mounted on a wiring board Was laminated.

Further, since the semiconductor chips constituting each semiconductor device have electrodes formed only on one side thereof, when the semiconductor chips are stacked, metal wires or substrates are used to interconnect the semiconductor chips. Electrical connection was made.

FIG. 64 is a sectional view of a semiconductor device using a conventional resin wiring substrate.

As shown in FIG. 64, one or a plurality of semiconductor chips 2 are mounted on a resin wiring board 1 made of a composite material containing an epoxy resin by a flip chip method on a flat surface. And the connection electrodes on the surface of the resin wiring board 1 are electrically connected by the metal bumps 3. Further, the connection electrodes on the back surface of the resin wiring board 1 are electrically connected to the wiring of the motherboard 405 by the solder balls 404. The connection electrodes on both sides of the resin wiring board 1 are electrically connected by a conductive pattern formed on the inner wall of a through hole (not shown) penetrating the inside of the resin wiring board 1.

As described above, the semiconductor chip 2 is not directly mounted on the motherboard 405 but is mounted on the semiconductor chip 2.
And a motherboard 405 with a resin wiring board 1 interposed therebetween.

[0014]

However, conventional semiconductor devices in which a plurality of semiconductor chips are stacked have the following problems in each form.

First, as shown in FIG. 60, since a plurality of semiconductor chips 2 are arranged on the wiring substrate 1 in a plane, at least the area of the wiring substrate 1 must be larger than the sum of the areas of the plurality of semiconductor chips 2. Therefore, the area of the wiring board 1 must be increased as the number of semiconductor chips 2 mounted increases.

In the semiconductor device shown in FIG. 61, every time the semiconductor chip 5 is stacked, an electrode for connecting the metal wire 6 electrically connected to the wiring of the wiring board 4 is provided on the upper surface of the semiconductor chip 5. Because it needs to be exposed,
The semiconductor chip 5 away from the substrate becomes smaller. Therefore, it is impossible to stack semiconductor chips of the same size. When the number of stacked semiconductor chips 5 increases, the total length of the metal wires 6 also increases, so that there is a problem that the wiring length increases.

In the semiconductor device shown in FIG. 62, since it is impossible to stack three or more semiconductor chips 7, the function as the semiconductor device is limited.

Further, in the semiconductor device shown in FIG. 63, it is necessary to provide the wiring board 11 between the plurality of semiconductor chips 9, so that there is a problem that the thickness of the semiconductor device after the semiconductor chips are stacked becomes large.

As described above, in the conventional semiconductor device, the mounting area increases when a plurality of semiconductor chips are arranged in a plane, and it is impossible to stack semiconductor chips of the same size because electrodes for connecting metal wires must be provided. Yes, the number of stacked semiconductor chips is limited, the function as a semiconductor device is limited, and the thickness of the semiconductor device is increased due to the structure in which a substrate is provided between the stacked semiconductor chips. It was difficult to achieve high speed.

The characteristic change of a resin wiring board using a composite material containing an epoxy resin due to temperature, humidity, etc. is as follows.
It is larger than the characteristic change of the semiconductor chip, and there is a remarkable difference in the thermal expansion coefficient between the silicon and the epoxy resin based composite material, which are the base material of the semiconductor chip, and a large difference in the joint between the semiconductor chip and the resin wiring board. Since stress occurs, there is a risk that the joint may be broken.

Further, since the resin wiring board has insufficient flatness as compared with the semiconductor chip, the flip chip method in which the semiconductor chip is directly joined to the resin wiring board is not used.
There is a problem that the electrical connection between the metal bump formed on the electrode of the semiconductor chip and the connection electrode of the resin wiring board is not stable.

In addition, since the dimensional accuracy of the wiring formed on the resin wiring board is not sufficient as compared with the dimensional accuracy of the semiconductor chip, a positional deviation occurs at the connection between the surface electrode of the semiconductor chip and the connection electrode of the resin wiring board. May occur, resulting in poor bonding.

Furthermore, since the semiconductor chip is mounted on the resin wiring board in a plane, the area of the resin wiring board cannot be made smaller than the total area of the mounted semiconductor chips. There is a problem that the area of the resin wiring board increases as the number of chips increases.

According to the present invention, in order to solve the above-mentioned conventional problems, a plurality of semiconductor chips are connected to a wiring board by electrically connecting electrodes on both surfaces of the semiconductor chip by a conductive pattern passing through a side surface of the semiconductor chip. Even if you stack
Provided are a semiconductor chip, a method of manufacturing the semiconductor chip, and a semiconductor device using the semiconductor chip, which focus on not increasing the thickness and the substrate area of the semiconductor device on which the semiconductor chips are stacked and increasing the wiring length between the semiconductor chips. Things.

The present invention provides a wiring board using silicon as a base material of the wiring board and a method of manufacturing the same, in order to solve the above-mentioned conventional problems.

[0026]

According to a first aspect of the present invention, there is provided a semiconductor chip having a semiconductor substrate, a first external electrode formed on a first surface of the semiconductor substrate, and a second external electrode formed on a second surface of the semiconductor substrate. A semiconductor chip having a second external electrode and a through-hole formed in the semiconductor substrate, wherein the through-hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle. The external electrode and the second external electrode are electrically connected by a conductive pattern formed through the inner wall and the slope of the through hole.

According to the first aspect of the present invention, it is possible to realize a semiconductor chip in which electrodes on both sides are connected through a through hole and a conductive pattern formed on a slope, so that a semiconductor chip having stacked semiconductor chips can be realized. It is possible to reduce the size, density, and speed of the device.

According to a second aspect of the present invention, there is provided a semiconductor chip comprising: a semiconductor substrate; a surface electrode formed on a first surface of the semiconductor substrate;
A through hole formed in the semiconductor substrate, wherein the through hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first surface excluding the surface electrode;
A first insulating layer formed on an inner wall, a slope, and a second surface of the through hole; a conductive pattern filled in the through hole and formed on the first insulating layer and the surface electrode; A second insulating layer formed by opening a part of the surface of the conductive pattern as a first external electrode and opening a part of the surface of the conductive pattern on the second surface as a second external electrode. A semiconductor chip characterized in that:

According to the semiconductor chip of the second aspect, by forming such a conductive pattern, electrodes between the semiconductor substrate and the conductive pattern and electrodes on both surfaces of the semiconductor substrate exposed from the insulating layer are electrically connected. It can be connected, and since the electrodes and conductive patterns are covered with an insulating layer, it is possible to prevent electrical problems such as short-circuits and to protect the semiconductor chip against external impacts. And speeding up are also possible.

According to a third aspect of the present invention, there is provided a semiconductor chip having a surface formed with elements and an inclined surface formed at an acute angle with the back surface facing the surface in parallel with the surface and a concave portion formed around the surface and continuous with the inclined surface. A first electrode formed on the front surface, a second electrode formed on the back surface, and a first electrode formed in the concave portion and on the inclined surface. It is provided with a conductive pattern for connecting to two electrodes.

According to a third aspect of the present invention, there is provided a semiconductor chip comprising a semiconductor substrate on which elements are integrally formed, and having a front surface electrode and a back surface electrode connected through a conductive pattern in a recess around the surface and on the side surface. A chip semiconductor device chip is obtained. Therefore, a multi-chip semiconductor device using such a chip for a multi-chip semiconductor device,
A small, high-density and high-speed multi-chip semiconductor device can be realized. Further, by forming and joining the conductive pattern on the inclined surface and the conductive pattern in the concave portion, processing can be performed easily and the bonding area between the conductive patterns can be increased.

According to a fourth aspect of the present invention, there is provided a semiconductor chip in which an element is integrated and formed, and a back surface facing the surface in parallel with the surface, a slope formed at an acute angle with the front surface, and a recess formed around the surface and continuous with the slope. A first insulating layer formed on a surface other than the inner wall of the concave portion and the surface electrode, and a formation of the first insulating layer. A first conductive pattern formed in a shape of a desired wiring and electrode by connecting the surface electrode on the surface on which the first insulating layer is formed by filling the formed concave portion, and opening an electrode portion formed by the first conductive pattern; A second insulating layer formed on the front surface, a slope portion where the first conductive pattern of the concave portion is continuously exposed on the slope around the back surface, and a slope where the first conductive pattern is exposed on the back surface and the slope. The opening formed part An insulating layer, a second conductive pattern which is connected to the first conductive pattern on the slope on which the third insulating layer is formed and the back surface of the semiconductor chip and is formed in a desired wiring and electrode shape; And a fourth insulating layer formed on the back surface and the inclined surface of the semiconductor chip by opening an electrode portion formed by the conductive pattern.

According to the semiconductor chip of the fourth aspect, the first electrode, the second electrode, and the wiring connecting the first electrode and the second electrode passing through the inside of the recess and on the side surface are formed by the conductive pattern. The conductive pattern is electrically connected to the surface electrode, an insulating layer is formed on the surface of the conductive pattern excluding the first electrode and the second electrode, and an insulating layer is also formed between the conductive pattern and the semiconductor substrate. The obtained multi-chip semiconductor device chip is obtained. Therefore, a multichip semiconductor device using such a chip for a multichip semiconductor device can realize a small, high-density, high-speed multichip semiconductor device as in the first and second aspects.

According to a fifth aspect of the present invention, there is provided a semiconductor chip.
Alternatively, in claim 4, a laminated metal film is formed between the first insulating layer and the conductive pattern and between the surface electrode and the conductive pattern.

According to the semiconductor chip of the fifth aspect, in addition to the same effects as those of the second or fourth aspect, the electrolytic chip is formed by the barrier layer and the seed layer constituting the laminated metal film by forming the laminated metal film. A conductive pattern using a plating method can be formed, and diffusion of constituent elements of the conductive pattern can be prevented.

According to a sixth aspect of the present invention, there is provided the semiconductor chip according to the second, fourth or fifth aspect, except that at least one conductive pattern is formed on the surface electrode.

According to the semiconductor chip of the sixth aspect, in addition to the same effects as those of the second, fourth or fifth aspect,
By using a semiconductor chip having at least one conductive pattern that is not connected to an integrated circuit, when stacking a plurality of semiconductor chips, a specific semiconductor chip is not electrically connected to an integrated circuit of the specific semiconductor chip. Other semiconductor chips can be electrically connected to each other.

The semiconductor chip according to the seventh aspect is the second aspect.
Alternatively, in claim 4, a vertical side surface is formed by the insulating resin supplied on the slope.

According to the semiconductor chip of the seventh aspect, in addition to the effect similar to the second or fourth aspect, a relatively thick insulating layer is formed on the second conductive pattern formed on the slope. In addition, the side surface of the semiconductor chip can be reinforced and the protection of the conductive pattern on the slope can be enhanced.

The semiconductor chip according to the eighth aspect is the fifth aspect.
Wherein the laminated metal film comprises a barrier layer and a seed layer.

According to the semiconductor chip of the eighth aspect, in addition to the same effects as those of the fifth aspect, the diffusion of the constituent elements of the conductive pattern and the deterioration of the characteristics of the semiconductor chip can be prevented by the barrier layer. Further, by providing the seed layer, it is possible to plate the conductive pattern by the electrolytic plating method.

According to a ninth aspect of the present invention, in the wiring board, the base material is made of silicon, the wiring board has a plurality of through holes, and the first conductive pattern is formed on the surface of the wiring board. The hole is provided on a slope formed by forming an obtuse angle with the back surface of the wiring substrate, a second conductive pattern is formed on the back surface and the slope, and the first conductive pattern and the second conductive pattern are formed by a plurality of holes. It is characterized by being electrically connected by a third conductive pattern formed in the through hole.

According to the ninth aspect of the present invention, the formation of the slope makes it unnecessary to form the hole deeply, so that the processing time can be reduced and the cost can be reduced. Further, since it is not necessary to grind the silicon substrate to reduce its thickness, stable conveyance can be ensured.

According to a tenth aspect of the present invention, there is provided a wiring board for a multichip semiconductor device in which electronic components are mounted on a wiring board and mounted on a motherboard, wherein the wiring board has a silicon substrate made of silicon. A first conductive pattern comprising at least one layer for mounting and wiring electronic components on a surface of a silicon substrate, and a second conductive pattern comprising at least one layer having electrodes for mounting on a motherboard on a back surface of the silicon substrate Wherein the first conductive pattern and the second conductive pattern are electrically connected by a third conductive pattern formed on a side surface of the silicon substrate.

According to a tenth aspect of the present invention, there is provided a wiring board having a first conductive pattern for mounting and wiring electronic components on the front surface and a second conductive pattern having electrodes for mounting on the motherboard on the rear surface. A wiring substrate made of silicon is obtained in which the first conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface.

Since the silicon wiring substrate is not changed in shape due to humidity and is formed of the same silicon as the semiconductor chip, the change in shape such as expansion and contraction due to temperature change is the same as that of the semiconductor chip. The degree of accuracy is high, the dimensional accuracy of the electrode position is high, and the pitch of the connection electrodes and the density of the wiring can be increased at the same level as the semiconductor chip.

Therefore, in a multi-chip semiconductor device using such a silicon wiring substrate, stress is reduced at the bonding portion of the metal bump to enhance reliability, and bonding stability is improved by flatness and dimensional accuracy of the wiring substrate. Therefore, it is possible to increase the wiring density at a level that cannot be achieved by a resin wiring substrate, and it is possible to realize small size, high density, and high speed.

According to a eleventh aspect of the present invention, there is provided a wiring board for a multi-chip semiconductor device in which electronic components are mounted on a wiring board and mounted on a motherboard, wherein the wiring board forms a side surface at an acute angle with the surface. A first conductive pattern formed of at least one layer of an electrode formed in the surface and the concave portion of the silicon substrate having a silicon substrate having a concave portion formed around the surface; And a second conductive pattern formed of at least one layer having electrodes and connected to the first conductive pattern.

According to the eleventh aspect of the present invention, the first conductive pattern has the first conductive pattern on the front surface and the second conductive pattern on the back surface, and the first conductive pattern and the second conductive pattern are directly electrically connected. A wiring substrate made of connected silicon is obtained.

Therefore, in the multi-chip semiconductor device using such a silicon wiring substrate, the stress at the junction of the metal bumps is reduced and the reliability is improved, and the flatness of the wiring substrate and the flatness of the wiring substrate are improved. The dimensional accuracy enhances the stability of bonding, enables the wiring density to be improved at a level that cannot be achieved by a resin wiring board, and realizes compactness, high density, and high speed.

According to a twelfth aspect of the present invention, in the ninth or eleventh aspect, an insulating layer is formed on a side surface so as to be perpendicular to the surface of the substrate.

According to the twelfth aspect of the present invention, in addition to the same effect as the ninth or eleventh aspect, the side surface of the wiring substrate can be reinforced and the protection of the conductive pattern on the side surface can be improved.

According to a thirteenth aspect of the present invention, there is provided the wiring board according to the ninth aspect.
In a tenth or eleventh aspect, a low-stress resin layer is provided between one or both of the first conductive pattern and the substrate and between the second conductive pattern and the substrate.

According to the wiring board of the thirteenth aspect, in addition to the same effects as those of the ninth, tenth, and eleventh aspects, the stress due to the temperature change generated between the semiconductor chip and the wiring board is alleviated. Therefore, the mounting reliability of the semiconductor chip can be improved.

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor chip, comprising the steps of: preparing a semiconductor substrate; forming a hole in a peripheral portion of the semiconductor substrate in units of semiconductor chips; Forming a first conductive pattern electrically connected to the first external electrode in the hole and the first surface, and an inner angle with the second surface of the semiconductor substrate becomes obtuse. Forming a slope and penetrating the hole, forming a second external electrode on the second surface, and electrically connecting the second external electrode and the first conductive pattern on the slope and the second surface. Forming a second conductive pattern connected to the second conductive pattern.

According to the method of manufacturing a semiconductor chip according to the fourteenth aspect, the slope formed by the obtuse angle formed by the second surface and the through-hole is formed between the slope and the first surface. By forming a conductive pattern in the through hole, the first surface and the second surface are formed.
Can be electrically connected to the first surface and, unlike the case where a through hole is first formed from the first surface to the second surface, a deep hole is formed or the semiconductor substrate is thinly formed on the back surface. It is not necessary to polish from the beginning, and the processing time can be shortened, so that the cost can be reduced. Further, the transfer is easier than a thinly processed semiconductor substrate.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor chip, comprising the steps of: preparing a semiconductor substrate; forming a hole in a peripheral portion of the semiconductor substrate in units of semiconductor chips; Forming a first insulating layer on the surface and on the inner wall of the hole, forming a first conductive pattern on the first insulating layer and filling the hole, and forming a first conductive pattern on the surface of the first conductive pattern. Forming a second insulating layer having a portion opened as a first external electrode; and forming a second insulating layer on the semiconductor substrate.
Grinding the surface to a desired thickness, forming a slope having an obtuse internal angle with the second surface at the boundary between the semiconductor chips on the second surface, and passing a hole through the slope. Forming a third insulating layer on the inclined surface and the second surface excluding the hole, forming a second conductive pattern electrically connected to the first conductive pattern on the third insulating layer,
Forming a fourth insulating layer by opening a part of the surface of the second conductive pattern as a second external electrode.

According to the method of manufacturing a semiconductor chip of the present invention, conductive patterns such as electrodes and wirings can be formed on the semiconductor substrate at one time, and the formation of the oblique surface at an obtuse angle with the back surface allows simultaneous formation of holes. Since the inner first conductive pattern can be exposed on the slope, the number of manufacturing steps and manufacturing cost of the semiconductor chip can be significantly reduced.

According to a sixteenth aspect of the present invention, there is provided a method of manufacturing a plurality of semiconductor chips obtained from a wafer having a front surface on which elements are integrated and a back surface parallel to the front surface. Forming a recess around the semiconductor chip, forming an inclined surface at an acute angle with the front surface on the semiconductor substrate, forming a first external electrode on the front surface, and forming a second external electrode on the back surface Forming a first conductive pattern connected to the first external electrode in the recess and on the surface thereof; and forming a second conductive electrode connecting the second external electrode and the first conductive pattern on the inclined surface and the back surface. Forming a pattern.

According to the method for manufacturing a semiconductor chip of the present invention, since the concave portion around the front surface and the side surface forming an acute angle with the front surface are formed in the semiconductor substrate, a conductive pattern is formed from the front surface and the back surface there. For example, after forming a first conductive pattern on the front surface side of a semiconductor substrate having a concave portion formed around the front surface, a second conductive pattern is formed only on the back surface side having an inclined surface forming an acute angle with the front surface. In this case, the wiring can be formed so as to conduct to the surface, and the front and back conducting electrodes can be easily formed. Therefore, a multichip semiconductor chip can be easily realized.

A method of manufacturing a semiconductor chip according to a seventeenth aspect is a method of manufacturing a plurality of semiconductor chips obtained from a wafer having a front surface on which elements are integrated and a back surface parallel to the front surface. Forming a concave portion around the semiconductor chip over the scribe line on the surface scribe line, forming a first insulating layer on the inner wall of the concave portion and on a surface other than the surface electrode of the semiconductor chip; Bury the concave portion in which the insulating layer is formed, and
Forming a first conductive pattern in a desired wiring and electrode shape on the surface on which the insulating layer is formed, and forming an second insulating layer on the surface by opening an electrode portion of the first conductive pattern. A step of polishing the wafer to a desired thickness from the back surface, and forming an inclined surface at an acute angle with the front surface of the wafer from the back surface to the periphery of the semiconductor chip along the scribe line, and the first conductive pattern in the recess. Exposing the exposed portion of the first conductive pattern on the back surface and the slope to form a third insulating layer; and forming the third insulating layer on the slope and the semiconductor chip on which the third insulating layer is formed. A step of forming a second conductive pattern in a shape of a desired wiring and electrode connected to the first conductive pattern exposed from the slope on the back surface, and opening an electrode portion of the second conductive pattern to form a semiconductor chip It is intended to include a step of forming a fourth insulating layer formed on the back surface and the slope.

According to the method of manufacturing a semiconductor chip according to the seventeenth aspect, it is possible to collectively form a concave portion, a conductive pattern such as an electrode and a wiring on a wafer, and form an acute angle with the front surface by forming a slope from the back surface. It is possible to simultaneously form the side surface to be formed, divide the semiconductor chip into individual pieces, and make the first conductive pattern visible from the back surface. Therefore, the number of manufacturing steps and the manufacturing cost of the multi-chip semiconductor device chip can be significantly reduced.

A method of manufacturing a semiconductor chip according to claim 18 is the method according to claim 14 or 16, wherein the step of forming the first external electrode and the step of forming the first conductive pattern are performed simultaneously. .

According to the method of manufacturing a semiconductor chip of the eighteenth aspect, in addition to the same effect as the fourteenth or sixteenth aspect, the first external electrode and the first conductive pattern can be simultaneously formed, so that the number of manufacturing steps is reduced. Can be reduced.

According to a nineteenth aspect of the present invention, in the method of the fourteenth or sixteenth aspect, the step of forming the second external electrode and the step of forming the second conductive pattern are simultaneously performed. .

According to the method of manufacturing a semiconductor chip according to the nineteenth aspect, in addition to the same effects as those of the fourteenth and sixteenth aspects, the second external electrode and the second conductive pattern can be simultaneously formed. Can be further reduced.

According to a twentieth aspect of the present invention, there is provided a semiconductor chip manufacturing method according to the fifteenth or seventeenth aspect, wherein a first insulating layer and a first conductive pattern are formed between the step of forming the first insulating layer and the step of forming the first conductive pattern. A step of forming a first laminated metal film on the insulating layer is provided, and a second step is formed on the third insulating layer between the step of forming the third insulating layer and the step of forming the second conductive pattern.
Characterized by providing a step of forming a laminated metal film.

According to the method of manufacturing a semiconductor chip according to the twentieth aspect, in addition to the same effects as those of the fifteenth and seventeenth aspects, by providing the laminated metal film in this manner, the electroplating of the conductive pattern and the conductive pattern Can be prevented from spreading.

According to a twenty-first aspect of the present invention, in the method of manufacturing a semiconductor chip according to the fifteenth aspect, the fourth insulating layer is formed by applying and curing a liquid resin.
The semiconductor chip is divided into individual pieces by dicing.

According to the method of manufacturing a semiconductor chip of the twenty-first aspect, in addition to the same effects as in the fifteenth, seventeenth, or twentieth aspect, the fourth resin layer is formed by using a liquid resin. Thereby, the thickness of the resin formed on the slope can be sufficiently ensured, and the conductive pattern can be protected from external impact. In addition, by dividing the resin-coated portion by dicing, the resin can absorb mechanical and thermal shocks caused by cutting resistance and the like at the time of dicing. From the state where various films are formed on the entire surface of the semiconductor chip, the semiconductor chip can be processed at high speed and in a stable state.

According to a twenty-second aspect of the present invention, there is provided a method of manufacturing a semiconductor chip according to the fifteenth or seventeenth aspect, wherein the inclined surface having an obtuse angle with the second surface is formed at an end of the second surface and the hole is formed. Is carried out by bevel cutting from the second surface.

According to the method of manufacturing a semiconductor chip of the twenty-second aspect, in addition to the same effects as those of the fifteenth and seventeenth aspects, the slope can be easily formed in a short time and the first aspect can be formed.
Can be exposed.

According to a twenty-third aspect of the present invention, in the method for manufacturing a semiconductor chip according to the fifteenth, seventeenth or twentieth aspect, the rate at which the third insulating layer is etched is reduced by the first insulating layer and the second insulating layer. Is higher than the etching speed.

According to the method of manufacturing a semiconductor chip according to the twenty-third aspect, in addition to the same effect as the fifteenth aspect, the seventeenth aspect or the twentieth aspect, the third insulating layer is formed on the entire second surface and the inclined surface. After the formation, when opening the third insulating layer by etching to expose the first conductive pattern,
Since the third insulating layer can be selectively etched and opened without substantially etching the first insulating layer, the first insulating layer that insulates the first conductive pattern from the semiconductor substrate is partially removed. It won't. Claim 2
According to a fourth aspect of the present invention, in the method for manufacturing a semiconductor chip, the concave portion is a groove formed by dicing.

According to the method of manufacturing a semiconductor chip according to the twenty-fourth aspect, in addition to the same effect as the seventeenth aspect, a groove can be formed in a batch in a wafer state in a short time, thereby reducing manufacturing steps and manufacturing costs. Can be reduced.

The method for manufacturing a wiring board according to claim 25 is
A step of forming a hole from the surface of the silicon substrate, a step of forming a first conductive pattern in the surface and the hole, and forming an obtuse angle with the back surface of the silicon substrate at an obtuse angle by forming a boundary portion of the back surface substrate unit. Forming a first conductive pattern in a region to be sandwiched and penetrating a hole;
Forming a second conductive pattern electrically connected to the conductive pattern on the back surface and the slope.

According to the method of manufacturing a wiring board according to the twenty-fifth aspect, since the hole is made to penetrate by forming the slope from the back surface of the wiring board, the processing time of the hole can be reduced and the processing cost can be reduced. .

The method of manufacturing a wiring board according to claim 26 is
A step of forming a first conductive pattern comprising at least one layer for mounting and wiring electronic components on a surface of a silicon wafer; and a second layer comprising at least one layer having electrodes for mounting on a motherboard on a back surface of the silicon wafer.
Forming a conductive pattern, and dividing the silicon wafer into individual silicon substrates to form side surfaces,
Forming a third conductive pattern on a side surface for electrically connecting the first conductive pattern and the second conductive pattern. After the step of forming the first conductive pattern, individual pieces are separated from the silicon wafer. A step of forming a side surface by dividing the silicon substrate into the silicon substrate, and thereafter, a step of forming a second conductive pattern and a step of forming a third conductive pattern are performed simultaneously.

According to the method for manufacturing a wiring board according to the twenty-sixth aspect, there is provided a first conductive pattern for mounting and wiring electronic components on the front surface and a second conductive pattern including electrodes for mounting on the motherboard on the rear surface. Then, a wiring substrate made of silicon is obtained in which the first conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface. Further, it is possible to easily realize a multi-chip semiconductor wiring substrate having a front electrode and a back electrode electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface. Further, after the step of forming the first conductive pattern, a step of dividing the silicon wafer into individual silicon substrates to form side surfaces is performed, and thereafter, a step of forming a second conductive pattern and a step of forming the third conductive pattern Since the step of forming the substrate is performed simultaneously, the number of manufacturing steps can be reduced.

The method for manufacturing a wiring board according to claim 27 is characterized in that
A step of forming a recess around the surface of the silicon substrate in a wafer state, a step of forming a first conductive pattern having at least one layer having electrodes in the surface and the recess, and forming a slope at an acute angle with the surface on the silicon substrate Forming a
Electrically connecting the back surface and the slope of the silicon substrate with the first conductive pattern to form a second conductive pattern including at least one layer having electrodes.

According to the method for manufacturing a wiring board according to the twenty-seventh aspect, the first conductive pattern is provided on the front surface and the second conductive pattern is provided on the back surface, and the first conductive pattern and the second conductive pattern are directly connected to each other. A wiring substrate made of electrically connected silicon is obtained. Further, since the concave portion and the side surface forming an acute angle with the front surface are formed in the wiring substrate, it is possible to form a wiring that conducts between the front and back surfaces only by forming a conductive pattern from the front surface and the back surface. Further, it is possible to easily realize a multi-chip semiconductor wiring substrate having a front surface electrode and a back surface electrode which are electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface.

The method of manufacturing a wiring board according to claim 28 is
28. The method according to claim 25, further comprising the step of forming an insulating layer on the slope so as to be perpendicular to the surface of the silicon substrate, wherein the insulating layer is formed by applying and curing a liquid resin, and is divided into individual pieces by dicing. It is characterized by doing.

The method of manufacturing a wiring board according to claim 28 is
In addition to the same effects as those of claim 25 or claim 27, the liquid resin is supplied on a slope, and the cured resin portion is diced and divided into individual pieces of the substrate, so that mechanical interference caused by cutting resistance during dicing and mechanical interference can be reduced. The resin absorbs distortion due to frictional heat, and can prevent problems such as chipping.

The method for manufacturing a wiring board according to claim 29 is
25. The method according to claim 25, wherein a step of forming a low-stress resin layer between the substrate and the first conductive pattern or between the substrate and the second conductive pattern is provided. .

According to the method of manufacturing a wiring board described in claim 29, in addition to the same effect as in claim 25 or 27, the stress due to a temperature change generated between the semiconductor chip and the wiring board is alleviated. Therefore, the mounting reliability of the semiconductor chip can be improved.

The semiconductor device according to claim 30, wherein the semiconductor substrate, the first external electrode formed on the first surface of the semiconductor substrate, and the second external electrode formed on the second surface of the semiconductor substrate And a through hole formed in the semiconductor substrate, wherein the through hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first external electrode, the second external electrode, Means that a plurality of semiconductor chips electrically connected by a conductive pattern formed through the inner wall and the slope of the through-hole are electrically connected to respective first external electrodes and second external electrodes. And laminated.

According to the semiconductor device of the thirtieth aspect, the semiconductor chip having the first external electrode and the second external electrode connected via the conductive pattern formed on the inner wall and the slope of the through hole is laminated. Thus, a semiconductor device in which the semiconductor chips are electrically connected to each other via the electrodes on both surfaces thereof is obtained. Since the semiconductor chips are not arranged in a plane on the wiring board, the mounting area can be reduced. Further, since there is no need to provide electrodes for connecting metal wires, two or more semiconductor chips of the same size and different sizes can be stacked in a desired order, and the wiring length between the semiconductor chips can be increased. , And the thickness of the stacked layers can be reduced, and a semiconductor device corresponding to miniaturization, high density, and high speed can be realized.

A semiconductor device according to claim 31, wherein a semiconductor substrate, a first external electrode formed on a first surface of the semiconductor substrate, and a second external electrode formed on a second surface of the semiconductor substrate And a through hole formed in the semiconductor substrate, wherein the through hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first external electrode, the second external electrode, Is a first semiconductor chip 2 electrically connected by a first conductive pattern formed through the inner wall and the slope of the through hole.
A third external electrode formed in a portion of the third surface other than the element forming region, a fourth external electrode formed in a portion of the fourth surface other than the element forming region, Is provided with a second semiconductor chip electrically connected by the second conductive pattern, and the first semiconductor chip and the second semiconductor chip are electrically connected directly or via a connection member. It is characterized by the following.

According to the semiconductor device of the thirty-first aspect, the mounting area is reduced, the wiring length between the semiconductor chips is reduced,
A multi-chip type semiconductor device with a low stacking height, small size, high density, and high speed can be realized.

A semiconductor device according to a thirty-second aspect is a multi-chip type semiconductor device in which a plurality of semiconductor chips each formed of a semiconductor substrate having elements formed on the surface thereof are stacked, wherein the stacked semiconductor chips are: A semiconductor substrate having a front surface, a back surface facing in parallel with the front surface, a slope formed at an acute angle with the front surface, and a concave portion formed around the front surface, and a first surface formed on the front surface; A semiconductor having an external electrode, a second external electrode formed on the back surface, and a conductive pattern formed in the recess and on the side surface for connecting the first external electrode and the second external electrode, and The semiconductor device is characterized in that the chip is electrically connected to another semiconductor chip via the first external electrode and the second external electrode.

According to the semiconductor device of the thirty-second aspect, a semiconductor chip having a first external electrode and a second external electrode connected via a conductive pattern is stacked, and the first external electrode and the second external electrode are stacked. Since each semiconductor chip is electrically connected via external electrodes, the mounting area is small and semiconductor chips of the same size can be stacked without arranging multiple semiconductor chips on the wiring board in a plane. In addition, semiconductor chips of different sizes can be stacked in a desired order, the wiring length between the semiconductor chips is short, the stacking height is low, and the number of stacked semiconductor chips is two or more. Thus, a multi-chip semiconductor device which is small, high-density and high-speed can be realized. Further, since the semiconductor substrate has a slope formed at an acute angle with the surface and a concave portion formed around the surface, the semiconductor chip can be easily manufactured.

The semiconductor device according to the thirty-third aspect is the third aspect.
2, wherein the stacked semiconductor chips are electrically connected to the semiconductor chips immediately above and immediately below the semiconductor chips by electrodes directly or via connection members.

According to the semiconductor device of the thirty-third aspect, in addition to the same effects as the thirty-second aspect, the semiconductor chips are connected to each other in a plane of the semiconductor chip such that the wiring length is short and the stacking height is low. The obtained multi-chip semiconductor device is obtained. Therefore, it is possible to realize a small-sized, high-density, high-speed multi-chip semiconductor device having a small mounting area, a short wiring length between semiconductor chips, a low stacking height.

[0094]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor chip, a method of manufacturing the same, and a semiconductor device using the semiconductor chip of the present invention will be described with reference to the drawings.

First, the semiconductor chip of the present invention will be described. First, a first embodiment of the present invention will be described.

FIG. 1 is a sectional view of a semiconductor chip of the present embodiment. As shown in FIG. 1, an element (not shown) and a multilayer conductive pattern (not shown) are formed on a first surface 14 which is a surface of a semiconductor substrate 13, from the first surface 14 to the slope 15. A slope 15 formed with a processed through hole 16 and formed such that an inner angle formed with a second surface 17 as a bottom surface is an obtuse angle forms a part of the outer shape of the semiconductor substrate 13. In the present embodiment, the interior angle between the slope and the second surface is 1
The angle is 35 degrees, and the slope is formed to a position 50 [μm] from the second surface. This makes it easier for a certain amount of resin supplied on the slope to adhere to the surface, protects the conductive pattern against external impact, and electrically connects the electrodes formed on the surface of the semiconductor substrate. Since the distance between the conductive patterns is shortened, it is possible to cope with high speed.

The surface electrode 18 formed on the first surface 14 is electrically connected to a conductive pattern 19 formed on the inner wall of the through hole 16 and the surface of the slope 15. The conductive pattern 19 may be filled in the through hole 16,
The thickness of the conductive pattern 19 is preferably 5 to 15 [μm].
In the present embodiment, it is 10 [μm]. And
The material of the surface electrode 18 is made of aluminum (Al), copper (Cu), or the like.
1.0 [μm], which differs depending on the manufacturing process of the semiconductor chip. For example, in a manufacturing process for forming a wiring made of copper (Cu) having a wiring width of 0.13 [μm],
The thickness of the wiring is 0.45 [μm].

Next, the insulating layer formed on the formed surface electrode and conductive pattern will be described. A first insulating layer 20 is formed on the first surface 14, the second surface 17, the inclined surface 15, and the inner wall of the through hole 16 of the semiconductor substrate 13 excluding the surface electrode 18, and the thickness of the first insulating layer 20 is , Preferably 0.5 to 10 [μm].
[μm]. Then, a part of the conductive pattern 19 is opened as the first external electrode 21 and the second external electrode 22, and on the conductive pattern 19 except those electrodes, and
First insulating layer 20 on which conductive pattern 19 is not formed
And on the first insulating layer 20 on the second surface 17,
A second insulating layer 23 is formed.

Here, the thickness of the second insulating layer 23 is 1 to 3
0 [μm], and in this embodiment, silicon dioxide (S
iO2), silicon nitride (SiN) and oxynitride film (Si
1 [μm] for ON), 7 [μm] for polyimide
m]. The second insulating layer 23 may be mainly made of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment. Also, the first external electrode 21
Since the second external electrode 22 is formed as a part of the conductive pattern 19, the thickness of the first external electrode 21 and the thickness of the second external electrode 22 are the same as the thickness of the conductive pattern 19.

As described above, in the semiconductor chip of this embodiment, since the surface electrodes of the semiconductor substrate and the external electrodes formed on both surfaces of the semiconductor substrate are electrically connected, a plurality of semiconductor chips are stacked facing each other. In this state, electrical connection between the semiconductor chips becomes possible.

Next, a method for manufacturing the semiconductor chip of the present embodiment will be described.

FIG. 2 to FIG. 16 are cross-sectional views of each step of the method for manufacturing a semiconductor chip of the present embodiment.

First, as shown in FIG. 2A, a wafer-like semiconductor substrate 13 composed of a plurality of semiconductor chip units and having a thickness of 600 to 1000 [μm] is prepared. An element (not shown), a multilayer conductive pattern (not shown), and a surface electrode 18 are formed on the first surface 14. Here, the position where the surface electrode 18 is formed is not particularly limited, but is formed around the semiconductor chip unit in the present embodiment. Also, the surface electrode 18
In the present embodiment, silicon nitride (SiN)
Is formed, but the surface insulating layer 25 may be formed of a material other than SiN, and is not particularly limited as long as the material has a function as a protective film. Further, the thickness of the surface insulating layer 25 is 0.5 to 10 [μm], and is 1 [μm] in the present embodiment. Since the surface insulating layer 25 is intended to protect against external impact, it is not particularly necessary to form the surface insulating layer 25.

Dotted lines indicate the positions where both ends in the width direction of the cutting blade pass during dicing for dividing the semiconductor substrate into semiconductor chip units, and the center of the two dotted lines indicates the position between the semiconductor chip units. It is the boundary of.

Next, the hole forming process will be described.

FIG. 2B is a cross-sectional view showing a state where a hole is machined from the first surface of the semiconductor substrate.

As shown in FIG. 2B, RIE (Rea)
A hole 26 having a depth of 20 to 100 [μm] is formed from the first surface 14 of the semiconductor substrate 13 without penetrating in the thickness direction by an active ion etching (active ion etching) method. It is formed around the unit, and in the present embodiment, on a straight line at a position of 50 [μm] from the boundary line of the semiconductor chip unit, it is the position closest to the corresponding hole. In this embodiment, the depth of the hole is 70 μ
m], and the length of the through hole through which the hole penetrated by forming the slope is about 50 [μm]. The hole 26
Is not limited to the RIE method, and light etching, wet etching, ultrasonic machining, electric discharge machining, and the like may be used, and the above-described various machining methods may be combined.

As described above, the RIE method, which is a method of processing a hole formed in a semiconductor substrate, is a dry etching method using reactive gas plasma, and is a method used for fine processing of a semiconductor wafer. A mask covering portions other than the holes is formed on the insulating layer so that the portion is not etched, and the mask is removed after etching.

Next, as shown in FIG.
8 except for the opening of FIG.
After the first insulating layer 20 is formed thereon, a mask having an opening at the surface electrode 18 is formed on the first insulating layer 20, and the insulating layer formed on the surface electrode 18 is etched.
Remove the mask. Here, the first insulating layer 20 has a CV
Silicon dioxide (SiO ₂ ), silicon nitride (Si) by methods such as D method, sputtering method, photo CVD method, coating, etc.
N), an oxynitride film (SiON), a film made of polyimide or the like is formed.

Next, as shown in FIG. 3D, a first laminated metal film 27 is formed on the first insulating layer 20, and the first laminated metal film 27 has a seed layer on the barrier layer. Stacked 2
It has a layered structure. Here, the barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer is made of any of titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), and nickel (Ni), and the seed layer is made of copper (Cu), gold (Au), and silver (Ag). ), Nickel (N
i) and the like are used.

Next, as shown in FIG. 4E, a first conductive pattern 28 is formed on the inner wall of the hole 26 by electrolytic plating using the first laminated metal film 27 as an electrode, and a desired wiring and The electrode is formed on the first laminated metal film 27 as a shape. At this time, a plating resist 29 is formed on the first laminated metal film 27 in order to obtain a desired wiring and electrode shape, and after the electrolytic plating, the plating resist 29 is removed. The first conductive pattern 28 may be formed by filling the hole 26. Further, as a material of the first conductive pattern 28, copper (Cu), gold (Au), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al), or the like is used. .

Next, as shown in FIG. 4F, the first conductive pattern 28 is
The portion of the first stacked metal film 27 other than the region where the is formed is removed by etching.

Next, as shown in FIG. 5G, a second insulating layer 23 is formed by opening a part of the first conductive pattern 28 as the first external electrode 21. After the second insulating layer 23 is formed on the first conductive pattern 28 and the first insulating layer 20 excluding the first external electrode 21, a mask in which the first external electrode 21 is opened is formed. After etching the second insulating layer 23 in the opening of the first external electrode 21, the mask is removed. The second insulating layer 23 is formed of silicon dioxide (SiO2), silicon nitride (Si) by a CVD method, a sputtering method, an optical CVD method, a coating method, or the like.
N), an oxynitride film (SiON), a film of polyimide or the like is formed.

As described above, only the first external electrode 21 electrically connected to the surface electrode 18 is formed on the surface of the semiconductor substrate as a conductive substance in a state of being exposed from the second insulating layer 23. .

Next, as shown in FIG.
Surface 14 is adhered to a support 31 with an adhesive 30 and is mechanically ground or CMP (Chemical Mechanical).
The semiconductor substrate 13 is ground from the second surface 17 by a cal polishing (cal polishing) method, and 50 to 200 [μm].
Process up to thickness. In the present embodiment, the thickness of the semiconductor substrate after grinding is 100 [μm].

Next, as shown in FIG. 7, on the second surface 17 of the semiconductor substrate 13, the center of two dotted lines sandwiching the boundary of the semiconductor chip unit is cut by bevel cutting.
A slope 15 at an obtuse angle with the second surface 17 of the semiconductor substrate 13 is formed, and the first conductive pattern 28 is
Exposure to Therefore, as shown in FIG. 2B, the hole 26 formed in the semiconductor substrate 13 is
Does not need to be penetrated, and the time required to process the hole 26 can be reduced. The processing depth of the hole 26 shown in FIG. 2B is determined by the cutting depth in bevel cutting and the tip shape of the cutting blade.

Here, the bevel cut means that a semiconductor substrate is formed with a slope having an obtuse angle with respect to the second surface by using a cutting blade having a relatively large thickness and a tip formed by a slope. Cutting method. The thickness of the cutting blade used for bevel cutting is desirably about 100 [μm] or more larger than the distance between adjacent through holes. In this embodiment, the distance between adjacent through holes is 1
00 [μm], and the thickness of the cutting blade used for bevel cutting is 200 [μm]. In the present embodiment, the processing method using bevel cutting has been described, but processing may be performed by etching.

Next, as shown in FIG. 8, a third insulating layer 32 is formed on the entire surface of the slope 15 and the second surface 17 except for the portion exposed on the slope 15 of the first conductive pattern 28.
At this time, the third insulating layer 32 is placed on the slope 15 and the second surface 1.
7, a mask having an opening at a portion where the first conductive pattern 28 is exposed is formed on the third insulating layer 32, and the third insulating layer 32 at the opening of the first conductive pattern 28 is formed. After the etching, the mask is removed. Note that the third insulating layer 32 is formed by a CVD method, a sputtering method,
A film such as silicon dioxide (SiO2), silicon nitride (SiN), oxynitride film (SiON), or polyimide is formed by a method, coating, or the like.

It is desirable that the third insulating layer 32 be formed of a material having a higher etching rate than that of the first insulating layer 20. That is, when opening the third insulating layer 32 by etching, the third insulating film 32 is selectively etched without substantially etching the first insulating layer 20 even if a mask shift occurs. This is because the opening can be formed and the first insulating layer 20 is not partially removed.

Next, as shown in FIG. 9, a second laminated metal film 33 is formed on the entire surface of the slope 15 and the second surface 17. The second laminated metal film 33 has a two-layer structure in which a seed layer is laminated on a barrier layer. The barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. Titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), nickel (Ni), etc. are used for the barrier layer, and copper (Cu), gold (Au),
Silver (Ag), nickel (Ni), or the like is used.

Next, as shown in FIG. 10, a second conductive pattern 34 having a desired wiring and electrode shape is formed on the inclined surface 15 and the second surface by electrolytic plating using the second laminated metal film 33 as an electrode. 17, the second conductive pattern 34 is formed on the slope 15 through the second laminated metal film 33.
Is electrically connected to the first conductive pattern 28 exposed from the substrate. At this time, in order to form a desired wiring and electrode shape, the plating resist 3 is formed on a portion of the second laminated metal film 33 where the second conductive pattern 34 does not need to be formed.
5 is formed, and after electrolytic plating, a plating resist 35 is formed.
Is removed. The material of the second conductive pattern 34 is copper (Cu), gold (Au), tungsten (W),
Molybdenum (Mo), nickel (Ni), titanium (T
i), aluminum (Al) or the like is used.

Next, as shown in FIG. 11, using the second conductive pattern as a mask, the second laminated metal film 33 other than the region where the second conductive pattern is formed is removed by etching.

Next, as shown in FIG. 12, the entire second surface 17 excluding the opening of the second external electrode 22 and the slope 15
Next, a fourth insulating layer 36 is formed. At this time, after the fourth insulating layer 36 is formed on the entire slope 15 and the second surface 17, a mask having an opening in the second external electrode 22 is formed, and the opening of the second external electrode 22 is formed. Fourth insulating layer 36
After etching, the mask is removed. The fourth insulating layer 36 is made of a film such as silicon dioxide (SiO2), silicon nitride (SiN), oxynitride film (SiON), polyimide, etc. Is formed.

Next, as shown in FIG. 13, dicing is performed on a scribe line 37 which is a boundary line of a semiconductor chip unit to form a side surface 38 in which an inner angle with the first surface 14 is a right angle. Thereafter, the adhesive 30 and the support 31 are removed, and the semiconductor chip 39 is divided into individual pieces.

Through the series of semiconductor chip manufacturing steps, a first external electrode is formed on the first surface of the semiconductor chip in a state where the first external electrode is exposed from the second insulating layer.
Further, a second external electrode is formed on the second surface in a state exposed from the fourth insulating layer, and the surface electrode, the first external electrode, and the second external electrode are electrically connected to each other. You.

The positions at which the first external electrode and the second external electrode are formed are not particularly limited. When a plurality of semiconductor chips are stacked, the positions at which the external electrodes of the adjacent semiconductor chips correspond to each other. Should be there.

FIGS. 14 to 16 are cross-sectional views showing a step of supplying and curing the resin on the slope after the step shown in FIGS. The steps shown in FIGS. 14 to 16 are intended to reinforce the slope.

As shown in FIG. 14, FIG.
After the step shown in (2), the liquid resin is applied to the bevel-cut portion until the upper surface thereof reaches the height of the second surface, so that the second surface excluding the portion that opens as the second external electrode 22 is formed. An insulating resin layer 40 is formed on the entire surface and the slope 15.

The liquid resin is preferably a resin such as polyimide which can relieve stress.

Next, as shown in FIG. 15, dicing is performed on the scribe line 37 from the second surface side.
To form a side surface perpendicular to the surface.

Next, as shown in FIG. 16, the adhesive 30 and the support 31 are removed, and the semiconductor chip 39 is divided into individual pieces.

The shape of the through hole or hole may be circular or square, and in the case of a circular shape, the diameter is 10 to 20 [μm].
In the case of a square, the length of one side is 10 to 20 [μm], and in this embodiment, it is 20 [μm]. Here, when the shape of the hole is a quadrangle, the corner of the quadrangle is not a right angle but a rounded shape. Also, due to the technological innovation of the RIE method, the diameter or the length of one side is 10 [μm].
It is also possible to machine smaller through holes or holes.

In addition, the first insulating layer, the second insulating layer, the third
The thickness of the insulating layer and the fourth insulating layer is 1 to 30 [μm].
In this embodiment, silicon dioxide (SiO2),
The thickness is 1 [μm] for silicon nitride (SiN) and oxynitride film (SiON), and 7 [μm] for polyimide. The second insulating layer and the fourth insulating layer may be mainly made of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment.

In addition, the first conductive pattern 28 and the second
Is preferably 5 to 15 [μ].
m] and 10 [μm] in the present embodiment.

In this embodiment, after applying the liquid resin on the slope, dicing is performed on the cured liquid resin portion, thereby preventing problems such as chipping at the time of cutting.
Since the corners of the semiconductor substrate formed of an insulating resin layer having a relatively large thickness and perpendicular to the second surface can be formed, and the individual semiconductor chips can be formed into individual pieces, the side surfaces of the semiconductor chips are reinforced, The second conductive pattern on the slope can be protected.

As described above, in this embodiment, in addition to the steps of forming various insulating layers, a step of forming a hole halfway from the first surface of the semiconductor substrate and a step of forming a slope from the second surface are performed. By providing the step of penetrating the hole and the step of forming a conductive pattern via the hole and the inclined surface, a structure in which electrodes formed on both surfaces of the semiconductor substrate are electrically connected to each other can be realized.

Further, after the first conductive pattern is formed in the hole formed in the semiconductor substrate, the first conductive pattern is formed by forming an inclined surface which reaches the hole and forms an obtuse angle with the second surface. Is exposed on the second surface, so that it is not necessary to form a hole deeply or to polish the semiconductor substrate thinly, so that the processing time can be reduced and the processing cost can be reduced.
In addition, since the degree of freedom of the thickness of the semiconductor chip is increased and the thickness of the semiconductor substrate is relatively large, the transfer of the semiconductor substrate is facilitated. Further, by forming a slope having an obtuse interior angle with the second surface by bevel cutting, the first surface is formed.
Since the conductive pattern is exposed on the second surface, the number of manufacturing steps and manufacturing cost can be significantly reduced as compared with the processing method in which holes are first penetrated.

In order to reduce the number of manufacturing steps, the formation of the first external electrode and the formation of the first conductive pattern, or the formation of the second external electrode and the formation of the second conductive pattern are simultaneously performed. May go.

By forming a laminated metal film comprising a barrier layer and a seed layer below the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern can be formed by the barrier layer. The constituent elements can be suppressed from diffusing into the first external electrode and the semiconductor substrate, and the characteristics of the semiconductor chip can be prevented from deteriorating. The first conductive pattern and the second conductive pattern are formed by electrolytic plating on the seed layer. can do.

As described above, according to the method of manufacturing a semiconductor chip of the present embodiment, a surface electrode is formed on the first surface of a semiconductor substrate, and a conductive pattern is formed via an inner wall of a through hole formed in the semiconductor substrate. The first external electrode formed on the first surface, the second external electrode formed on the second surface, and the surface electrode are electrically connected by a conductive pattern, and the internal angle formed by the second surface. A semiconductor chip having a through hole formed on a slope having an obtuse angle can be manufactured.

In the semiconductor chip manufactured by the method of manufacturing a semiconductor chip according to the present embodiment, the electrodes on both sides are electrically connected by a conductive pattern passing through the side surface of the semiconductor substrate. And the semiconductor chips can be electrically connected to each other, and by forming the slope, the wiring length can be shortened and the resin can be supplied on the slope to prevent external impact on the conductive pattern. Can be achieved, and the semiconductor device in which the semiconductor chips are stacked can be made thinner, smaller and faster.

Next, a second embodiment of the present invention will be described.

FIG. 17 is a sectional view showing a semiconductor chip of this embodiment.

Here, the same components as those in the first embodiment are denoted by the same reference numerals, and the description of the common contents is omitted.

As shown in FIG. 17, the semiconductor chip of this embodiment is different from the semiconductor chip of the first embodiment in that
These are the thickness of the first external electrode and the thickness of the second external electrode.

That is, the semiconductor chip of this embodiment is
The surface of the first external electrode and the surface of the second external electrode
It protrudes from the surface of the second insulating layer formed on the surface of the semiconductor substrate. Specifically, the surface of the first external electrode and the surface of the second external electrode protrude from the surface of the second insulating layer by securing the height of the electrode itself by plating or the like.

Therefore, when a plurality of semiconductor chips of the present embodiment are stacked, electrical connection between the semiconductor chips can be ensured without using a connecting member.

Next, a method for manufacturing the semiconductor chip of the present embodiment will be described.

The method for manufacturing a semiconductor chip of this embodiment is as follows.
After the completion of the semiconductor chip of the first embodiment, a step of forming each external electrode is added. That is, FIGS. 10 to 12 or FIGS. 14 to 15 shown in the first embodiment.
After the step shown in (1), a step for securing the height of the external electrode is added.

That is, as shown in FIG. 17, by securing the height of the electrode itself by plating or the like,
The surface of the first external electrode 21 and the surface of the second external electrode 22 project from the surface of the second insulating layer 23. Accordingly, when a plurality of semiconductor chips are stacked facing each other, electrical connection between the semiconductor chips can be secured without using a connection member, so that a reduction in thickness and speed can be achieved. Becomes

Next, a third embodiment of the present invention will be described.

FIG. 18 is a sectional view of a semiconductor chip of this embodiment.

Here, the same components as those of the first embodiment and the second embodiment are denoted by the same reference numerals, and the description of the common contents will be omitted.

As shown in FIG. 18, at least one electrode not electrically connected to the surface electrode formed on the surface of the semiconductor substrate is provided.
Since the conductive pattern 19 has one conductive pattern 19, the conductive pattern 19 is not connected to the integrated circuit of the semiconductor chip H, and the first external electrode 21 and the second external electrode 21 formed on the first surface 14 of the semiconductor chip H are not connected. Is electrically connected to the second external electrode 22 formed on the surface 17.

Therefore, the semiconductor chip of this embodiment has a structure having a conductive pattern in which the external electrodes formed on both sides are electrically connected but are not electrically connected to the integrated circuit.

Next, a method for manufacturing the semiconductor chip of this embodiment will be described.

The method for manufacturing a semiconductor chip of this embodiment is as follows.
Compared with the semiconductor chip manufacturing method of the first embodiment, a feature is that a conductive pattern is not formed on at least one arbitrary surface electrode among the surface electrodes formed on the semiconductor substrate. That is, in the method for manufacturing a semiconductor chip according to the first embodiment, the conductive pattern for electrically connecting the external electrodes on both surfaces of the semiconductor chip is electrically connected to the surface electrode. By forming a conductive pattern for electrically connecting the external electrodes on both surfaces of the semiconductor chip to a portion where no is present, a conductive pattern that is not electrically connected to the integrated circuit of the semiconductor chip is formed. Therefore, by stacking semiconductor chips that do not need to be electrically connected to the integrated circuit between two semiconductor chips that need to be electrically connected,
It is possible to realize a semiconductor device that passes an integrated circuit of a semiconductor chip sandwiched therebetween, and the degree of freedom of electrical connection between the semiconductor chips is improved.

As described above, the three embodiments of the semiconductor chip are as follows.
Each has a structure in which electrodes are formed on both sides of a semiconductor substrate, but differs in that the structure of the electrodes and the electrodes to be electrically connected are selective.

That is, the surface electrodes formed on the surface of the semiconductor substrate and the external electrodes on both surfaces are electrically connected by a conductive pattern, and the height of the surface of the external electrodes is ensured by plating or the like. A configuration in which the external electrodes are electrically connected to each other by a conductive pattern that is not electrically connected to the surface electrode of the semiconductor substrate, and a configuration in which a conductive pattern that is not connected to at least one external electrode is formed. Yes, when a plurality of such semiconductor chips are stacked, external electrodes on the surface of the opposed semiconductor chip can be electrically connected to each other,
It is possible to select whether or not any semiconductor chip is electrically connected to the integrated circuit.

Next, the semiconductor device of the present invention will be described.

Each embodiment of the semiconductor device described below is composed of each embodiment of the semiconductor chip described above, and will be described as fourth to sixth embodiments.

A fourth embodiment of the present invention will be described.

FIG. 19 is a sectional view showing the semiconductor device of this embodiment.

As shown in FIG. 19, the semiconductor chip A, the semiconductor chip B and the semiconductor chip C shown as the first embodiment of the semiconductor chip are stacked. Each semiconductor chip has external electrodes formed on both sides,
They are electrically connected via connection members.

That is, the surface electrode 18 of the semiconductor chip C
Is electrically connected to the second external electrode 22 of the semiconductor chip B via the connection member 24, and the surface electrode 18 of the semiconductor chip B is electrically connected to the second external electrode 22 of the semiconductor chip A via the connection member 24. Since they are electrically connected, the semiconductor chips A, B and C are electrically connected to each other.

With this configuration, in the present embodiment, the semiconductor chips A, B and C are formed by connecting the electrodes formed on both surfaces thereof to the conductive patterns passing through the through holes of the respective semiconductor substrates. When the semiconductor chips are electrically connected and the semiconductor chips are stacked, the surfaces of the semiconductor chips are opposed to each other. Therefore, unlike a conventional semiconductor device in which a plurality of semiconductor chips are arranged in a plane, the semiconductor chips to be stacked are stacked. The problem that the mounting area of the semiconductor device increases as the number of chips increases is solved.

Further, since the electrodes arranged on both sides of each semiconductor chip are electrically connected to each other, the electrical connection of the stacked semiconductor chips is different from the conventional form in which the stacked semiconductor chips are connected by metal wires. It is not necessary to expose the lower electrode of the semiconductor chip to the upper semiconductor chip away from the substrate, and to stack not only semiconductor chips of the same size but also semiconductor chips of different sizes in a desired order. Therefore, there is no problem that the wiring length between the semiconductor chips becomes long.

Furthermore, a conventional COC (Chip On Ch) for connecting the surfaces of the respective semiconductor chips so as to face each other.
In the ip) structure, the element formation surface on which the electrodes are formed is only one surface of the semiconductor chip, so the number of stacked semiconductor chips is limited to two. In the present embodiment, however, both surfaces of the semiconductor chip are provided. Because the electrode can be formed,
The electrodes on both sides of each semiconductor chip can be electrically connected, and the number of stacked semiconductor chips can be increased.

In this embodiment, since the electrodes of the respective semiconductor chips are laminated in correspondence with each other, a plurality of semiconductor chips are stacked without increasing the thickness of the entire semiconductor device unlike the conventional semiconductor device laminated using a wiring board. The thickness of the semiconductor device in which the semiconductor chips are stacked can be reduced, and the mounting area is equivalent to the size of the semiconductor chip to be stacked.

As described above, the semiconductor device of the present embodiment in which a plurality of semiconductor chips are stacked makes it possible to stack a plurality of semiconductor chips. Since the thickness of the stacked layers is reduced without increasing the wiring length of the semiconductor device, it is possible to realize a semiconductor device that is compatible with miniaturization, high density, and high speed without increasing the mounting area.

In this embodiment, the case where the number of stacked semiconductor chips is three has been described, but it is also possible to stack two or four or more semiconductor chips.

Next, a fifth embodiment of the present invention will be described.

FIG. 20 is a sectional view showing a semiconductor device in which electrodes of respective semiconductor chips are directly joined without using a connecting member and semiconductor chips are stacked.

The portions corresponding to those of the semiconductor device of FIG. 1 are denoted by the same reference numerals as in FIG. 1, and the description of the contents common to FIG. 19 will be omitted.

As shown in FIG. 20, the configuration of the electrodes, insulating layers and conductive patterns in each semiconductor chip is the same, except that the method of electrically connecting the semiconductor chips is different from that of the fourth embodiment.

That is, the first external electrode 21 of the semiconductor chip F is directly joined to the second external electrode 22 of the semiconductor chip E, and the first external electrode 21 of the semiconductor chip E is connected to the second external electrode of the semiconductor chip D. Since it is directly joined to the electrode 22,
Semiconductor chip D, semiconductor chip E and semiconductor chip F
Are electrically connected to each other.

Here, since the first external electrode 21 and the second external electrode 22 of each semiconductor chip need to protrude beyond the second insulating layer 23, for example, the electrodes themselves are plated by plating or the like. It is desirable to secure the height.

As described above, according to the present embodiment, the external electrodes of the semiconductor substrate are directly connected to each other without using a connecting member, so that the semiconductor device after laminating the semiconductor chips is different from the case of the fourth embodiment. In addition to reducing the thickness of the semiconductor device, the wiring length can also be reduced, and a semiconductor device in which semiconductor chips are stacked is small in thickness, and a semiconductor device compatible with miniaturization and high speed can be realized.

Next, a sixth embodiment will be described.

FIG. 21 is a sectional view showing the semiconductor device of this embodiment.

The parts corresponding to those in FIG. 19 are denoted by the same reference numerals as in FIG. 1, and the description of the common contents will be omitted.

As shown in FIG. 21, the semiconductor chip H is
The configuration is different from the semiconductor chip G and the semiconductor I, and the first electrode or the third electrode connected to the conductive pattern is not formed, showing a characteristic configuration of the semiconductor chip of the present embodiment.

That is, in the semiconductor chips G and I, the surface electrode 18 formed on the first surface, the first external electrode 21, and the second external electrode 22 formed on the second surface are formed by the conductive pattern 19. The first external electrode 21 of the semiconductor chip I, which is electrically connected and electrically connected to the second external electrode 22 of the semiconductor chip H, and the first external electrode 21 of the semiconductor chip H. Although it is electrically connected to the second external electrode 22 of the connected semiconductor chip G, it is not connected to the integrated circuit of the semiconductor chip H, so that the integrated circuit of the semiconductor chip H can be passed. Thus, by stacking a semiconductor chip that does not need to be electrically connected to the integrated circuit between two semiconductor chips that need to be electrically connected, the electrical connection between the semiconductor chips can be improved. The degree of freedom is improved.

Although the three embodiments of the semiconductor device have been described above, in any of the embodiments, the semiconductor device is formed by stacking semiconductor chips, and the semiconductor device is interposed between the surface electrodes formed on the semiconductor substrate and the conductive patterns. A semiconductor device in which a plurality of semiconductor chips having external electrodes electrically connected to each other are stacked, wherein the external connection electrodes are electrically connected via a connection member, and the external electrodes of the semiconductor chip are connected to each other. There is a form in which at least one semiconductor chip in which external electrodes on both sides are electrically connected by a conductive pattern which is not directly connected to the front surface electrode of the semiconductor substrate is used.

In the fourth to sixth embodiments, the laminated metal film is used as a base for the conductive pattern, and between the conductive pattern and the first resin layer and between the conductive pattern and the surface electrode. May be formed. The laminated metal film is composed of a barrier layer and a seed layer. The barrier layer can prevent the diffusion of the constituent elements of the conductive pattern and prevent the deterioration of the characteristics of the semiconductor chip. The conductive pattern can be plated. The thickness of each of the barrier layer and the seed layer constituting the laminated metal film is 0.05 to 0.35 [
μm] and the thickness of the seed layer is 0.2 to 0.8 μm. In the present embodiment, the thickness of the barrier layer is 0.2 μm and the thickness of the seed layer is 0.5 μm.

As described above, the semiconductor device in which the semiconductor chips having the external electrodes formed on both surfaces thereof are laminated can be used without increasing the mounting area of the semiconductor chip and without the need for a wiring board and metal wires. And speeding up.

As described above, according to the semiconductor chip of the present invention, the electrodes formed on both sides of the semiconductor chip are electrically connected via the conductive pattern, so that a plurality of semiconductor chips can be stacked without using metal wires. Further, by forming a slope having an obtuse interior angle with the second surface, the wiring length can be reduced and the side surface of the semiconductor chip can be protected by resin supply.

Further, in the semiconductor device in which the semiconductor chips of the present invention are stacked, a plurality of semiconductor chips are electrically connected on the surface facing each other, so that the wiring length can be reduced, and the thickness and mounting area of the semiconductor device can be prevented from increasing. Is possible.

Further, in the method of manufacturing a semiconductor chip, the hole formed in the semiconductor substrate is made to penetrate by forming a slope having an obtuse angle with the second surface of the semiconductor substrate, so that the hole is formed before the slope is formed. Processing time can be reduced. In addition, in the division of the semiconductor chip unit, by cutting the resin portion supplied on the slope, problems such as chipping at the time of cutting can be prevented.

Hereinafter, a seventh embodiment of the wiring board and the method of manufacturing the same of the present invention will be described.

First, the wiring board of this embodiment will be described. FIG. 22 is a cross-sectional view of the wiring board of the present embodiment.

As shown in FIG. 22, the thickness is 50 to 200.
A through hole 109 is formed from the surface 107 to the slope 108 of the silicon substrate 106 having a silicon base of [μm].
The slope 108 formed so that the inner angle with the back surface 110 is an obtuse angle forms a part of the outer shape of the wiring board 111.
In the present embodiment, the through hole 109 is located near the boundary of the wiring substrate 111 in units of individual pieces, for example, 50 to 150 from the boundary.
It is formed at the position of [μm]. The shape of the through hole 109 may be circular or square, and in the case of a circular shape, the diameter is 10 to 2
0 [μm]. In the case of a square, the length of one side is 10
In the case of ２０20 [μm], the corners of the square are not right angles but rounded. In the present embodiment, the inner angle between the slope 108 and the rear surface 110 is 135 degrees, and the slope 108 is formed from the rear surface to a position of 10 to 50 [μm].
In the present embodiment, the substrate thickness is 100 [μm], and the slope 108 is formed from the rear surface 110 to a position 20 [μm].
Then, the front surface 107 and the back surface 1 of the silicon substrate 106
In 10, a first conductive pattern 112 and a second conductive pattern 113 are formed, respectively. Further, a third conductive pattern 114 is formed on the inner wall and the slope of the through-hole, and the first conductive pattern 112 and the second conductive pattern 113 are electrically connected by the third conductive pattern 114. In this way, by forming a slope having an obtuse interior angle with the back surface of the silicon substrate, the distance of the conductive pattern that electrically connects the electrodes on both surfaces of the silicon substrate is shortened, and a wiring pattern corresponding to high speed is formed. Can be secured. Note that the third conductive pattern 114 may be formed along the inner wall of the through hole or may be filled in the through hole. Materials for these conductive patterns include copper (Cu), gold (Au), tungsten (W), molybdenum (Mo),
Nickel (Ni), titanium (Ti), aluminum (Al), or the like is used. The thickness of each conductive pattern is preferably 5 to 15 [μm],
In this embodiment, the thickness is 10 [μm],
The thickness is the same as each conductive pattern.

As a base for this conductive pattern, a laminated metal film may be formed between each conductive pattern and the first insulating layer 115. The laminated metal film is formed by laminating a seed layer on the upper surface of the barrier layer. The conductive layer has a layer structure, and the barrier layer can prevent the diffusion of the constituent elements of each conductive pattern and the deterioration of the characteristics of the wiring substrate. By providing the seed layer, the conductive pattern can be plated by the electrolytic plating method. The barrier layer is made of titanium (Ti), titanium tungsten (Ti /
W), chromium (Cr), nickel (Ni), or the like is used as the material, and the thickness is 0.05 to 0.35 [μm], and is 0.2 [μm] in the present embodiment. The seed layer is made of copper (Cu), gold (Au), silver (Ag), nickel (Ni), or the like, and has a thickness of 0.2.
0.8 [μm], and in this embodiment, 0.5 [μm].

Further, a first insulating layer 115 is formed between the silicon substrate 106 and the first conductive pattern 112, the second conductive pattern 113, and the third conductive pattern 114. The pattern is electrically insulated. Further, the first conductive pattern 11
The second insulating layer 118 covers the surface other than the second electrode portion 116 and the rear surface other than the electrode portion 117 of the second conductive pattern 113.
Each electrode part is a part of each conductive pattern, and each electrode part corresponding to each conductive pattern is formed at the same time. Each insulating layer has a thickness of 1 to 30.
[μm] silicon dioxide (SiO 2), silicon nitride (Si
N), an oxynitride film (SiON), a polyimide film, etc. are used, and silicon dioxide (SiO2), silicon nitride (Si
N), 1 [μm] for an oxynitride film (SiON) and 7 [μm] for a polyimide film. Also, the second insulating layer 1
Reference numeral 18 may be made mainly of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment.

In this embodiment, each conductive pattern is formed in one layer. However, two or more conductive patterns may be formed alternately with the insulating layer, and the number of layers of each conductive pattern is limited. is not.

As described above, through holes are formed in a silicon substrate having silicon as a base material, and electrodes formed on both surfaces of the silicon substrate are electrically connected through conductive patterns formed on both surfaces of the silicon substrate and the through holes. With the wiring substrate thus formed, it is possible to achieve the same high-precision pattern formation and flatness as a semiconductor chip mounted on the wiring substrate, so that it is possible to realize improvement in bonding reliability.

Next, a method of manufacturing the wiring board of the present embodiment will be described.

Note that the same components as those in FIG. 22 are denoted by the same reference numerals.

FIGS. 23 to 38 are sectional views or plan views of each step of the method for manufacturing a wiring board according to the present embodiment.

First, as shown in FIG.
A silicon substrate 106 in a wafer state having a thickness of 00 [μm]
Prepare Note that the broken lines shown in the figure indicate the positions through which both ends in the width direction of the cutting blade pass during dicing for dividing the silicon substrate into divided wiring boards.
The central part of the broken line of the book is the boundary between the individual pieces of the wiring board.

FIG. 24 is a plan view showing a state in which holes have been machined from the surface of the silicon substrate, and FIG.
FIG. 5 is a sectional view taken along the line VV ′.

As shown in FIGS. 24 and 25 (a),
A hole 119 having a depth of 20 to 100 [μm] is formed by a reactive ion etching (RIE) method without penetrating the surface 107 of the silicon substrate 106 in the thickness direction. It is formed around the individual unit of the wiring board, and in this embodiment, 50 [μm] from the boundary line of the individual unit of the divided wiring board in the present embodiment.
Is formed at the position.

In this embodiment, the thickness of the silicon substrate 106 is 100 [μm] and the depth of the hole 119 is 70 [μm]. Is about 50 μm. Note that the method for forming the holes 119 is not limited to the RIE method, and light etching, wet etching, ultrasonic machining, electric discharge machining, and the like can be used, and the above-described various machining methods may be combined. .

As described above, the RIE method, which is a method of processing a hole formed in a silicon substrate, is a dry etching method using a reactive gas plasma, and is a method used for fine processing of a semiconductor wafer. A mask covering portions other than the holes is formed on the insulating layer so that the portion is not etched, and the mask is removed after etching.

Next, as shown in FIG.
The first insulating layer 120 is formed on the inner wall of the substrate and on the surface 107 of the silicon substrate. Here, the first insulating layer 120
Silicon dioxide (SiO2), silicon nitride (Si) by CVD, sputtering, photo-CVD, coating, etc.
N), an oxynitride film (SiON), a film made of polyimide or the like is formed.

Next, as shown in FIG. 26C, a first laminated metal film 121 is formed on the first insulating layer 120.
The first laminated metal film 121 has a two-layer structure in which a seed layer is laminated on a barrier layer. Here, the barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer is made of titanium (T
i), titanium tungsten (Ti / W), chromium (C
r), nickel (Ni),
For the seed layer, copper (Cu), gold (Au), silver (Ag), nickel (Ni), or the like is used.

Next, as shown in FIG. 26D, the first conductive pattern 112 is formed on the inner wall of the hole 119 and the first laminated metal film 121 by electrolytic plating using the first laminated metal film 121 as an electrode. Form on top. At this time, a plating resist 122 is formed on the first laminated metal film 121 in order to obtain a desired wiring and electrode shape, and after the electrolytic plating, the plating resist 122 is removed. Note that the first conductive pattern 112 may be formed by filling the hole 119. Further, as a material of the first conductive pattern 112, copper (Cu), gold (Au), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al), or the like is used. .

Next, as shown in FIG. 27E, using the first conductive pattern 112 as a mask, the first laminated metal film 121 in a portion other than the region where the first conductive pattern 112 is formed is etched. Remove.

Next, as shown in FIG. 27 (f), a part of the first conductive pattern 112 is opened as a first external electrode 123 to form a second insulating layer 124. After the second insulating layer 124 is formed on the first conductive pattern 112 and the first insulating layer 120 except for the first external electrode 123, a mask in which the first external electrode 123 is opened is formed. After etching the second insulating layer 124 at the opening of the first external electrode 123, the mask is removed. Note that the second insulating layer 124 is formed by a CVD method, a sputtering method,
Silicon dioxide (SiO 2) by VD method, coating method, etc.
2), silicon nitride (SiN), oxynitride film (SiON),
A film such as polyimide is formed.

Next, as shown in FIG.
06 is adhered to a support 126 with an adhesive 125, and is subjected to mechanical grinding or CMP (Chemical M).
The silicon substrate 106 is ground from the rear surface 110 by the mechanical polishing method,
Work to a thickness of ~ 200 [μm]. In the present embodiment, the thickness of the silicon substrate after grinding is 100 [μm].

Next, as shown in FIG.
06, the central portion of two dotted lines sandwiching the boundary of each unit of the divided wiring board is cut by bevel cutting to form an inclined surface 108 at an obtuse angle with the back surface 110 of the silicon substrate 106. Then, the first conductive pattern 114 is exposed on the slope 108. Therefore, as shown in FIG. 25A, the hole 119 formed in the silicon substrate 106 does not need to penetrate the silicon substrate 106, and the time required for processing the hole 119 can be reduced. The processing depth of the hole 119 shown in FIG. 25A is determined by the cutting depth in bevel cutting and the tip shape of the cutting blade.

[0212] Here, the bevel cutting is to form a slope in which the inner angle with the back surface is obtuse on the silicon substrate by using a cutting blade having a relatively large blade thickness and a tip formed by a slope. It is such a cutting method.
Note that the thickness of the cutting blade used for bevel cutting is desirably greater than the distance between adjacent through holes by about 100 [μm] or more. In this embodiment, the distance between adjacent through holes is 1
00 [μm], and the thickness of the cutting blade used for bevel cutting is 200 [μm]. In the present embodiment, the processing method using bevel cutting has been described, but processing may be performed by etching.

Next, as shown in FIG. 30, the slope 10 of the first conductive pattern 114 excluding the portion exposed to the slope 108 is removed.
8 and the back surface 110, the third insulating layer 127 is formed. At this time, after the third insulating layer 127 is formed on the slope 108 and the back surface 110, the first conductive pattern 114 is exposed. A mask having an opening in a portion is formed over the third insulating layer 127, and after the third insulating layer 127 in the opening of the first conductive pattern 114 is etched, the mask is removed. Note that the third insulating layer 127 is formed by a CVD method,
Silicon dioxide (SiO2), silicon nitride (SiN), oxynitride film (S
(iON), polyimide or the like.

[0214] It is preferable that the third insulating layer 127 be formed using a material whose etching rate is higher than that of the first insulating layer 120. In other words, when opening the third insulating layer 127 by etching, even if a mask shift occurs, the third insulating layer 120 is hardly etched and the third insulating layer 120 is etched.
This is because the insulating layer 127 can be selectively etched to form an opening, and the first insulating layer 120 is not partially removed.

Next, as shown in FIG. 31, a second laminated metal film 128 is formed on the entire surface of the inclined surface 108 and the rear surface 110. The second laminated metal film 128 has a two-layer structure in which a seed layer is laminated on a barrier layer. The barrier layer and the seed layer are formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. Titanium (Ti), titanium tungsten (Ti / W), chromium (Cr), nickel (N
i) and the like, and copper (Cu) and gold (A
u), silver (Ag), nickel (Ni) and the like.

Next, as shown in FIG. 32, a second conductive pattern 129 having a desired wiring and electrode shape is formed on the slope 1 by electrolytic plating using the second laminated metal film 128 as an electrode.
08 and the back surface 110, the second conductive pattern 129 is electrically connected to the first conductive pattern 114 exposed from the slope 108 via the second laminated metal film 128. At that time, in order to form desired wiring and electrode shapes, a portion where the second conductive pattern 129 does not need to be formed is formed on the second laminated metal film 128.
A plating resist 130 is formed, and after electrolytic plating,
The plating resist 130 is removed. The material of the second conductive pattern 129 is copper (Cu), gold (A
u), tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), aluminum (Al)
Are used.

Next, as shown in FIG. 33, using the second conductive pattern 129 as a mask, the second laminated metal film 128 other than the region where the second conductive pattern 129 is formed is removed by etching.

Next, as shown in FIG. 34, the entire back surface 110 excluding the opening of the second external electrode 131 and the slope 1
At 08, a fourth insulating layer 132 is formed. At that time, the fourth
Is formed on the entire surface of the inclined surface 108 and the rear surface 110, and a mask having an opening in the second external electrode 131 is formed.
After etching the insulating layer 132, the mask is removed. Note that the fourth insulating layer 132 is formed of silicon dioxide (SiO2), silicon nitride (SiN), or an oxynitride film (Si
ON), a film of polyimide or the like is formed.

Next, as shown in FIG. 35, dicing is performed on the inside of both ends in the width direction of the cutting blade shown by the broken line in FIG. 34 around the scribe line 133 which is the boundary line of the division unit of the wiring board. The side surface 134 is formed such that the inner angle with the back surface 110 is a right angle.

Through such a series of manufacturing steps of the wiring board, the first external electrode is formed on the surface of the wiring board in a state of being exposed from the second insulating layer, and the second external electrode is formed on the back surface. Are formed so as to be exposed from the fourth insulating layer, and the first external electrode and the second external electrode are electrically connected to each other.

The formation positions of the first external electrode and the second external electrode are not particularly limited, and the external electrode is formed at a position corresponding to the electrode of the semiconductor chip to be mounted and the electrode at the joint with the motherboard. May be formed respectively.

FIGS. 36 to 38 are cross-sectional views showing a step of supplying and curing the resin on the slope after the steps shown in FIGS. 23 to 33. The steps shown in FIGS. 36 to 38 are intended to reinforce slopes.

As shown in FIG. 36, FIG.
After applying the liquid resin to the bevel-cut portion until the upper surface thereof reaches the height of the rear surface, the entire surface of the rear surface 110 and the slope 108 except for the portion that opens as the second external electrode 131 after the process shown in FIG. Then, an insulating resin layer 135 is formed.

The liquid resin is preferably a resin such as polyimide which can relieve stress.

Next, as shown in FIG. 37, dicing is performed on the scribe line 133 from the back side to form a side surface perpendicular to the back side.

Next, as shown in FIG. 38, the adhesive 125 and the support 126 are removed, and the wiring board 106 is divided into individual pieces.

The shape of the through hole or the hole may be circular or square. In the case of a circular shape, the diameter is 10 to 20 [μm].
In the case of a square, the length of one side is 10 to 20 [μm],
In the present embodiment, it is 20 [μm]. Here, if the shape of the hole is a square, the corners of the square are not right angles,
It has a rounded shape. In addition, it is also possible to process through holes or holes whose diameter or length of one side is smaller than 10 [μm] by technical innovation of the RIE method.

In addition, the first insulating layer, the second insulating layer, the third
The thickness of the insulating layer and the fourth insulating layer is 1 to 30 [μm], and in the present embodiment, 1 [in the case of silicon dioxide (SiO ₂ ), silicon nitride (SiN), and oxynitride film (SiON). μm] and 7 [μm] for polyimide. Further, the second insulating layer and the fourth insulating layer may be mainly made of a solder resist, and the thickness in this case is 30 [μm] in the present embodiment.

In addition, the first conductive pattern 12 and the second conductive pattern
The thickness of the conductive pattern 13 is preferably 5 to 15 [μm].
In the present embodiment, it is 10 [μm].

In this embodiment, after applying the liquid resin on the slope, dicing is performed on the cured liquid resin portion, thereby preventing problems such as chipping at the time of cutting.
Since the corners of the silicon substrate formed of a relatively thick insulating resin layer perpendicular to the back surface are formed and the wiring substrate can be divided into individual pieces, the side surfaces of the wiring substrate are reinforced and The second conductive pattern can be protected.

As described above, in this embodiment, in addition to the steps of forming various insulating layers, a step of forming a hole halfway through the first surface of the silicon substrate and a step of forming a slope from the back surface and forming a hole through the hole are performed. By providing the step of forming the conductive pattern and the step of forming the conductive pattern via the hole and the inclined surface, a structure in which the electrodes formed on both surfaces of the silicon substrate are electrically connected to each other can be realized.

Further, after forming the first conductive pattern in the hole formed in the silicon substrate, the first conductive pattern is formed on the back surface by forming a slope that reaches the hole and has an obtuse internal angle with the back surface. Because it is exposed, a hole is formed deeply,
Since it is not necessary to polish the silicon substrate thinly, the processing time can be reduced and the processing cost can be reduced. Further, since the degree of freedom of the thickness of the wiring substrate is increased, the transfer of the silicon substrate is facilitated. In addition, since the first conductive pattern is exposed on the back surface by forming a slope having an obtuse interior angle with the back surface by bevel cutting, the number of manufacturing steps and manufacturing cost are reduced as compared with a processing method in which holes are first penetrated. Can be significantly reduced.

By forming a laminated metal film comprising a barrier layer and a seed layer below the first conductive pattern and the second conductive pattern, the first conductive pattern and the second conductive pattern can be formed by the barrier layer. The constituent elements can be prevented from diffusing into the first electrode and the silicon substrate, and the characteristics of the semiconductor chip can be prevented from deteriorating. The first conductive pattern and the second conductive pattern are formed by electroplating the seed layer. be able to.

As described above, according to the method of manufacturing a wiring board of the present embodiment, the conductive pattern is formed via the inner wall of the through hole formed in the silicon substrate, and the first pattern formed on the first surface is formed.
And a second external electrode formed on the back surface are electrically connected by a conductive pattern, and a wiring board having a through hole formed on a slope having an obtuse interior angle with the back surface is manufactured. it can.

In the wiring board manufactured by the method of manufacturing a wiring board according to the present embodiment, the electrodes on both surfaces are electrically connected by conductive patterns passing through the side surfaces of the silicon substrate. The chip and the wiring board can be joined.

Further, by forming a slope on the wiring board, it is possible to secure a reduction in the wiring length, and by supplying resin on the slope, it is possible to prevent external impact on the conductive pattern.

Next, an eighth embodiment of the present invention will be described.

The contents common to the seventh embodiment are omitted, and the same components are denoted by the same reference numerals.

FIG. 39 is a sectional view of the wiring board of this embodiment.

As shown in FIG. 39, a wiring board according to the present embodiment has a hole 10 in a silicon substrate 106 made of silicon.
9, a first insulating layer 115, a second insulating layer 118, a first conductive pattern 112, a second conductive pattern 113, and a third conductive pattern 114 are respectively formed, and the first conductive pattern 112 and the second Is electrically connected to the conductive pattern 113 by the third conductive pattern 114. Unlike the seventh embodiment, the wiring board of the present embodiment has a low-stress resin layer 136 between the silicon substrate 106 and the second conductive pattern 113. As a material for the low stress resin layer, an epoxy resin, a phenol resin, a polyimide resin, a silicon resin, an acrylic resin, and a bismalimide resin are suitable. In the present embodiment, an epoxy resin is used. In this embodiment, the low stress resin layer is provided between the silicon substrate and the second conductive pattern, but may be provided between the silicon substrate and the first conductive pattern. In addition, the thickness of the low stress resin layer is 5-1.
00 [μm] is preferable and 20 [μm] in the present embodiment. However, it is preferable that the thickness be as thin as possible in order to reduce the thickness of the wiring board. The thickness of the low-stress resin layer is adjusted according to the characteristics of the members such as the size of the board, the temperature at the time of mounting, the material of the motherboard, and the material of the solder.

As described above, the stress generated by the temperature change between the motherboard and the motherboard can be reduced by the low-stress resin layer, and the mounting reliability on the motherboard can be improved.

Next, a method for manufacturing the wiring board of the present embodiment will be described.

In this embodiment, a low stress resin layer is formed on the back surface of the silicon substrate after the mechanical grinding or the CMP step of the back surface 110 of the silicon substrate shown in FIG. 28 in the seventh embodiment. A process is provided. That is, a liquid low-stress resin before curing is applied to the back surface of the silicon substrate, and a low-stress resin layer is formed only at a necessary portion by exposure and development, followed by heating and curing. The surface of the low-stress resin may be processed by a CMP method in order to flatten the surface after curing.

Next, the semiconductor device of the present invention will be described.

Each embodiment of the semiconductor device described below is composed of the above-described embodiments of the wiring board, and will be described as a ninth embodiment and a tenth embodiment.

The ninth embodiment of the present invention will be described.

The semiconductor device of the present embodiment uses the wiring board of the seventh embodiment, and the contents common to the seventh embodiment are omitted, and the same components are denoted by the same reference numerals. Is attached.

FIG. 40 is a sectional view of the semiconductor device of this embodiment.

In the semiconductor device of this embodiment, one or a plurality of semiconductor chips 137 are mounted on the wiring substrate shown in the seventh embodiment, and the wiring substrate 111 is connected to the bumps 138.
And mounted on the motherboard 139. The wiring substrate 111 includes a silicon substrate 106 as a base material, and the silicon substrate 106 is formed with a slope 108 having an obtuse interior angle with the back surface 110. And a first conductive pattern 112 formed in the surface 107 of the silicon substrate 106 and the through hole 109.
And a second conductive pattern 113 formed on the back surface 110 and the slope 108. The first conductive pattern 112 and the second conductive pattern 113 are
And the slope 108 is directly electrically connected. The first conductive pattern 112 and the silicon substrate 1
Between the second conductive pattern 113 and the silicon substrate 106, a first insulating layer 115 is formed and electrically insulated. Further, the surface of the first conductive pattern 112 other than the electrode portion 116 and the second conductive pattern 11
The surface other than the electrode portion 117 and the slope 108 are the second surface.
Covered with an insulating layer 118.

As described above, the semiconductor chip is electrically connected to the first conductive pattern of the silicon wiring board via the metal bump, and the second conductive pattern is electrically connected to the motherboard via the bump.

By using the wiring substrate of the present embodiment made of silicon as a base material, the thermal expansion characteristics of the semiconductor chip and the wiring substrate are substantially the same, the reliability of the joint can be ensured, and the flatness of the wiring substrate can be ensured. Since the degree and dimensional accuracy are improved as compared with the conventional resin wiring board, high-density mounting corresponding to the wiring density of the semiconductor chip becomes possible. In addition, by interposing metal bumps at the joint between the wiring board and the motherboard, it is possible to reduce the stress at the joint and improve the joint reliability.

Next, a tenth embodiment of the present invention will be described.

The semiconductor device of this embodiment uses the wiring board of the eighth embodiment, and the contents common to the eighth embodiment are omitted, and the same components are the same. Are given.

FIG. 41 is a sectional view of the semiconductor device of the present embodiment.

As shown in FIG. 41, in the wiring board of the semiconductor device of this embodiment, a low stress resin layer 136 is formed between the silicon substrate 106 and the second conductive pattern 113. The low-stress resin layer 136 is formed on the silicon substrate 1.
06 and the first conductive pattern 112.

According to the present embodiment, the stress generated between the wiring board and the motherboard due to the temperature change is reduced by the low-stress resin layer, and the reliability of mounting the wiring board on the motherboard can be improved. In addition, with a semiconductor device in which a semiconductor chip is mounted on a wiring substrate made of silicon, the thermal expansion characteristics of the semiconductor chip and the wiring substrate are almost the same, so that the reliability of the bonding portion can be ensured and the metal bumps can be formed. Since the stress at the joint between the used wiring board and the motherboard is reduced, the bonding reliability is improved, and the flatness and dimensional accuracy of the wiring board using the silicon substrate improve the bonding stability, miniaturization and high density. And high speed can be realized.

Although the semiconductor chips are mounted on the wiring board in the ninth and tenth embodiments, electronic components other than the semiconductor chips may be mounted.

As described above, according to each embodiment of the semiconductor device of the present invention, when the same silicon as the material of the semiconductor chip is used for the wiring board, the semiconductor device is heated at the time of mounting the semiconductor chip at the junction between the semiconductor chip and the wiring board. Since the thermal stress is reduced, the bonding reliability is improved, and the wiring pattern formed on the wiring board has the same flatness and dimensional accuracy as the wiring pattern formed on the semiconductor chip.
High-density mounting of a semiconductor chip on a wiring board can be realized. Further, by mounting the wiring board on the motherboard via the metal bumps, the stress due to the metal bumps can be reduced, and the bonding reliability is improved.

In addition, the slope can be shortened by forming a slope having an obtuse interior angle with the back surface of the wiring board as a part of the outer shape of the wiring board, and the wiring can be shortened. A semiconductor device on which a semiconductor chip to be protected is mounted can be realized.

Further, by forming a low-stress resin layer on the front surface or the back surface of the silicon substrate, the stress generated between the wiring substrate and the mother board can be reduced, and the bonding reliability is improved.

As described above, according to the wiring substrate and the method of manufacturing the same of the present invention, the electrodes on both surfaces of the silicon substrate are electrically connected via the conductive patterns formed in the through holes. Therefore, the semiconductor device using this wiring board reduces the stress of each bonding portion via the metal bumps to increase the reliability, and the flatness and dimensional accuracy of the wiring board using silicon improve the stability and stability of the bonding. Wiring density is improved,
Small size, high density and high speed can be realized.

Further, the slope can be shortened by forming a slope having an obtuse interior angle with the back surface of the wiring board as a part of the outer shape of the wiring board, and the wiring can be shortened. It is possible to realize a semiconductor device on which a semiconductor chip to be protected is mounted, and further, since a low-stress resin layer is formed on the back surface of the silicon substrate as described above, the semiconductor device is generated between the wiring board and the motherboard. Stress can be relieved, and bonding reliability is improved.

FIG. 4 shows an eleventh embodiment of the present invention.
2 will be described. FIG. 42 shows an eleventh embodiment of the present invention.
FIG. 3 is a cross-sectional view of a multi-chip semiconductor device according to an embodiment. This
Multi-chip semiconductor device has three semiconductor chips
1₁, 1_Two, 1_ThreeAre laminated. Each half
Conductor chip 1₁, 1_Two, 1_ThreeIs an integrated device
(Not shown) and multilayer conductive pattern formed thereon
From the semiconductor substrate 202 having a surface (not shown) on its surface.
The semiconductor substrate 202 is formed at an acute angle with the surface.
Inclined surface 203, which is
A plurality of recesses 204, and
One electrode 205 and a second electrode 206 formed on the back surface
And the front and back surfaces passing through the recess 204 and on the slope 203
The first electrode 205 and the second electrode
From the conductive pattern 207 for connecting to the pole 206
It is configured. First electrode 205 and semiconductor substrate 202
And between the second electrode 206 and the semiconductor substrate 202,
An insulating layer between the conductive pattern 207 and the semiconductor substrate 202;
208 are formed. In addition, each semiconductor chip 1₁,
1 _Two, 1_ThreeWiring on the semiconductor substrate 202 of FIG.
) Are provided with a surface electrode 209, respectively.
The surface electrode 209 is electrically connected to the conductive pattern 207.
Have been. In addition, each semiconductor chip 1₁, 1_Two, 1_ThreeIs
Except for the openings of the first electrode 205 and the second electrode 206
The surface is covered with an insulating layer 210. Semiconductor chip 1₁
The first electrode 205 is a connecting member such as a metal bump.
Via the semiconductor chip 1_TwoOf the second electrode 206
Is electrically connected to Thereby, the semiconductor chip 1
₁Is the semiconductor chip 1_TwoIt is electrically connected to
You. Similarly, semiconductor chip 1_TwoFirst electrode 205 is connected
The semiconductor chip 1 via the member 211_ThreeSecond electrode 2
06 and the semiconductor chip 1_TwoIs the semiconductor chip
Top 1_ThreeIs electrically connected to In this way,
Semiconductor chip 1₁, 1_Two, 1 _ThreeElectrical connection between
Will be.

According to [0264] this embodiment, for laminating semiconductor chips 1 _1, 1 _2, 1 _3, unlike the conventional multi-chip semiconductor device arranging a plurality of semiconductor chips in a plane, the number of semiconductor chips There is no problem that the area of the device increases as the number increases.

[0265] In order to connect via the electrodes 205 and 206 disposed on the front and back surfaces of the semiconductor chip ₁ 1 to 1 _3, a conventional multi-chip semiconductor to connect the semiconductor chip ₁ 1 to 1 ₃ in stacked metal wire Unlike the device, there is no restriction that the area of the semiconductor chip in the upper layer must be smaller and the surface electrode of the lower layer must be exposed, so it is desirable to stack semiconductor chips of the same size, as well as semiconductor chips of different sizes. Can be stacked in this order, and there is no problem that the wiring length between the semiconductor chips becomes long.

Furthermore, since the connection is made via electrodes arranged on the front and back surfaces of the semiconductor chip, unlike a conventional multi-chip semiconductor device having a COC structure in which surfaces are connected face to face, the number of stacked semiconductor chips is two. It is not limited to sheets. Since only semiconductor chips are stacked, unlike a conventional multi-chip semiconductor device in which the semiconductor chips are stacked using a wiring board, the height of the stacked semiconductor chips can be reduced, and the size of the stacked semiconductor chips itself is reduced by the mounting area of the device. can do.

Therefore, according to the present embodiment, the mounting area is small, the size and order of the semiconductor chips to be stacked are not limited, the wiring length between the semiconductor chips is short, the stacking height is low, and the stacking of the semiconductor chips is small. A small, high-density, high-speed multi-chip semiconductor device capable of two or more devices can be realized.

In this embodiment, the case where the number of stacked semiconductor chips is three has been described. However, according to the structure of this embodiment, even when the number of stacked semiconductor chips is four or more, the connection can be similarly performed. .

FIG. 43 is a sectional view of a multichip semiconductor device according to the twelfth embodiment of the present invention. Note that portions corresponding to the multi-chip semiconductor device of FIG.
The same reference numerals as in Fig. 2 denote the same parts, and a detailed description thereof will be omitted.

In the present embodiment, each of the electrodes 205 and 206
This is an example in which the connection member 211 is not used for connection. Semiconductor chip
Top 1₁The first electrode 205 of the semiconductor chip 1_TwoSecond
Is directly joined to the electrode 206. Semiconductor
Chip 1₁Is the semiconductor chip 1 _TwoElectrically connected to
And Semiconductor chip 1_TwoOf the first electrode 205 is a semiconductor
Directly connected to the second electrode 206 of the body chip 213,
It is pneumatically connected. In this way, the semiconductor chip
1₁, 1_Two, 1_ThreeThe connection is made electrically.

According to the present embodiment, by directly connecting the electrodes without using a connecting member, the stacked height can be further reduced and the wiring length can be shortened. Therefore, the same effect as that of the first embodiment can be obtained, and furthermore, a multi-chip semiconductor device having a shorter wiring length between semiconductor chips, a lower stacking height, a smaller size, and a higher speed can be realized.

FIGS. 44 to 46 are process sectional views showing a method for manufacturing a semiconductor chip of a multichip semiconductor device according to the thirteenth embodiment of the present invention.

First, as shown in FIG. 44A, a semiconductor substrate 212 in a wafer state is prepared. This semiconductor substrate 21
Reference numeral 2 denotes a device after a device (not shown) and a multilayer conductive pattern (not shown) are formed on the surface. The multilayer conductive pattern is provided with a surface electrode 213, and a desired region of the surface is made of SiN. An insulating layer 214 and a resin layer 215 made of polyimide are formed. Note that the insulating layer 214 and the resin layer 215 may or may not be formed of another material.

Next, as shown in FIG. 44B, a recess 217 is formed on the surface of the semiconductor substrate 12 so as to straddle the scribe line 216 by RIE. At this time, a mask is formed so that other portions are not etched, and the mask is removed after the etching. The depth of the recess 217 is 20
１００100 μm. FIG. 47 shows a partial plan view at this time. FIGS. 44 (b) and 47 (b) are cross-sectional views taken along line VV 'of FIG. 47 (a). Note that the method for forming the recess 217 is not limited to the RIE method, and light etching, wet etching, ultrasonic processing, electric discharge processing, or the like can also be used. Further, the above processing methods may be combined.

Next, as shown in FIG. 44C, a first insulating layer 218 is formed on the entire surface including the inner wall of the recess 217 except for the opening of the surface electrode 213. At that time, after forming the first insulating layer 218 over the entire surface, a mask is formed,
After etching the first insulating layer 218 in the opening of the surface electrode 213, the mask is removed. Note that the first insulating layer 218 is formed using a layer such as a SiO ₂ , SiN, SiON, or polyimide film by a CVD method, a sputtering method, an optical CVD method, coating, or the like.

Next, as shown in FIG. 44D, a laminated metal film in which a barrier layer 219 and a seed layer 220 are sequentially laminated on the entire surface is formed. Barrier layer 219 and seed layer 220
Is formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer is made of Ti, Ti / W, C
r or Ni, and the seed layer is Cu, Au, Ag or Ni.
And so on.

Next, as shown in FIG. 44E, the recess 217 is filled and the first conductive pattern 221 is formed in a desired wiring and electrode shape by electrolytic plating using the seed layer 220 as an electrode. At this time, a plating resist 2 is formed on the seed layer 220 in order to obtain desired wiring and electrode shapes.
22 is formed, and after electrolytic plating, the plating resist 2
22 is removed. Cu, A as the first conductive pattern
u, W, Mo, Ni, Ti, Al and the like are used.

Next, as shown in FIG. 44 (f), the seed layer 220 other than the region where the first conductive pattern 221 is formed is removed by etching using the first conductive pattern 221 as a mask. The first conductive pattern 22 is etched by using the conductive pattern 221 as a mask.
The barrier layer 219 other than the region where 1 is formed is removed.

Next, as shown in FIG. 44 (g), the second insulating layer 2 is formed on the entire surface of the first electrode 223 except for the opening.
24 are formed. At this time, after forming the second insulating layer 224 over the entire surface, a mask is formed. After the second insulating layer 224 in the opening of the first electrode 223 is etched, the mask is removed. Note that the second insulating layer 224 is made of SiO.
2. Layers such as SiN, SiON, polyimide film, etc.
It is formed by a D method, a sputtering method, a photo CVD method, coating, or the like.

As a result, the surface electrode 21
3, only the first electrode 223 electrically connected to the second
Is formed so as to be exposed from the insulating layer 224.

Next, as shown in FIG. 45A, the wafer surface is adhered to a support 226 with an adhesive 225, and the semiconductor substrate 212 is polished from the back surface to reduce the thickness to a desired thickness. The polishing method may be mechanical polishing or CMP. The thickness of the semiconductor substrate is 50 to 200 μm.

Next, as shown in FIG. 45B, an inclined surface 227 forming an acute angle with the front surface is formed from the back surface of the semiconductor substrate 212 by bevel cutting, and the first conductive pattern 221 is seen from the back surface. The exposure to the slope 227 and the division into the semiconductor chip 228 are simultaneously performed.

Note that the processing method may be etching.

Next, as shown in FIG. 45C, a third insulating layer 229 is formed on the slope 227 and the entire back surface of the first conductive pattern 221 except for the portion exposed on the slope 227. At this time, after forming the third insulating layer 229 on the slope 227 and the entire back surface, a mask is formed, and after the third insulating layer 229 in the opening of the first conductive pattern 221 is etched, the mask is removed. . Note that the third insulating layer 229
Is to form a layer such as SiO ₂ , SiN, SiON, polyimide film by CVD method, sputtering method, photo CVD method, coating or the like.

The third insulating layer 229 is formed of the first insulating layer 21
8 and the second insulating layer 224 are desirably formed of a material having a higher etching rate.

Thus, when the third insulating layer 229 is opened by etching, even if a mask shift occurs, the third insulating layer 218 and the second insulating layer 224 are hardly etched and the third insulating layer 229 is etched. The first conductive pattern 2 can be selectively etched to form openings.
The first insulating layer 218 and the second insulating layer 224 covering
Is not partially removed.

Next, as shown in FIG.
7 and a barrier layer 230 and a seed layer 231 on the entire back surface.
Are sequentially laminated to form a laminated metal film. Barrier layer 230
The seed layer 231 is formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer 230 is made of Ti, Ti / W, Cr or Ni, and the seed layer 231 is made of C
u, Au, Ag, Ni, or the like is used.

Next, as shown in FIG. 46A, the first conductive pattern 2 exposed from the slope 227 is formed on the slope 227 and the rear face by electrolytic plating using the seed layer 231 as an electrode.
21 so as to connect to the second wiring 21
Is formed. At this time, a plating resist 233 is formed on the seed layer 231 in order to obtain desired wiring and electrode shapes, and the plating resist 233 is removed after electrolytic plating. Second conductive pattern 232
Used are Cu, Au, W, Mo, Ni, Ti, Al and the like.

Next, as shown in FIG. 46B, the seed layer 231 other than the region where the second conductive pattern 232 is formed is removed by etching using the second conductive pattern 232 as a mask. The second conductive pattern 23 is etched by using the conductive pattern 232 as a mask.
The barrier layer 230 other than the region where 2 is formed is removed.

Next, as shown in FIG. 46C, a fourth insulating layer 235 is formed on the entire slope 227 and the back surface except for the opening portion of the second electrode 234 and the scribe line 216. At this time, after forming the fourth insulating layer 235 on the slope 227 and the entire back surface, a mask is formed, and the fourth insulating layer 235 at the opening of the second electrode 234 and the fourth insulating layer on the scribe line 216 are formed. Layer 235 and third insulating layer 2
After etching 29, the mask is removed. Note that the fourth insulating layer 235 is formed by depositing a layer such as SiO ₂ , SiN, SiON, or a polyimide film by a CVD method, a sputtering method,
It is formed by a method, coating or the like.

Next, as shown in FIG.
25 and the support 226 are removed, and the semiconductor chip 228 is divided into individual pieces.

As a result, only the first electrode 223 is formed on the surface of the semiconductor chip 228 so as to be exposed from the second insulating layer 224, and only the second electrode 234 is formed on the back surface of the fourth insulating layer 235. It is formed in a state exposed from
Surface electrode 213, first electrode 223, and second electrode 234
Thus, a structure in which the and are electrically connected is completed.

As described above, the present embodiment includes the step of forming the concave portion 217 on the surface of the semiconductor substrate 212 so as to straddle the scribe line 216 and the step of bevel-cutting the scribe line 216 from the back surface. Accordingly, the first electrode 223 and the second electrode 223 electrically connected to each other and also electrically connected to the surface electrode 213 are formed.
Having the electrodes 234 on the front and back surfaces of the chip of the semiconductor substrate 212 can be formed.

Therefore, according to the present embodiment, after the first conductive pattern 221 is formed on the front surface side of the semiconductor substrate 212 where the concave portion 217 is formed, the first conductive pattern 221 is formed on the back surface side where the inclined surface 227 forming an acute angle with the front surface is formed. By simply forming the second conductive pattern 232, it is possible to form a wiring that conducts from the front surface to the rear surface, and it is possible to easily form the front and back conductive electrodes.

According to the present embodiment, first conductive pattern 221 is formed in concave portion 217 formed in a wafer state.
By forming an acute angle at the center of the concave portion 217 after forming the concave portion 217, a part of the first conductive pattern 221 for wiring can be seen from the rear surface.
7 need not be formed extremely deep.
Since it is not necessary to grind 12 extremely thinly, the degree of freedom in setting the thickness of the semiconductor chip 228 is large, the number of manufacturing steps can be reduced, and the cost of a chip for a multi-chip semiconductor device can be reduced.

Further, according to the present embodiment, the step of forming first electrode 223 and the step of forming first conductive pattern 221 can be performed simultaneously, and the step of forming second electrode 234 can be performed simultaneously. And the second conductive pattern 232
Can be performed simultaneously, so that the number of manufacturing steps can be further reduced.

Further, according to the present embodiment, it is possible to form a slope 227 forming an acute angle with the surface by bevel cutting, to divide the semiconductor chip 228 into individual pieces,
The first conductive pattern can be made visible from the back side at the same time, and the number of manufacturing steps and manufacturing cost can be significantly reduced as compared with the case where the first conductive pattern is formed by other means.

The barrier layer (21) must be provided under the first conductive pattern 221 and the second conductive pattern 232.
9, 230) and the seed layer (220, 231), the constituent elements of the first conductive pattern 221 and the second conductive pattern 232 are changed by the barrier layer (219, 230) to the surface electrode 213 and the semiconductor substrate. The characteristic deterioration of the semiconductor chip due to the diffusion into 212 can be prevented, and the first conductive pattern 221 and the second conductive pattern 232 can be formed by electrolytic plating using the seed layer (220, 231). .

FIG. 49 is a cross-sectional view showing a case where the bevel cut line is shifted in the step of FIG.
The same reference numerals as in FIG. In FIG. 49, AA 'indicates a line to be originally cut, and BB' indicates a case where the line is deviated. Even in the case of such displacement, the recess 217 is always present.
By making the width of the concave portion sufficiently large so that the bottom surface of the first conductive pattern 221 is cut, the distance from the center of the exposed first conductive pattern 221 to the contact point between the slope and the back surface on the slope formed by cutting each line. C and D are equal,
The shape and position of the exposed first conductive pattern 221 can be stabilized.

FIG. 50 is a diagram showing another method in the step of FIG. 44 (b), and portions common to FIG. 44 are denoted by the same reference numerals. The recess 21 in the step of FIG.
7 and a scribe line 2 on the surface of the semiconductor substrate 212
A groove 237 is formed by dicing so as to straddle 16. The depth of the groove 237 is 20 to 100 μm. By forming them collectively by dicing, the number of steps can be reduced and the formation can be performed in a shorter time than in the case of forming by etching.

FIG. 48 is a process sectional view showing the method for manufacturing the semiconductor chip of the multi-chip semiconductor device according to the fourteenth embodiment of the present invention. 44, 45, and 46 are denoted by the same reference numerals as in FIGS. 44, 45, and 46, and will not be described in detail. In this embodiment, after the step of FIG. 46B of the thirteenth embodiment, as shown in FIG. 48A, the entire back surface except for the slope 227 and the opening of the second electrode 234 is formed. A liquid resin is applied so as to be flat and cured to form an insulating resin layer 236. This embodiment mode is shown in FIG.
Although the process is performed after the step (b), the process may be performed after the process of FIG.
As the liquid resin, a resin such as polyimide which can relieve stress is preferable.

Next, as shown in FIG. 48B, dicing is performed from the back surface to form side surfaces perpendicular to the front surface.

Next, as shown in FIG. 48 (c), the adhesive 2
25 and the support 226 are removed, and the semiconductor chip 228 is divided into individual pieces.

As described above, in the present embodiment, the side surface formed by the slope 227 can be embedded with the liquid resin, and the cured liquid resin portion is diced to make the thick insulating resin layer perpendicular to the surface. The sides formed at 236 can be obtained and at the same time singulated.

Therefore, the side surface of the chip for a multi-chip semiconductor device can be reinforced and the protection of the second conductive pattern 232 on the slope 227 can be enhanced.

FIG. 51 is a sectional view of a multichip semiconductor device according to the fifteenth embodiment of the present invention. Note that portions corresponding to the multi-chip semiconductor device of FIG.
The same reference numerals as in FIG. 2 denote the same parts, and a detailed description thereof will be omitted.

[0307] This embodiment is characterized in that at least one of the front and back conductive electrodes formed on the semiconductor chip 1 ₂ although it is not connected to the surface electrode.

[0308] The multi-chip semiconductor device has three semiconductor chips 1 _1, 1 _2, 1 ₃ is in the stacked configuration. The semiconductor chip 1 ₁ and 1 _3, the first electrode 205 formed on the surface, a second electrode 206 formed on the back surface
When, by the surface electrode 209 is a conductive pattern 207 are electrically connected, the semiconductor chip 1 ₂ has a conductive pattern 238 that is not electrically connected to at least one surface electrode 209, the conductive patterns 238 on the surface Is electrically connected to the second electrode 240 formed on the back surface.

[0309] Thus, the first electrode 205 of the semiconductor chip 1 ₁ electrically connected to the second electrode 240 of the semiconductor chip 1 ₂ is electrically connected to the first electrode 239 of the semiconductor chip 1 ₂ and the second electrode 20 of the semiconductor chip 1 ₃
6 is electrically connected, will not be connected to the semiconductor chip 1 _{and second} integrated circuits.

[0310] Thus, according to this embodiment, the semiconductor chip 1 _{and second} integrated circuits like to electrically electrically connect and each other without the need to connect to the electrodes (205,20
If 6) is in the semiconductor chip 1 ₁ and 1 _3, the front and back conductive electrodes in the integrated circuits formed the electrodes of the (205, 206) on the semiconductor chip 1 ₂ are not electrically connected (2
39, 240), the semiconductor chip 1
₂ will be able to pass.

A sixteenth embodiment of the present invention will be described with reference to FIG. FIG. 52 is a sectional view of a multichip semiconductor device using a silicon wiring substrate according to a sixteenth embodiment of the present invention.

As shown in FIG. 52, in this multi-chip semiconductor device, a plurality of electronic components such as a plurality of semiconductor chips 308 are mounted on the surface of a silicon wiring board 301 alone or in a stacked manner. It is a configuration implemented in. The silicon wiring substrate 301 has a silicon substrate 305 made of silicon, and has a first conductive pattern 302 formed on the front surface, a second conductive pattern 303 formed on the back surface, and a third conductive pattern 303 formed on the side surface.
And the conductive pattern 304. The first conductive pattern 302 and the second conductive pattern 303 are electrically connected via a third conductive pattern 304.
The first conductive pattern 302 has at least one layer for mounting and wiring electronic components 308, and the second conductive pattern 303 has at least one layer having electrodes for mounting on the motherboard 7.

Further, an insulating layer 310 is provided between the first conductive pattern 302 and the silicon substrate 305, between the second conductive pattern 303 and the silicon substrate 305, and between the third conductive pattern 304 and the silicon substrate 305. Are formed and electrically insulated. The silicon wiring substrate 301 has a first
Of the conductive pattern 302 and the second conductive pattern 3
The entire surface other than the electrode part 03 is covered with an insulating layer 311. The semiconductor chip 308 is connected via a metal bump 309
It is electrically connected to the first conductive pattern 302 of the silicon wiring board 301. The second conductive pattern 303 of the silicon wiring board 301 is
It is electrically connected to the motherboard 7. In this way, each of the plurality of semiconductor chips 308 is
And is also electrically connected to the motherboard 307.

For the wiring substrate for a multi-chip semiconductor device, a step of forming a first conductive pattern 302 on the front surface of a silicon wafer and a step of forming a second conductive pattern
Forming the conductive pattern 303, dividing the silicon wafer into individual silicon substrates 305 to form side surfaces, and electrically connecting the first conductive pattern 302 and the second conductive pattern 303. And forming a third conductive pattern 304 on the side surface.

After the step of forming the first conductive pattern, a step of dividing the silicon wafer into individual silicon substrates to form side surfaces is performed, and thereafter, a step of forming a second conductive pattern and a step of forming a second conductive pattern are performed. The step of forming the third conductive pattern may be performed simultaneously.

According to this embodiment, it is possible to obtain a wiring substrate using silicon as a base material, and a multi-chip semiconductor device using the same can reduce the stress at the joints of the metal bumps and improve the reliability. In addition, the bonding stability is enhanced by the flatness and dimensional accuracy of the wiring board, and the wiring density can be improved at a level that cannot be achieved by the resin wiring board, so that miniaturization, high density and high speed can be realized.

A seventeenth embodiment of the present invention will be described with reference to FIG. FIG. 53 is a sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to a seventeenth embodiment of the present invention.

As shown in FIG. 53, in this multi-chip semiconductor device, a plurality of electronic components such as a plurality of semiconductor chips 308 are mounted on the surface of a silicon wiring substrate 312 singly or in a stacked manner. It is a configuration implemented in. Silicon wiring board 312
Is composed of a silicon substrate 305, and the silicon substrate 3
05 is an inclined surface 314 which is four side surfaces formed at an acute angle with the surface, and a plurality of concave portions 31 formed around the surface.
3 and includes a first conductive pattern 302 formed on the front surface and the concave portion 313, and a second conductive pattern 303 formed on the rear surface and the inclined surface 314. First conductive pattern 302 and second conductive pattern 3
Numeral 03 is directly electrically connected at the joint between the concave portion 313 and the slope 314. The first conductive pattern 302 has at least one layer for mounting and wiring the electronic component 308, and the second conductive pattern 303 has at least one layer having electrodes for mounting on the motherboard 307. When the silicon substrate 312 is used upside down, the first conductive pattern 302 is
7 has at least one layer having electrodes for mounting, and the second conductive pattern 303 has at least one layer for mounting and wiring electronic components.

Further, an insulating layer 310 is formed between the first conductive pattern 2 and the silicon substrate 305 and between the second conductive pattern 303 and the silicon substrate 305 to be electrically insulated. The entire surface of the silicon wiring board 312 other than the electrode portions of the first conductive pattern 302 and the electrode portions of the second conductive pattern 303 is covered with an insulating layer 311. The semiconductor chip 308 is electrically connected to the first conductive pattern 302 of the silicon wiring board 312 via the metal bump 309. The second conductive pattern 303 of the silicon wiring board 312 is electrically connected to the motherboard 307 via the solder balls 306. In this way, each of the plurality of semiconductor chips 308 is electrically connected to each semiconductor chip 308 via the silicon wiring substrate 301 and also electrically connected to the motherboard 307.

According to this embodiment, a wiring substrate using silicon as a base material can be easily obtained, and a multi-chip semiconductor device using the same can reduce the stress at the joints of metal bumps and improve reliability. , The bonding stability is enhanced by the flatness and dimensional accuracy of the wiring board, and the wiring density can be improved at a level that cannot be achieved by a resin wiring board, and a small size, high density, and high speed can be realized.

An eighteenth embodiment of the present invention will be described with reference to FIG. FIG. 54 is a sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to the third embodiment of the present invention. As shown in FIG. 54, the silicon wiring substrate 315 of this multi-chip semiconductor device has a low-stress resin layer 316 between the second conductive pattern 303 and the silicon substrate 305. Note that portions corresponding to the multi-chip semiconductor device of FIG. 52 are denoted by the same reference numerals as those of FIG. 52, and detailed description thereof will be omitted.

According to this embodiment, the stress caused by a temperature change between the motherboard and the motherboard can be reduced by the resin layer, and the mounting reliability on the motherboard can be improved. Further, the resin layer 316 of this embodiment is
3 may be applied to the multi-chip semiconductor device. In the present embodiment, the second conductive pattern 303 is
07, the case where the first conductive pattern 302 is used upside down, that is, the case where the first conductive pattern 302 is connected to the motherboard 307, has a low stress between the first conductive pattern 302 and the silicon substrate 305. A resin layer 316 is formed. In addition, the first
Between the conductive pattern 302 and the silicon substrate 305,
A low-stress resin layer 316 may be formed both between the second conductive pattern 303 and the silicon substrate 305.

The nineteenth embodiment of the present invention is shown in FIGS.
58 will be described. 55 to 57 are process cross-sectional views showing a method for manufacturing a wiring board for a multichip semiconductor device according to a nineteenth embodiment of the present invention, and FIG.
FIG. 39 is a plan view showing a method for forming a concave portion of a chip for a multi-chip semiconductor device according to a ninth embodiment.

As shown in FIG. 57 (d), this silicon wiring substrate 330 has a side surface (slope 329) formed at an acute angle with the surface and a concave portion 319 around the surface, similarly to the second embodiment. A first conductive pattern 323 formed on the surface of the silicon substrate 317 and in the recess 319 and having at least one layer of electrodes, and a silicon substrate 317.
Formed on the back and side surfaces of the first conductive pattern 323
And a second conductive pattern 334 composed of at least one layer having electrodes.

Next, a method of manufacturing the wiring board for a multi-chip semiconductor device having the above configuration will be described. First, FIG.
A silicon substrate 317 in a wafer state is prepared as shown in FIG.

Next, as shown in FIG. 55B, scribe lines 318 are formed on the surface of the silicon substrate 317 by RIE.
The recess 319 is formed so as to straddle. At this time, a mask is formed so that other portions are not etched, and the mask is removed after the etching. The depth of the recess 319 is 2
0 to 100 μm. FIG. 58 shows a partial plan view at this time. FIG. 55B is a cross-sectional view taken along the line VV ′ of FIG. Note that the method for forming the concave portion 319 is not limited to the RIE method, and light etching, wet etching, ultrasonic processing, electric discharge processing, or the like can also be used. Further, the above processing methods may be combined.

Next, as shown in FIG.
The first insulating layer 320 is formed on the entire surface including the inner wall of No. 9. Note that the first insulating layer 320 is made of SiO ₂ , SiN, S
A layer such as an iON or a polyimide film is formed by a CVD method, a sputtering method, an optical CVD method, coating, or the like.

Next, as shown in FIG. 55D, a laminated metal film in which a barrier layer 321 and a seed layer 322 are sequentially laminated on the entire surface is formed. Barrier layer 321 and seed layer 322
Is formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer 321 is made of Ti, Ti /
W, Cr or Ni, the seed layer 322 is Cu, Au, A
g or Ni is used.

Next, as shown in FIG. 55E, the recess 319 is buried and the first conductive pattern 323 is formed in a desired wiring and electrode shape by electrolytic plating using the seed layer 322 as an electrode. At this time, a plating resist 3 is formed on the seed layer 322 in order to obtain desired wiring and electrode shapes.
24, and after electrolytic plating, the plating resist 3
24 is removed. Wiring materials include Cu, Au, W, M
o, Ni, Ti, Al, etc. are used.

Next, as shown in FIG. 55 (f), the seed layer 322 other than the region where the first conductive pattern 323 is formed is removed by etching using the first conductive pattern 323 as a mask. The first conductive pattern 32 is etched by using the conductive pattern 323 as a mask.
The barrier layer 321 other than the region where 3 is formed is removed.

Next, as shown in FIG. 55 (g), a second insulating layer 325 is formed on the entire surface excluding the first conductive pattern electrode portion 326. At this time, after forming the second insulating layer 325 over the entire surface, a mask is formed. After the second insulating layer 325 on the first conductive pattern electrode portion 326 is etched, the mask is removed. Note that the second insulating layer 325
Is to form a layer such as SiO ₂ , SiN, SiON, polyimide film by CVD method, sputtering method, photo CVD method, coating or the like.

As a result, only the first conductive pattern electrode portion 326 is formed on the wafer surface while being exposed from the second insulating layer 325.

Next, as shown in FIG. 56 (a), the surface of the wafer is bonded to a support 327 with an adhesive 328, and the silicon substrate 317 is polished from the back surface to reduce the thickness to a desired thickness. The polishing method may be mechanical polishing, chemical polishing or CMP. The thickness of the silicon substrate 317 is 50 to 200 μm.

Next, as shown in FIG. 56B, bevel cutting is performed from the back surface of the silicon substrate 317 with a scribe line to form an inclined surface 329 that forms an acute angle with the front surface, and the first conductive pattern 323 is formed. Is exposed on the inclined surface 329 so as to be seen from the back surface, and the silicon wiring board 33 is exposed.
The division into 0 is performed at the same time. Note that the processing method may be etching.

Next, as shown in FIG. 56 (c), a third insulating layer 331 is formed on the slope 329 and the entire back surface of the first conductive pattern 323 except for the portion exposed on the slope 329. At this time, after forming the third insulating layer 331 on the slope 329 and the entire back surface, a mask is formed, and after the third insulating layer 331 in the opening of the first conductive pattern 323 is etched, the mask is removed. . Note that the third insulating layer 331
Is to form a layer such as SiO ₂ , SiN, SiON, polyimide film by CVD method, sputtering method, photo CVD method, coating or the like. The third insulating layer 331 includes the first insulating layer 32
It is preferable that the second insulating layer 325 be formed of a material having a higher etching rate than the second and third insulating layers 325. Thereby, when the third insulating layer 331 is opened by etching, even if a mask shift occurs, the third insulating film 320 and the second insulating layer 325 are hardly etched and the third insulating film 331
Can be selectively etched to form an opening, and the first insulating layer 320 and the second insulating layer 320 covering the first conductive pattern 323 can be formed.
The insulating layer 325 is not partially removed.

Next, as shown in FIG.
9 and a barrier layer 332 and a seed layer 333 on the entire back surface.
Are sequentially laminated to form a laminated metal film. Barrier layer 332
The seed layer 333 is formed by a sputtering method, a CVD method, an electron beam evaporation method, or the like. The barrier layer is Ti,
Ti / W, Cr or Ni, seed layer is Cu, Au, A
g or Ni is used.

Next, as shown in FIG. 57 (a), the first conductive pattern 3 exposed from the slope 329 is formed on the slope 329 and the back face by electrolytic plating using the seed layer 333 as an electrode.
A second conductive pattern 334 is formed in a desired wiring and electrode shape so as to be electrically connected to. At this time, a plating resist 335 is formed on the seed layer 333 in order to obtain a desired wiring and electrode shape, and the plating resist 335 is removed after electrolytic plating. As the wiring material, Cu, Au, W, Mo, Ni, Ti, Al or the like is used.

Next, as shown in FIG. 57 (b), the seed layer 333 other than the region where the second conductive pattern 334 is formed is removed by etching using the second conductive pattern 334 as a mask. The second conductive pattern 33 is etched by using the conductive pattern 334 as a mask.
The barrier layer 332 other than the region where 4 is formed is removed.

Next, as shown in FIG. 57C, the second conductive pattern electrode portion 337 and the adhesive 328 are removed.
A fourth insulating layer 336 is formed on the entire back surface including the slope 329.
To form At this time, the fourth insulating layer 336 is sloped 329.
After forming the mask on the entire back surface, a mask is formed, and the fourth insulating layer 336 on the second conductive pattern electrode portion 337 and the fourth insulating layer 336 and the third insulating layer 3 on the adhesive 328 are formed.
After etching 31, the mask is removed. The fourth insulating layer 336 is formed by depositing a layer such as SiO2, SiN, SiON, or a polyimide film by a CVD method, a sputtering method, or an optical CVD method.
It is formed by a method, coating or the like.

Next, as shown in FIG.
28 and the support 327 are removed, and the silicon wiring substrate 33 is removed.
Get 0.

As a result, only the first conductive pattern electrode portion 326 is formed on the surface of the silicon wiring substrate 330 so as to be exposed from the second insulating layer 325, and only the second conductive pattern electrode portion 337 is formed on the back surface. The first conductive pattern electrode portion 326 on the front surface and the second conductive pattern electrode portion 3 on the rear surface are formed so as to be exposed from the fourth insulating layer 336.
37 is completed.

As described above, in this embodiment,
By providing a step of forming a concave portion 319 on the surface of the silicon substrate 317 so as to straddle the scribe line 318 and a step of bevel-cutting the scribe line 318 from the back surface, a conductive pattern is formed only from the front surface and the back surface. Can be formed having electrodes electrically connected to the silicon wiring substrate 330 on each of the front surface and the back surface.

Therefore, according to the present embodiment, the front and back conductive electrodes can be easily formed.

According to the present embodiment, the first conductive pattern 323 is formed in the concave portion 319 formed in a wafer state, and then the first conductive pattern 323 is cut at the central portion of the concave portion 319 at an acute angle with the surface. Since a part of the conductive pattern 323 for wiring can be seen from the back surface, the concave portion 319 is formed.
Need not be formed extremely deep, and the silicon substrate 3
Since it is not necessary to grind 17 extremely thinly, the degree of freedom in setting the thickness of the silicon wiring substrate 330 is large, the number of manufacturing steps can be reduced, and the cost can be reduced.

Further, according to the present embodiment, the slope 329 forming an acute angle with the front surface is formed by bevel cutting, the silicon wiring substrate 330 is divided into individual pieces, and the first conductive pattern 323 is formed on the back surface. Can be performed at the same time, and the number of manufacturing steps and manufacturing costs can be significantly reduced as compared with the case where the formation is performed by other means.

The twentieth embodiment of the present invention will be described with reference to FIG. FIG. 59 is a process sectional view showing the method for manufacturing the multi-chip semiconductor device wiring substrate according to the twentieth embodiment of the present invention.

As shown in FIG. 59 (c), this silicon wiring substrate 330 has a side surface (slope 329) formed at an acute angle to the surface and a recess 319 around the surface, as in the second embodiment. A first conductive pattern 323 formed on the surface of the silicon substrate 317 and in the recess 319 and having at least one layer of electrodes, and a silicon substrate 317.
Formed on the back and side surfaces of the first conductive pattern 323
And a second conductive pattern 334 comprising at least one layer having electrodes, and an insulating layer 338 is formed on the side surface so as to be perpendicular to the surface of the silicon substrate 317.

Next, a method of manufacturing the wiring board for a multi-chip semiconductor device having the above configuration will be described. In addition, FIG.
Parts corresponding to the multi-chip semiconductor device wiring board 57 are denoted by the same reference numerals as in FIGS. 55 to 57, and detailed description thereof is omitted.

In this embodiment, after the step of FIG. 57 (b) of the nineteenth embodiment, as shown in FIG. 59 (a), the entire back surface and the slope except for the second conductive pattern electrode portion 337 are formed. At 329, an insulating resin layer 338 is formed. At this time, a liquid resin is applied to the inclined surface 329 and the entire back surface so as to be flat, and is formed by exposing and developing so as to open the second conductive pattern electrode portion 337. Although the present embodiment is performed after the step of FIG. 57B, it may be performed after the step of FIG. As the liquid resin, a resin such as polyimide which can relieve stress is preferable.

Next, as shown in FIG. 59 (b), dicing is performed from the back surface along scribe lines to form side surfaces perpendicular to the front surface.

Next, as shown in FIG. 59 (c), the adhesive 3
28 and the support 327 are removed, and the silicon wiring substrate 33 is removed.
Get 0.

As described above, in this embodiment,
The side surface formed by the inclined surface 329 can be embedded with the liquid resin, and the cured liquid resin portion is diced to obtain the side surface formed by the thick insulating resin layer 338 perpendicular to the surface, and at the same time, it is divided into pieces. be able to.

Therefore, the side surface of the wiring board for a multi-chip semiconductor device is reinforced and the second
Of the conductive pattern 334 can be enhanced.

The above embodiment is an example, and the present invention is not limited to the above embodiment. In addition, without departing from the gist of the present invention,
Various modifications can be made.

[0355]

According to the semiconductor chip of the first aspect,
Since it is possible to realize a semiconductor chip in which electrodes on both sides are connected through a through hole and a conductive pattern formed on a slope, it is possible to reduce the size, density, and speed of a semiconductor device in which semiconductor chips are stacked. Become.

According to the semiconductor chip of the second aspect, by forming such a conductive pattern, the electrodes between the semiconductor substrate and the conductive pattern and the electrodes on both surfaces of the semiconductor substrate exposed from the insulating layer are electrically connected. It can be connected, and since the electrodes and conductive patterns are covered with an insulating layer, it is possible to prevent electrical problems such as short-circuits and to protect the semiconductor chip against external impacts. And speeding up are also possible.

According to the third aspect of the present invention, there is provided a semiconductor chip comprising a semiconductor substrate on which elements are integrally formed, and having a front electrode and a back electrode connected through conductive patterns in concave portions around the surface and on side surfaces. A chip semiconductor device chip is obtained. Therefore, a multi-chip semiconductor device using such a chip for a multi-chip semiconductor device,
A small, high-density and high-speed multi-chip semiconductor device can be realized. Further, by forming and joining the conductive pattern on the inclined surface and the conductive pattern in the concave portion, processing can be performed easily and the bonding area between the conductive patterns can be increased.

According to the semiconductor chip of the fourth aspect, the first electrode, the second electrode, and the wiring connecting the first electrode and the second electrode passing through the inside of the recess and on the side surface are formed of a conductive pattern. The conductive pattern is electrically connected to the surface electrode, an insulating layer is formed on the surface of the conductive pattern excluding the first electrode and the second electrode, and an insulating layer is also formed between the conductive pattern and the semiconductor substrate. The obtained multi-chip semiconductor device chip is obtained. Therefore, a multichip semiconductor device using such a chip for a multichip semiconductor device can realize a small, high-density, high-speed multichip semiconductor device as in the first and second aspects.

According to the semiconductor chip of the fifth aspect, in addition to the same effects as those of the second or fourth aspect, the electrolytic chip is formed by the barrier layer and the seed layer constituting the laminated metal film by forming the laminated metal film. A conductive pattern using a plating method can be formed, and diffusion of constituent elements of the conductive pattern can be prevented.

According to the semiconductor chip of claim 6, in addition to the effects similar to those of claim 2, claim 4, or claim 5,
By using a semiconductor chip having at least one conductive pattern that is not connected to an integrated circuit, when stacking a plurality of semiconductor chips, a specific semiconductor chip is not electrically connected to an integrated circuit of the specific semiconductor chip. Other semiconductor chips can be electrically connected to each other.

According to the semiconductor chip of the seventh aspect, in addition to the same effect as the second or fourth aspect, a relatively thick insulating layer is formed on the second conductive pattern formed on the slope. In addition, the side surface of the semiconductor chip can be reinforced and the protection of the conductive pattern on the slope can be enhanced.

According to the semiconductor chip of the eighth aspect, in addition to the effect similar to that of the fifth aspect, the diffusion of the constituent elements of the conductive pattern can be prevented by the barrier layer, and the characteristic deterioration of the semiconductor chip can be prevented. Further, by providing the seed layer, it is possible to plate the conductive pattern by the electrolytic plating method.

According to the ninth aspect of the present invention, since the formation of the slope makes it unnecessary to form the hole deeply, the processing time can be shortened and the cost can be reduced. Further, since it is not necessary to grind the silicon substrate to reduce its thickness, stable conveyance can be ensured.

According to the tenth aspect of the present invention, there is provided a first conductive pattern for mounting and wiring electronic components on the front surface and a second conductive pattern including electrodes for mounting on the motherboard on the rear surface. A wiring substrate made of silicon is obtained in which the first conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface.

Since the silicon wiring substrate is not changed in shape due to humidity and is formed of the same silicon as the semiconductor chip, the shape change such as expansion and contraction due to temperature change is the same as that of the semiconductor chip. The degree of accuracy is high, the dimensional accuracy of the electrode position is high, and the pitch of the connection electrodes and the density of the wiring can be increased at the same level as the semiconductor chip.

Therefore, in a multi-chip semiconductor device using such a silicon wiring board, the stress at the bonding portion of the metal bump is reduced to enhance reliability, and the bonding stability is improved by the flatness and dimensional accuracy of the wiring board. Therefore, it is possible to increase the wiring density at a level that cannot be achieved by a resin wiring substrate, and it is possible to realize small size, high density, and high speed.

[0367] According to the eleventh aspect, the first conductive pattern is provided on the front surface and the second conductive pattern is provided on the back surface, and the first conductive pattern and the second conductive pattern are directly electrically connected to each other. A wiring substrate made of connected silicon is obtained.

Therefore, in a multi-chip semiconductor device using such a silicon wiring substrate, the stress at the bonding portion of the metal bump is reduced to enhance reliability, and the bonding stability is improved by the flatness and dimensional accuracy of the wiring substrate. Therefore, it is possible to increase the wiring density at a level that cannot be achieved by a resin wiring substrate, and it is possible to realize small size, high density, and high speed.

According to the twelfth aspect of the present invention, in addition to the same effects as the ninth and eleventh aspects, the side surface of the wiring substrate can be reinforced and the protection of the conductive pattern on the side surface can be improved.

According to the thirteenth aspect of the present invention, in addition to the effects similar to the ninth, tenth and eleventh aspects, the stress due to a temperature change generated between the semiconductor chip and the wiring board is alleviated. Therefore, the mounting reliability of the semiconductor chip can be improved.

According to the method for manufacturing a semiconductor chip of the present invention, since the inclined surface forming the second surface with an obtuse angle and the through hole are formed between the inclined surface and the first surface, By forming a conductive pattern in the through hole, the first surface and the second surface are formed.
Can be electrically connected to the first surface and, unlike the case where a through hole is first formed from the first surface to the second surface, a deep hole is formed or the semiconductor substrate is thinly formed on the back surface. It is not necessary to polish from the beginning, and the processing time can be shortened, so that the cost can be reduced. Further, the transfer is easier than a thinly processed semiconductor substrate.

According to the method of manufacturing a semiconductor chip according to the fifteenth aspect, conductive patterns such as electrodes and wirings can be collectively formed on a semiconductor substrate, and by forming an oblique surface forming an obtuse angle with the back surface, holes can be formed simultaneously. Since the inner first conductive pattern can be exposed on the slope, the number of manufacturing steps and manufacturing cost of the semiconductor chip can be significantly reduced.

According to the method of manufacturing a semiconductor chip of the present invention, since the concave portion around the surface and the side surface forming an acute angle with the front surface are formed in the semiconductor substrate, the conductive pattern is formed from the front surface and the back surface there. For example, after forming a first conductive pattern on the front surface side of a semiconductor substrate having a concave portion formed around the front surface, a second conductive pattern is formed on the back surface side having an inclined surface forming an acute angle with the front surface. In this case, the wiring can be formed so as to conduct to the surface, and the front and back conducting electrodes can be easily formed. Therefore, a multichip semiconductor chip can be easily realized.

According to the method of manufacturing a semiconductor chip according to the seventeenth aspect, it is possible to collectively form a concave portion, a conductive pattern such as an electrode and a wiring on the wafer, and form an acute angle with the front surface by forming a slope from the back surface. It is possible to simultaneously form the side surface to be formed, divide the semiconductor chip into individual pieces, and make the first conductive pattern visible from the back surface. Therefore, the number of manufacturing steps and the manufacturing cost of the multi-chip semiconductor device chip can be significantly reduced.

According to the method of manufacturing a semiconductor chip of the eighteenth aspect, in addition to the same effects as the fourteenth and sixteenth aspects, the first external electrode and the first conductive pattern can be formed at the same time. Can be reduced.

According to the method of manufacturing a semiconductor chip according to the nineteenth aspect, in addition to the same effects as those of the fourteenth and sixteenth aspects, the second external electrode and the second conductive pattern can be formed simultaneously, thereby reducing the number of manufacturing steps. Can be further reduced.

According to the twentieth aspect of the method of manufacturing a semiconductor chip, in addition to the same effects as the fifteenth and seventeenth aspects, by providing the laminated metal film in this manner, the electroplating of the conductive pattern and the conductive pattern can be performed. Can be prevented from spreading.

According to the method of manufacturing a semiconductor chip according to the twenty-first aspect, in addition to the same effects as the fifteenth, seventeenth, and twentieth aspects, the fourth resin layer is formed using a liquid resin. Thereby, the thickness of the resin formed on the slope can be sufficiently ensured, and the conductive pattern can be protected from external impact. In addition, by dividing the resin-coated portion by dicing, the resin can absorb mechanical and thermal shocks caused by cutting resistance and the like at the time of dicing. From the state where various films are formed on the entire surface of the semiconductor chip, the semiconductor chip can be processed at high speed and in a stable state.

According to the method of manufacturing a semiconductor chip of the twenty-second aspect, in addition to the same effects as the fifteenth and seventeenth aspects, the slope can be easily formed in a short time and the first aspect can be formed.
Can be exposed.

According to the method of manufacturing a semiconductor chip of the twenty-third aspect, in addition to the same effect as the fifteenth aspect, the seventeenth aspect or the twentieth aspect, a third insulating layer is formed on the entire surface of the second surface and the slope. After the formation, when opening the third insulating layer by etching to expose the first conductive pattern,
Since the third insulating layer can be selectively etched and opened without substantially etching the first insulating layer, the first insulating layer that insulates the first conductive pattern from the semiconductor substrate is partially removed. It won't. Claim 2
According to the method of manufacturing a semiconductor chip described in Item 4,
In addition to the same effects as described above, grooves can be formed in a batch in a short time in a wafer state, and the number of manufacturing steps and manufacturing costs can be reduced.

According to the method of manufacturing a wiring board according to the twenty-fifth aspect, since the hole is made to penetrate by forming the slope from the back surface of the wiring board, the processing time of the hole can be shortened and the processing cost can be reduced. .

According to the method of manufacturing a wiring board according to the twenty-sixth aspect, there is provided a first conductive pattern for mounting and wiring electronic components on the front surface and a second conductive pattern having electrodes for mounting on the motherboard on the rear surface. Then, a wiring substrate made of silicon is obtained in which the first conductive pattern and the second conductive pattern are electrically connected by the third conductive pattern formed on the side surface. Further, it is possible to easily realize a multi-chip semiconductor wiring substrate having a front electrode and a back electrode electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface. Further, after the step of forming the first conductive pattern, a step of dividing the silicon wafer into individual silicon substrates to form side surfaces is performed, and thereafter, a step of forming a second conductive pattern and a step of forming the third conductive pattern Since the step of forming the substrate is performed simultaneously, the number of manufacturing steps can be reduced. According to the method of manufacturing a wiring board according to claim 27, the first conductive pattern is provided on the front surface and the second conductive pattern is provided on the back surface, and the first conductive pattern and the second conductive pattern are directly electrically connected. A wiring substrate made of connected silicon is obtained. Further, since the concave portion and the side surface forming an acute angle with the front surface are formed in the wiring substrate, it is possible to form a wiring that conducts between the front and back surfaces only by forming a conductive pattern from the front surface and the back surface. Further, it is possible to easily realize a multi-chip semiconductor wiring substrate having a front surface electrode and a back surface electrode which are electrically connected from a silicon substrate in a wafer state via a conductive pattern passing through a side surface.

According to the method of manufacturing a wiring board according to the twenty-eighth aspect, in addition to the same effects as the twenty-fifth or twenty-seventh aspects, a liquid resin is supplied on a slope, and the cured resin portion is diced into substrate pieces. By dividing, resin absorbs mechanical interference generated by cutting resistance at the time of dicing and distortion due to frictional heat, and can prevent problems such as chipping.

According to the method of manufacturing a wiring board according to the twenty-ninth aspect, in addition to the same effects as those of the twenty-fifth or twenty-seventh aspects, the stress due to a temperature change generated between the semiconductor chip and the wiring board can be reduced. Therefore, the mounting reliability of the semiconductor chip can be improved.

According to the semiconductor device of the thirtieth aspect, the semiconductor chip having the first external electrode and the second external electrode connected via the conductive pattern formed on the inner wall and the slope of the through hole is laminated. Thus, a semiconductor device in which the semiconductor chips are electrically connected to each other via the electrodes on both surfaces thereof is obtained. Since the semiconductor chips are not arranged in a plane on the wiring board, the mounting area can be reduced. Further, since there is no need to provide electrodes for connecting metal wires, two or more semiconductor chips of the same size and different sizes can be stacked in a desired order, and the wiring length between the semiconductor chips can be increased. , And the thickness of the stacked layers can be reduced, and a semiconductor device corresponding to miniaturization, high density, and high speed can be realized.

According to the semiconductor device of the thirty-first aspect, the mounting area is reduced, the wiring length between the semiconductor chips is reduced,
A multi-chip type semiconductor device with a low stacking height, small size, high density, and high speed can be realized.

According to the semiconductor device of the thirty-second aspect, a semiconductor chip having a first external electrode and a second external electrode connected via a conductive pattern is stacked, and the first external electrode and the second external electrode are stacked. Since each semiconductor chip is electrically connected via external electrodes, the mounting area is small and semiconductor chips of the same size can be stacked without arranging multiple semiconductor chips on the wiring board in a plane. In addition, semiconductor chips of different sizes can be stacked in a desired order, the wiring length between the semiconductor chips is short, the stacking height is low, and the number of stacked semiconductor chips is two or more. Thus, a multi-chip semiconductor device that is small, high-density, and high-speed can be realized. Further, since the semiconductor substrate has a slope formed at an acute angle with the surface and a concave portion formed around the surface, the semiconductor chip can be easily manufactured.

According to the semiconductor device of the thirty-third aspect, in addition to the same effects as the thirty-second aspect, the semiconductor chips are connected to each other in a plane of the semiconductor chip such that the wiring length is short and the stacking height is low. The obtained multi-chip semiconductor device is obtained. Therefore, it is possible to realize a small-sized, high-density, high-speed multi-chip semiconductor device having a small mounting area, a short wiring length between semiconductor chips, a low stacking height.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 4 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor chip according to the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 7 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 8 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 9 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 10 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 11 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 12 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor chip according to the first embodiment of the present invention.

FIG. 14 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 15 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 16 is a sectional view illustrating a manufacturing step of the semiconductor chip according to the first embodiment of the present invention;

FIG. 17 is a sectional view showing a semiconductor chip according to a second embodiment of the present invention.

FIG. 18 is a sectional view showing a semiconductor chip according to a third embodiment of the present invention.

FIG. 19 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 20 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 21 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 22 is a sectional view of a wiring board according to a seventh embodiment of the present invention.

FIG. 23 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 24 is a plan view showing each step of the method for manufacturing a wiring board of the present invention.

FIG. 25 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 26 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 27 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 28 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 29 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 30 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 31 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 32 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 33 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 34 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 35 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 36 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 37 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 38 is a cross-sectional view of each step of the method for manufacturing a wiring board of the present invention.

FIG. 39 is a sectional view of a wiring board according to an eighth embodiment of the present invention.

FIG. 40 is a sectional view of a semiconductor device using a wiring substrate according to a ninth embodiment of the present invention.

FIG. 41 is a sectional view of a semiconductor device using a wiring board according to a tenth embodiment of the present invention.

FIG. 42 is a sectional view of a multichip semiconductor device according to an eleventh embodiment of the present invention.

FIG. 43 is a sectional view of a multichip semiconductor device according to a twelfth embodiment of the present invention.

FIG. 44 is a process sectional view illustrating the method for forming the surface of the chip for a multi-chip semiconductor device according to the thirteenth embodiment of the present invention;

FIG. 45 is a process sectional view of the first half showing the method of forming the back surface of the chip for a multi-chip semiconductor device according to the thirteenth embodiment of the present invention;

FIG. 46 is a process sectional view of the latter half showing the method of forming the back surface of the chip for a multi-chip semiconductor device according to the thirteenth embodiment of the present invention;

FIG. 47 (a) is a plan view showing a method for forming a concave portion of a chip for a multichip semiconductor device according to a thirteenth embodiment of the present invention, and FIG.

FIG. 48 is a process sectional view illustrating the method of manufacturing the semiconductor chip in the multi-chip semiconductor device according to the fourteenth embodiment of the present invention.

FIG. 49 is a cross-sectional view showing a case where a bevel cut line is shifted.

FIG. 50 is a perspective view showing another method for forming the concave portion.

FIG. 51 is a sectional view of a multichip semiconductor device according to a fifteenth embodiment of the present invention.

FIG. 52 is a cross-sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to a sixteenth embodiment of the present invention.

FIG. 53 is a cross-sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to a seventeenth embodiment of the present invention.

FIG. 54 is a cross-sectional view of a multi-chip semiconductor device using a silicon wiring substrate according to an eighteenth embodiment of the present invention.

FIG. 55 is a process sectional view illustrating the method for manufacturing the wiring substrate for a multichip semiconductor device of the nineteenth embodiment of the present invention.

FIG. 56 is a process sectional view after FIG. 55;

FIG. 57 is a process sectional view after FIG. 56;

FIG. 58 is a plan view illustrating a method of forming a concave portion in a multi-chip semiconductor device chip according to a nineteenth embodiment of the present invention.

FIG. 59 is a process sectional view illustrating the method for manufacturing the wiring substrate for a multi-chip semiconductor device of the twentieth embodiment of the present invention.

FIG. 60 is a cross-sectional view showing a conventional semiconductor device.

FIG. 61 is a cross-sectional view showing a conventional semiconductor device.

FIG. 62 is a cross-sectional view showing a conventional semiconductor device.

FIG. 63 is a cross-sectional view showing a conventional semiconductor device.

FIG. 64 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Semiconductor chip 3 Metal bump 4 Wiring board 5 Semiconductor chip 6 Metal wire 7 Semiconductor chip 8 Metal bump 9 Semiconductor chip 10 Metal bump 11 Wiring board 12 Metal bump 13 Semiconductor substrate 14 First surface 15 Slope 16 Through hole 17 Second surface 18 Surface electrode 19 Conductive pattern 20 First insulating layer 21 First external electrode 22 Second external electrode 23 Second insulating layer 24 Connecting member 25 Surface insulating layer 26 Hole 27 First laminated metal film 28 first conductive pattern 29 plating resist 30 adhesive 31 support body 32 third insulating layer 33 second laminated metal film 34 second conductive pattern 35 plating resist 36 fourth insulating layer 37 scribe line 38 side surface 39 semiconductor Chip 40 Insulating resin layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 25/07 H01L 21/88 J 25/18 (31) Priority claim number Japanese Patent Application No. 2000-350977 (P2000- (350977) (32) Priority date November 17, 2000 (November 17, 2000) (33) Priority claiming country Japan (JP) F-term (reference) 5F033 HH07 HH08 HH11 HH13 HH14 HH18 HH19 HH20 HH23 JJ07 JJ08 JJ11 JJ13 JJ14 JJ18 JJ19 JJ20 JJ23 KK07 KK08 KK11 KK13 KK14 KK18 KK19 KK20 KK23 MM05 MM13 MM30 NN05 NN07 PP06 PP15 PP19 PP20 PP27 QQ00 QQ07 QQ08 QQ10 QQ13 QQ19 QQ35 QQRR RRQQRR XX19 XX28 XX33 XX34

Claims (33)

[Claims] A semiconductor substrate; a first external electrode formed on a first surface of the semiconductor substrate; a second external electrode formed on a second surface of the semiconductor substrate; A through hole formed in the semiconductor chip,
The through hole is provided on a slope formed such that an inner angle with the second surface is formed at an obtuse angle, and the first external electrode and the second external electrode form an inner wall of the through hole and the slope. A semiconductor chip which is electrically connected by a conductive pattern formed through the semiconductor chip. 2. A semiconductor chip having a semiconductor substrate, a surface electrode formed on a first surface of the semiconductor substrate, and a through-hole formed in the semiconductor substrate, wherein the through-hole is formed of a second electrode. A first insulating surface formed on an inclined surface formed at an obtuse angle with the surface, the first surface excluding the surface electrode, the inner wall of the through hole, the inclined surface, and the second surface; A layer, a conductive pattern filled in the through-hole and formed on the first insulating layer and the surface electrode, and a part of the surface of the conductive pattern on the first surface as a first external electrode. And a second insulating layer formed by opening a part of the surface of the conductive pattern on the second surface as a second external electrode. 3. A device having a surface on which elements are integratedly formed, a back surface facing in parallel with the front surface, a slope formed at an acute angle with the front surface, and a concave portion formed around the front surface and continuous with the slope. A semiconductor chip made of a semiconductor substrate, comprising: a first electrode formed on the front surface; a second electrode formed on the back surface; and a first electrode formed in the recess and on the slope. A semiconductor chip having a conductive pattern for connecting the second electrode and the second electrode. 4. A surface on which elements are integratedly formed, a back surface facing in parallel with the front surface, a slope formed at an acute angle with the front surface, and a concave portion formed around the front surface and continuous with the slope surface. A semiconductor chip comprising a semiconductor substrate having a surface electrode connected to the element, a first insulating layer formed on the surface other than the inner wall of the recess and the surface electrode, and the first insulating layer A first conductive pattern formed in a desired wiring and electrode shape by burying the concave portion formed with the first insulating layer and connecting to the surface electrode on the surface on which the first insulating layer is formed; A second insulating layer formed on the front surface by opening an electrode portion by a conductive pattern, a slope portion where the first conductive pattern of the concave portion is continuously exposed to the slope on the periphery of the back surface, On the back and on the slope A third insulating layer formed by opening the slope portion where the first conductive pattern is exposed, and a first conductive layer formed on the slope on which the third insulating layer is formed and the back surface of the semiconductor chip. A second conductive pattern connected to the pattern and formed in a desired wiring and electrode shape; and a fourth conductive pattern formed on the back surface and the slope of the semiconductor chip by opening an electrode portion formed by the second conductive pattern. A semiconductor chip comprising an insulating layer. 5. The semiconductor chip according to claim 2, wherein a laminated metal film is formed between the first insulating layer and the conductive pattern and between the surface electrode and the conductive pattern. 6. The semiconductor chip according to claim 2, wherein at least one of the conductive patterns is formed on a surface electrode. 7. The semiconductor chip according to claim 2, wherein a vertical side surface is formed by the insulating resin supplied on the slope. 8. The semiconductor chip according to claim 5, wherein the laminated metal film includes a barrier layer and a seed layer. 9. A wiring substrate having a base material made of silicon, wherein the wiring substrate has a plurality of through holes, a first conductive pattern is formed on a surface of the wiring substrate, and the through holes are formed by the wiring. An inner angle with the back surface of the substrate is provided on a slope formed at an obtuse angle, a second conductive pattern is formed on the back surface and the slope, and the first conductive pattern and the second conductive pattern are A wiring board, wherein the wiring board is electrically connected by third conductive patterns formed in a plurality of through holes. 10. A wiring board for a multi-chip semiconductor device in which electronic components are mounted on a wiring board and mounted on a motherboard, wherein the wiring board has a silicon substrate made of silicon, and the surface of the silicon substrate has A first conductive pattern including at least one layer for mounting and wiring the electronic component; and a second conductive pattern including at least one layer having electrodes for mounting on the motherboard on a back surface of the silicon substrate. A wiring board, wherein the first conductive pattern and the second conductive pattern are electrically connected by a third conductive pattern formed on a side surface of the silicon substrate. 11. A wiring board for a multi-chip semiconductor device in which electronic components are mounted on a wiring board and mounted on a motherboard, wherein the wiring board forms a side surface at an acute angle with the surface, and a concave portion is formed around the surface. A first conductive pattern comprising at least one layer having electrodes formed on the surface of the silicon substrate and in the recess, and formed on the back surface and the side surfaces of the silicon substrate; Connecting to the first conductive pattern,
A second conductive pattern including at least one layer having electrodes. 12. The wiring substrate according to claim 9, wherein an insulating layer is formed on a side surface so as to be perpendicular to a surface of the substrate. 13. A method according to claim 1, further comprising:
12. The wiring board according to claim 9, wherein a low stress resin layer is provided on one or both of the second conductive pattern and the substrate. 14. A step of preparing a semiconductor substrate, a step of forming a hole in a peripheral portion of a semiconductor chip unit of the semiconductor substrate, and forming a first external electrode on a first surface of the semiconductor substrate, Forming a first conductive pattern electrically connected to the first external electrode in the hole and the first surface, and forming a slope having an obtuse internal angle with the second surface of the semiconductor substrate; And forming a second external electrode on the second surface, and forming the second external electrode and the first conductive pattern on the slope and on the second surface. Forming a second conductive pattern that is electrically connected to the semiconductor chip. 15. A step of preparing a semiconductor substrate, a step of forming a hole in a peripheral portion of a semiconductor chip unit of the semiconductor substrate, and a step of forming a hole on a first surface excluding a surface electrode of the semiconductor substrate and an inner wall of the hole. Forming a first insulating layer;
Forming a conductive pattern on the first insulating layer and filling the hole, and forming a second insulating layer having a part of the surface of the first conductive pattern opened as a first external electrode Performing the step of grinding the second surface of the semiconductor substrate to a desired thickness, and forming a slope having an obtuse internal angle with the second surface at the boundary between the semiconductor chip units on the second surface. Forming the hole on the slope and passing the hole through the slope;
Forming a third insulating layer on the surface of the first conductive pattern, forming a second conductive pattern electrically connected to the first conductive pattern on the third insulating layer, and forming the second conductive pattern on the third insulating layer. Forming a fourth insulating layer by opening a part of the surface as a second external electrode. 16. A method of manufacturing a plurality of semiconductor chips obtained from a wafer having a front surface on which elements are integrally formed and a back surface facing in parallel with the front surface, wherein a concave portion is formed around the semiconductor chip on the front surface. Forming, forming a slope forming an acute angle with the front surface on the semiconductor substrate, forming a first external electrode on the front surface, forming a second external electrode on the back surface, Forming a first conductive pattern connected to the first external electrode in the concave portion and on the front surface, and connecting the second external electrode and the first conductive pattern on the inclined surface and the back surface; Forming a second conductive pattern. 17. A method for manufacturing a plurality of semiconductor chips obtained from a wafer having a front surface on which elements are integrally formed and a back surface facing in parallel with the front surface, wherein a plurality of semiconductor chips are provided on a scribe line on the front surface of the wafer. Forming a concave portion around the semiconductor chip over a scribe line, forming a first insulating layer on the inner wall of the concave portion and the surface other than the surface electrode of the semiconductor chip; Forming a first conductive pattern in a desired wiring and electrode shape on the surface on which the first insulating layer is formed by burying the recess having the layer formed thereon; and forming an electrode by the first conductive pattern. Opening a portion to form a second insulating layer on the front surface, polishing the wafer to a desired thickness from the back surface, and applying the wafer to the scribe line. Forming a slope that forms an acute angle with the front surface of the semiconductor chip from the back surface along with the front surface, and exposing the first conductive pattern in the concave portion to the slope, and forming the slope on the back surface and the slope. 1
Forming a third insulating layer by opening an exposed portion of the conductive pattern; and forming the first insulating layer exposed on the inclined surface on which the third insulating layer is formed and the back surface of the semiconductor chip from the inclined surface. Forming a second conductive pattern in a shape of a desired wiring and electrode connected to the conductive pattern; Forming a fourth insulating layer. 18. A method for forming a first external electrode, comprising:
2. The step of forming a conductive pattern according to claim 1.
A method for manufacturing a semiconductor chip according to claim 4 or claim 16. 19. A method for forming a second external electrode, comprising:
2. The step of forming a conductive pattern according to claim 1.
A method for manufacturing a semiconductor chip according to claim 4 or claim 16. 20. A step of forming a first laminated metal film on the first insulating layer between a step of forming a first insulating layer and a step of forming a first conductive pattern, 16. The method according to claim 15, further comprising a step of forming a second laminated metal film on the third insulating layer between the step of forming the third insulating layer and the step of forming the second conductive pattern. A method for manufacturing a semiconductor chip according to claim 17. 21. The method of manufacturing a semiconductor chip according to claim 15, wherein the fourth insulating layer is formed by applying and curing a liquid resin, and is divided into individual semiconductor chip pieces by dicing. . 22. The step of forming a slope having an obtuse interior angle with the second surface at an end of the second surface by bevel cutting from the second surface. A method for manufacturing a semiconductor chip according to claim 15 or 17. 23. The method according to claim 15, wherein the rate at which the third insulating layer is etched is higher than the rate at which the first insulating layer and the second insulating layer are etched. 3. The method for manufacturing a semiconductor chip according to item 1. 24. The method according to claim 17, wherein the recess is a groove formed by dicing. 25. A step of forming a hole from a front surface of a silicon substrate, a step of forming a first conductive pattern in the front surface and the hole, and forming a slope having an obtuse internal angle with the back surface of the silicon substrate on the back surface. Exposing the first conductive pattern by penetrating the hole and exposing the first conductive pattern, and forming a second conductive pattern electrically connected to the first conductive pattern. Forming a wiring board on the rear surface and the slope. 26. A step of forming a first conductive pattern comprising at least one layer for mounting and wiring electronic components on a surface of a silicon wafer, and an electrode for mounting on a motherboard on a back surface of the silicon wafer. Forming a second conductive pattern comprising at least one layer, dividing the silicon wafer into individual silicon substrates to form side surfaces, and forming the first conductive pattern and the second conductive pattern. Forming a third conductive pattern to be electrically connected to the side surface, forming a first conductive pattern, and thereafter, forming a side surface by dividing the silicon wafer into individual silicon substrates. And then forming a second conductive pattern and a third step.
And a step of forming a conductive pattern according to (1). 27. A step of forming a concave portion around a surface of a silicon substrate in a wafer state, a step of forming a first conductive pattern having at least one layer having electrodes on the surface and the concave portion, Forming an inclined surface at an acute angle with the silicon substrate; forming a second conductive pattern comprising at least one layer having an electrode, electrically connected to a first conductive pattern on the back surface and the inclined surface of the silicon substrate. And manufacturing a wiring board for a multi-chip semiconductor device. 28. A method of forming an insulating layer on an inclined surface so as to be perpendicular to a surface of a silicon substrate, wherein the insulating layer is formed by applying and curing a liquid resin, and is divided into individual pieces by dicing. Claim 25 or Claim 2 characterized by the above-mentioned.
8. The method for manufacturing a wiring board for a multi-chip semiconductor device according to claim 7. 29. The method according to claim 25, further comprising the step of forming a low-stress resin layer between the substrate and the first conductive pattern or between the substrate and the second conductive pattern.
28. The method for manufacturing a wiring board according to claim 27. 30. A semiconductor substrate, and a first substrate of the semiconductor substrate.
A first external electrode formed on a surface of the semiconductor substrate, a second external electrode formed on a second surface of the semiconductor substrate, and a through hole formed on the semiconductor substrate, wherein the through hole has The second
The first external electrode and the second external electrode are provided on an inclined surface formed at an obtuse angle with the surface of the conductive member formed through the inner wall of the through hole and the inclined surface. A semiconductor device, wherein a plurality of semiconductor chips electrically connected by a pattern are stacked by electrically connecting the first external electrodes and the second external electrodes, respectively. 31. A semiconductor substrate, and a first substrate of the semiconductor substrate.
A first external electrode formed on a surface of the semiconductor substrate, a second external electrode formed on a second surface of the semiconductor substrate, and a through hole formed on the semiconductor substrate, wherein the through hole has The second
The first external electrode and the second external electrode are provided on an inclined surface formed at an obtuse angle with the surface of the first and second surfaces formed through the inner wall of the through hole and the inclined surface. A third external electrode formed in a portion of the third surface other than the element formation region between two first semiconductor chips electrically connected by the first conductive pattern, and a fourth surface thereof A second external electrode formed in a portion other than the element formation region of the second electrically conductive pattern by a second conductive pattern.
Wherein the first semiconductor chip and the second semiconductor chip are electrically connected directly or via a connection member. 32. A multi-chip semiconductor device in which a plurality of semiconductor chips each formed of a semiconductor substrate having an element integrated on a surface are stacked, wherein the stacked semiconductor chips include the front surface and the front surface. A semiconductor substrate having a back surface facing in parallel to the surface, a slope formed at an acute angle with the front surface, and a concave portion formed around the front surface, and a first external surface formed on the front surface. An electrode, a second external electrode formed on the back surface, and a conductive pattern formed in the recess and on the side surface for connecting the first external electrode and the second external electrode. And
A semiconductor device, wherein the semiconductor chip is electrically connected to another semiconductor chip via the first external electrode and the second external electrode. 33. The semiconductor device according to claim 32, wherein the stacked semiconductor chips are electrically connected to the semiconductor chips immediately above and immediately below the semiconductor chips by electrodes or directly through connection members.