JP2002217260A - Device and method for fabrication of semiconductor wafer test map chart - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for fabrication of a semiconductor wafer test MAP chart which fabricates a MAP chart by which an user can recognize the test result of a chip on a wafer visually. SOLUTION: A semiconductor wafer test MAP chart fabricating device is provided with a data processor (2) for inputting test results of each of plurality of chips on a wafer including quality data showing the quality of the chips; and a basic MAP information memory part (32) for memorizing the basic MAP information including a display device (4), the quality data of the chips corresponding to the test results, quality display information for showing the quality of the chips, and a coordinate on which chip IDs corresponding to the chips are arranged. The data processor (2) fabricates the MAP chart out of the basic MAP information and outputs it to the display device (4). In the MAP chart, the chip IDs are substituted with the quality display information based on the test results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for preparing a semiconductor wafer test MAP diagram, and more particularly to a MAP that allows a user to visually recognize the test results of chips on a wafer.
The present invention relates to a semiconductor wafer test MAP diagram creating apparatus and method for creating a diagram.

[0002]

2. Description of the Related Art Conventionally, non-defective products in a semiconductor mass production line are determined by a wafer test (a test of chips on a wafer)
And an assembling process of extracting and operating only non-defective chips after the wafer test is performed mechanically, and is automatically performed by a program of a test apparatus. As a method of discriminating a non-defective product by coordinating a wafer test and an assembling process, there is a method of sorting by electronic data or a method of directly damaging a defective chip. Here, the electronic data corresponds to the coordinates of each wafer for a plurality of wafers and the test results of the chips on each wafer. The test equipment is
A plurality of electronic data (test results) are created for a plurality of wafers by a program, and non-defective products and defective products are sorted based on the created test results. The created plurality of test results are held in the test device.

[0003]

However, there are various problems in the trial manufacture of semiconductors, and it is not possible to determine good products by such a method.

[0004] First, since a prototyper determines a non-defective product condition (for example, a standard value of a wafer) while performing a trial production, a test apparatus cannot clearly distinguish a chip into a nondefective product and a defective product. For this reason, it is difficult to automatically perform non-defective discrimination as in the related art.

[0005] Next, in the prototype stage, the prototyper needs to temporarily determine a non-defective product condition because it is necessary to temporarily consider a chip satisfying a certain condition as a non-defective product and proceed to a subsequent process. During the trial production, these non-defective products conditions are often changed depending on the situation. For this reason, it is difficult to cope with the problem with a program fixed in the test apparatus as in the related art.

[0006] Further, in the trial manufacture, the chips on the wafer are classified according to the conditions of the test result, and are sent to the process after the wafer test. For this reason, the operation of taking out chips from the wafer often depends on humans. In addition, since the work is performed manually, the prototyper must grasp additional information such as the orientation of the wafer, the name of the wafer test program, and precautions for the work, in addition to the worker who performs the test. In the past, multiple test results were simply arranged in test order,
It is difficult to know which test result is a chip from which a chip is taken out from the wafer.

In the case of a non-defective product discrimination in a mass production line, the prototyper does not need to know the program for the test apparatus, and it is sufficient if the operator (or the prototyper) who performs the test can recognize whether or not the product is non-defective. On the other hand, in the case of non-defective discrimination of a prototype, it is preferable that the prototype can visually recognize the test result of the chip on the wafer. As described above, conventionally, there is no concept of visually recognizing the test results of the chips on the wafer. MAPs that allow the user including the prototype to visually recognize the test results of the chips on the wafer without changing the program of the test apparatus for determining the non-defective product by the semiconductor mass production line.
A semiconductor wafer test MAP diagram creating apparatus for creating a diagram is desired.

An object of the present invention is to provide a semiconductor wafer test MAP diagram creating method and method for creating a MAP diagram that allows a user to visually recognize a test result of a chip on a wafer.

It is another object of the present invention to provide a semiconductor wafer test MAP diagram creating apparatus and method capable of creating a MAP diagram without changing the program of the apparatus itself in advance.

It is still another object of the present invention to provide a semiconductor wafer test MAP diagram creating apparatus and method which can easily change the conditions for discriminating non-defective products.

[0011]

Means for solving the problem are described as follows. The technical matters corresponding to the claims in the expression are appended with numbers, symbols, etc. in parentheses (). The number, symbol, etc. are at least one of a plurality of embodiments of the present invention or a plurality of embodiments.
Technical matters constituting one embodiment or a plurality of examples, in particular, reference numerals assigned to technical matters expressed in the drawings corresponding to the embodiments or examples,
It matches the reference symbol. Such reference numbers and reference symbols clearly indicate the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence / bridge does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or the examples.

According to the semiconductor wafer test MAP diagram creating apparatus of the present invention, a data processing device (2) for inputting test results of each of a plurality of chips on a wafer, and the test results are quality data indicating chip quality. And a display device (4), quality data of the chip corresponding to the test result, quality display information for indicating the quality of the chip, and coordinates at which the chip ID corresponding to the chip is arranged.
A basic MAP information storage unit (32) for storing AP information. The data processing device (2) creates a MAP diagram from the basic MAP information and outputs the MAP diagram to the display device (4). In the MAP, the chip ID is replaced with the quality display information based on the test result.

The semiconductor wafer test MAP diagram creating apparatus according to the present invention further includes a completed MAP diagram storage unit (33) for storing the MAP diagram.

The basic MAP information includes search information indicating a chip name. The data processing device (2) has a basic MAP information extraction unit (22) for extracting basic MAP information corresponding to a product name based on search information.

The data processing device (2) has a chip information collecting section (21) for inputting test results and collecting chip quality data from the test results. Further, the semiconductor wafer test MAP diagram creating apparatus according to the present invention further comprises a chip information storage unit (3) for storing collected quality data.
1) is provided.

The data processing device (2) determines the quality data of the chip included in the test result and the stored quality data, and based on the result of the determination, extracts the extracted basic MAP.
The quality indication information to be replaced is determined from the information. Thereby, in the MAP diagram, the chip ID is replaced with the quality display information based on the test result.

The quality indication information is characters including symbols, numbers and words.

According to the semiconductor wafer test MAP diagram creating method of the present invention, (a) inputting a test result including quality data indicating the quality of each of a plurality of chips on a wafer; and (b) corresponding to the test result. Storing basic MAP information including chip quality data, quality display information for indicating chip quality, and coordinates at which chip IDs corresponding to the chips are arranged; and (c) basic MA.
Creating a MAP diagram in which the chip ID is replaced with the quality indication information based on the test result from the P information;
(D) outputting a MAP diagram.

The semiconductor wafer test MAP diagram creation method according to the present invention further comprises the step of (e) storing the MAP diagram.

The basic MAP information includes search information indicating a chip name. Further, the semiconductor wafer test MAP diagram creating method according to the present invention further comprises the step of (f) extracting basic MAP information corresponding to the product name based on the search information.

The semiconductor wafer test MAP diagram creation method according to the present invention further comprises: (g) inputting a test result and collecting chip quality data from the test result.
(H) storing quality data.

According to the method of preparing a semiconductor wafer test MAP diagram according to the present invention, the step (c) further comprises the step (i)
Determining the quality data of the chip included in the test result and the stored quality data; and (j) determining quality indication information to be replaced from the extracted basic MAP information based on the result of the determination. It has.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor wafer test MAP diagram creating apparatus according to the present invention will be described below with reference to the accompanying drawings.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
1 is a block diagram showing a configuration of a semiconductor wafer test MAP diagram creating apparatus according to the present invention.

FIG. 6 shows a specific example of the basic MAP information of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

FIG. 7 is a specific example of a MAP diagram of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

As shown in FIG. 1, the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment includes an input device 1 including a keyboard and a mouse, a data processing device 2 operated by a program to be executed by a computer,
It comprises a storage device 3 for storing information, an output device 4 including a display device, a printing device, and a display device. Further, a test apparatus 100 that generates test results of a plurality of chips arranged at predetermined positions on a wafer is connected to the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

First, FIG.
This will be described with reference to FIGS.

As shown in FIG. 1, the storage device 3 includes a chip information storage unit 31, a basic MAP information storage unit 32,
And a completed MAP diagram storage unit 33.

The basic MAP information storage section 32 stores the input device 1
A basic MAP data file (hereinafter, basic MAP data) including a plurality of basic MAP information that can be easily modified / changed via the data processing device 2 by the above operation is stored in a text format. In the basic MAP data, a plurality of pieces of basic MAP information are arranged in the order of product names. The basic MAP information is electronic information corresponding to the coordinates of each wafer and the test results of chips on each wafer (a plurality of measurement results created by a program of the test apparatus 100). In the wafer test (test of chips on a wafer), a non-defective product, a non-defective product, and a defective product are determined by converting a test result of each chip into a character string called a BIN number by a program of the test apparatus 100. The BIN number is used as a condition for discriminating a non-defective product, a semi-defective product, and a defective product, and is quality data indicating the quality of the chip.

For example, there are n test items (n is an integer)
In some cases, when a certain chip clears all n-item tests, a number “B0” indicating a non-defective product is given to the basic MAP information. In this case, the number “B0” is a character string arbitrarily set by the user (prototyper or tester). Similarly, when there are n test items and a chip clears (n-1) items among the n items of tests, for example, the basic MAP information is given a number "B1" indicating a non-defective product. In this case, the number “B1” is
This is a character string arbitrarily set by the user (prototyper or operator performing the test), and is a character string indicating that only certain items of the n-item test cannot be cleared. The non-defective and semi-defective conditions are specified by the BIN number.

Here, the basic MAP information stored in the basic MAP information storage unit 32 will be described.

As shown in FIG. 6, each of the basic MAP information includes a “delimiter” area, a “article name” area, and a “non-defective BI”.
The area includes an “N designation” area, a “semi-defective BIN designation” area, a “wafer coordinate” diagram, and a “number of conforming items” area.

At the head of the basic MAP information, a "delimiter" area is arranged. The “break” area is represented by “で Applicable product name”. “＠＠” separates the product name from the next product name.

An "article name" area is arranged below the "separation" area. The “article name” area is represented by “applicable article name”. The basic MAP information shown in FIG.
The corresponding product name “aaa” is shown.

Below the "article name" area, there is an M indicating a good article.
A “non-defective BIN designation” area for designating a symbol (quality indication information for indicating the quality of a chip) on the AP diagram is arranged. The "Good BIN designation" area is "Good: MA
Symbol on P diagram: BIN number ". When the input device 1 is designated in the "non-defective BIN designation" area via the data processing device 2, the basic MAP information shown in FIG.
“Good” is shown as a non-defective product, “○” is shown as a symbol on the MAP diagram, and “B0, 2” is shown as a BIN number designation. Here, a plurality of BIN numbers can be specified by separating them with commas “,”. In this case, the designated BIN numbers are, for example, character strings B0 and B2 indicating that all test items have been cleared. Here, by specifying a plurality of character strings, the present invention can be applied to a case where test conditions are different. As described above, the BIN numbers B0 and B2 specified in the “non-defective BIN designation” area are the M indicating the non-defective product.
This means that “○” is given as a symbol on the AP diagram.

Below the "non-defective BIN designation" area, a "semi-defective BIN designation" area for designating a symbol (quality display information for indicating the quality of a chip) on a MAP diagram indicating a semi-defective product is arranged. . The "specified BIN product" area
It is represented by “Sub: symbol on MAP diagram: BIN number”. When the designation is made in the “semi-defective product BIN designation” area from the input device 1 via the data processing device 2, the basic MAP information shown in FIG. 6 includes “Sub” as the semi-defective product and “△” as the symbol on the MAP diagram. "," A
1 ", where the BIN number is a comma", "
You can specify more than one by separating with. In this case, the specified BIN number is, for example, a character string A1 indicating that a certain test item cannot be cleared. As described above, the BIN number A1 specified in the “specified non-defective product BIN specification” area
Means that “△” is given as a symbol on the MAP diagram indicating a non-defective product.

Below the area of "specified non-defective product BIN",
Another "specified non-defective product BIN" area for designating a symbol (quality indication information for indicating the quality of a chip) on the MAP diagram indicating a non-defective product is arranged. The other “specified non-defective BIN” area is represented by “Sub: Symbol on MAP diagram: BIN number”. When the data is specified from the input device 1 through the data processing device 2 to another “specified non-defective product BIN” area,
The basic MAP information shown in FIG.
"ub", "@" as a symbol on the MAP diagram, and "A0, 3" as designation of a BIN number, where a plurality of BIN numbers can be designated by separating them with a comma ",". The BIN numbers given are, for example, A0 and A3 indicating that a test item different from the test item represented by the character string A1 cannot be cleared.
The BIN numbers A0 and A3 specified in the other “specified non-defective products BIN” area mean that “◆” is given as a symbol on the MAP diagram indicating the non-defective products.

A "wafer coordinate" diagram is arranged below another "specified non-defective product BIN" area. The “wafer coordinates” diagram shows the “X” axis,
"Wafer coordinates" represented by the "Y" axis are shown.
“Wafer coordinates” corresponds to each chip arranged at a predetermined position on the wafer. In the “wafer coordinates”
In the vicinity of the “X” axis, “Wafer ID” indicating the wafer ID
Area is arranged. The “Wafer ID” area is
It is represented by “#W_no”. For example, if the wafer ID is 7, “#W_no” is represented as “7”. In “coordinates of wafer”, “chip ID” areas indicating chip IDs of respective chips on the wafer are arranged in ascending order. The “chip ID” area is represented by “# number”. Each chip indicated by “# number” is given by the data processing device 2 a symbol (quality indication information for indicating the quality of the chip) on the MAP diagram indicating one of a non-defective product, a non-defective product, and a defective product. .

Below the "wafer coordinates" diagram, a "non-defective number" area is arranged. The "Number of good products" area
It is represented by “Good: # GP / 69”. The basic MAP information shown in FIG. 6 indicates that the number of non-defective “Good” out of “69” chips is “#GP” (number).

Below the "number of non-defective products" area, another "separation" area is arranged. Basic MA shown in FIG.
In the P information, the corresponding product name “bbb” is shown. The basic MAP information indicated by the corresponding product name “bbb” is different from the basic MAP information indicated by the corresponding product name “aaa”,
＠ ”.

As shown in FIG. 1, the chip information storage unit 31 stores the above-mentioned BIN number from the data processing device 2,
A symbol (quality indication information for indicating the quality of the chip) on the MAP diagram indicating a non-defective product or a semi-defective product corresponding to the BIN number is stored.

The completed MAP diagram storage section 33 stores a MAP diagram file (hereinafter referred to as a MAP diagram) created by the data processing device 2 based on the basic MAP information shown in FIG.
The completed MAP diagram storage unit 33 stores MAP diagrams of a plurality of wafers. The stored MAP of the wafer is taken out through the data processing device 2 by operating the input device 1.

Here, the MAP diagram stored in the completed MAP diagram storage section 33 will be described.

As shown in FIG. 7, in each MAP diagram,
The area includes a “file” area, a “non-defective BIN designation” area, a “semi-defective BIN designation” area, a “wafer coordinate” diagram, and a “non-defective number” area. The layout of each MAP diagram area
It corresponds to the area of the same name in the basic MAP information described above.

At the top of the MAP diagram, a "file" area is arranged. In the “file” area, a file name is given by the user. This MAP diagram is a file created by the data processing device 2 by selecting one piece of basic MAP information from among a plurality of pieces of basic MAP information and based on the selected basic MAP information.

Below the "file" area, a "non-defective BIN designation" area for designating a symbol (quality indication information for indicating the quality of a chip) on a MAP diagram indicating a non-defective item is arranged. The "Good BIN designation" area is "Good:
Symbol on MAP diagram: BIN number ". In the MAP diagram shown in FIG. 7, "Good"
"O" as a symbol on the figure and "B" as a BIN number designation
0, 2 ". This BIN number corresponds to the BIN number of" specify good BIN "in the basic MAP information described above.

Below the "non-defective BIN designation" area, a "semi-defective BIN designation" area for designating a symbol (quality display information for indicating the quality of a chip) on a MAP diagram indicating a semi-defective product is arranged. . The "specified BIN product" area
It is represented by “Sub: symbol on MAP diagram: BIN number”. In the MAP diagram shown in FIG. 7, "Su"
"b", "@" as a symbol on the MAP diagram, and "A1" as the designation of the BIN number.
The BI of the "semi-defective BIN designation" of the basic MAP information described above
Corresponds to N number.

Below the area of “specified non-defective product BIN”,
Another "specified non-defective product BIN" area for designating a symbol (quality indication information for indicating the quality of a chip) on the MAP diagram indicating a non-defective product is arranged. The other “specified non-defective BIN” area is represented by “Sub: Symbol on MAP diagram: BIN number”. In the MAP diagram shown in FIG. 7, “Sub” as a non-defective product, “Δ” as a symbol on the MAP diagram, and B
“A0, 3” is indicated as the designation of the IN number. This BIN number corresponds to the BIN number of “specified non-defective product BIN” in the basic MAP information described above.

Below the other “specified non-defective product BIN” area, a “wafer coordinate” diagram is arranged. The “wafer coordinates” diagram shows the “X” axis,
"Wafer coordinates" represented by the "Y" axis are shown.
“Wafer coordinates” corresponds to each chip arranged at a predetermined position on the wafer. In the “wafer coordinates”
In the vicinity of the “X” axis, “Wafer ID” indicating the wafer ID
Area is arranged. In the “wafer ID” area of the MAP diagram shown in FIG. 7, “7” indicating that the wafer ID is 7 is displayed. “Wafer coordinates”
"Chip ID" indicating the chip ID of each chip on the wafer
The areas are arranged in ascending order. Each chip indicated in the “chip ID” area is given a symbol (quality indication information for indicating the quality of the chip) on the MAP diagram indicating any of a non-defective product, a non-defective product, and a defective product by the data processing device 2. Have been.

Below the “wafer coordinates” diagram, a “non-defective number” area is arranged. “Good: 12/69” is represented in the “number of good products” area of the MAP diagram shown in FIG. Thus, the MAP diagram shown in FIG. 7 indicates that there are "12" non-defective "Good" chips out of "69" chips.

Next, the data processing device 2 will be described with reference to FIG.

As shown in FIG. 1, the data processing device 2
Is a chip information collecting unit 21 and a basic MAP information extracting unit 2
2 and a MAP diagram creating unit 23.

The chip information collecting section 21
A plurality of measurement result files (or log files) created by the program No. 0 are input and stored.
The chip information collecting unit 21 searches for a log file based on the measurement result file name (log file name) of each wafer specified by the input device 1 and extracts (collects) only chip test result information from the log file. Chip information is created based on the collected test result information and stored in the chip information storage unit 31. Further, the chip information collecting unit 21 outputs the collected test result information, the generated chip information, and the like to the output device 4. The output device 4 displays or outputs the collected test result information, the created chip information, and the like.

The input device 1 stores log files (chip IDs arranged in test order, BIN numbers corresponding to chip IDs, BI
(Including a comment corresponding to the N number), input information including the lot number attached to the product name, the wafer ID corresponding to the lot number, the product name, and the log file name is specified. The input device 1 can specify a plurality of pieces of input information for a plurality of log files stored by the chip information collecting unit 21. The chip information collecting unit 21 inputs a plurality of pieces of input information from the input device 1.

The chip information collecting section 21 performs a chip information creating process on the input information according to the program. Chip information collection unit 21 that performs chip information creation processing
Is based on the log file name from the input device 1,
Search for files, and among the found log files,
Test result information including chip IDs arranged in the test order and BIN numbers corresponding to the chip IDs is collected. At this time, the collection of the basic MAP information by the chip information collection unit 21 is a copy, and the contents of the log file are not changed. Further, based on the collected test result information, the chip information collecting unit 21 specifies a designated lot number, a wafer ID corresponding to the designated lot number, a chip ID arranged in a test order corresponding to the wafer ID, Chip information including a BIN number corresponding to the chip ID is created, and the created chip information is stored in the chip information storage unit 31.

A plurality of pieces of input information specified by the input device 1 are sequentially input to the basic MAP information extracting unit 22 via the chip information collecting unit 21. Basic MAP information extraction unit 22
Stores a plurality of pieces of input information input in order, and extracts the first piece of input information from the plurality of pieces of stored input information. This basic MAP information extraction unit 22
A basic MAP information search / extraction process is performed on input information according to a program.

The basic MAP information extracting unit 22 for performing the basic MAP information search / extraction process is based on the product name of the input information specified by the input device 1 and based on the product name specified by the basic MAP information storage unit 32. The MAP information is retrieved, and only the basic MAP information to be used is extracted as a temporary file (temporary MAP file), and the extracted temporary MAP file is supplied to the MAP diagram creating unit 23.
The basic MAP information extracting unit 22 checks whether or not there is unprocessed input information based on the control signal from the MAP diagram creating unit 23. As a result of the examination, if there is unprocessed input information, the basic MAP information extraction unit 22 extracts the first input information from the stored plurality of input information, and To perform basic MAP information search and extraction processing. The basic MAP information search / extraction process is performed on all input information specified by the input device 1. Further, the basic MAP information extraction unit 22 outputs the extracted temporary MAP file and the like to the output device 4. The output device 4 displays or outputs the extracted temporary MAP file or the like.

The MAP diagram creating section 23 performs a MAP diagram creating process using the temporary MAP file extracted by the basic MAP information extracting section 22 according to a program.
The MAP diagram creation unit 23 that performs the MAP diagram creation process extracts the chip information from the chip information storage unit 31 and the basic MAP information from the basic MAP information storage unit 32. A defective product is determined, and a symbol (quality display information for indicating the quality of a chip) on the MAP diagram is determined based on the result of the determination. Next, the determined symbol of each chip is replaced on each chip layout of the temporary MAP file supplied from the basic MAP information extraction unit 22.

The determination of non-defective, semi-defective and defective products of each chip is based on the BIN corresponding to the chip ID included in the chip information.
This is performed depending on whether the number matches the BIN number of the basic MAP information. For example, the chip I included in the chip information
When the BIN number corresponding to D is “B0” indicating a non-defective product,
Since it matches the BIN number indicating a non-defective product in the basic MAP information shown in FIG. 6, the "chip ID" is used as shown in FIG.
The area is given (decided) by a symbol “○” on the MAP diagram indicating a non-defective product. The BIN number corresponding to the chip ID included in the chip information indicates “A1” indicating a non-defective product.
In this case, since the BIN number of the basic MAP information shown in FIG. 6 matches the BIN number indicating a non-defective product, as shown in FIG. Is given (determined). Further, the BIN number corresponding to the chip ID included in the chip information is a BIN number indicating a non-defective product and a non-defective product of the basic MAP information shown in FIG.
If the numbers do not match, a symbol “x” on the MAP diagram indicating a defective product is given (determined) to the “chip ID” area as shown in FIG. Thus, MA
The P diagram creator 23 determines non-defective, non-defective, and defective products of each chip, and shows M, which indicates non-defective, semi-defective, and defective products, in the “chip ID” area of the MAP diagram of the extracted basic MAP information.
Determine the symbol on the AP diagram.

By performing these processes for all the chips on each wafer, the MAP diagram creating section 23 determines that the chip ID indicates a non-defective, semi-defective, or defective product based on the test result. A MAP diagram replaced with (quality display information for indicating the quality of the chip) is created (completed), and the completed MAP diagram is stored in the MAP diagram storage unit 33. Further, the MAP diagram creating unit 23 notifies the basic MAP information extracting unit 2 that the MAP diagram corresponding to the temporary MAP file supplied from the basic MAP information extracting unit 22 is completed.
MAP information extraction unit 2 transmits a control signal for notifying
Send to 2. The MAP diagram creation processing is performed on all temporary MAP files corresponding to all input information specified by the input device 1. In addition, the MAP diagram creating unit 23 outputs the created MAP diagram and the like to the output device 4. The output device 4
The created MAP diagram or the like is displayed or output.

Thus, according to the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment, the user creates the MAP diagram from the test results of the chips on the wafer so that the user can obtain the test results of the chips on the wafer. Visually recognizable. Further, the semiconductor wafer test M according to the first embodiment
According to the AP diagram creating apparatus, the user can visually recognize the test result of the chip on the wafer by setting the result to a condition indicating a good product or a non-defective product. Further, according to the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment, it is possible to create a MAP diagram even when the condition of a good product or a semi-good product changes. In this case, the user only needs to correct or change the contents of the basic MAP information storage unit 32.

Next, the operation of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment will be described in detail with reference to FIG.

FIG. 2 is a flowchart showing the operation of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

As shown in FIG. 2, the input device 1 is a log file stored in the chip information collection unit 21 of the data processing device 2 (chip I in the test order).
D, a BIN number corresponding to the chip ID, a comment corresponding to the BIN number, etc.), input information including the lot number assigned to the product name, the wafer ID corresponding to the lot number, the product name, and the log file name. specify. The input device 1 can specify a plurality of pieces of input information for a plurality of log files stored by the chip information collecting unit 21. The chip information collecting unit 21 inputs a plurality of pieces of input information from the input device 1 (Step A1).

Next, the chip information collecting section 21 performs a chip information creating process on the input information. The chip information collecting unit 21 searches for a log file based on the log file name from the input device 1 and includes, in the searched log files, chip IDs arranged in a test order and BIN numbers corresponding to the chip IDs. Collect test result information. Based on the collected test result information, the chip information collecting unit 21 specifies a designated lot number, a wafer ID corresponding to the designated lot number, a chip ID arranged in a test order corresponding to the wafer ID, and a chip ID. Is created, and the created chip information is stored in the chip information storage unit 31 (step A).
2).

Next, a plurality of pieces of input information specified by the input device 1 are sequentially input to the basic MAP information extracting unit 22 of the data processing device 2 via the chip information collecting unit 21.
The basic MAP information extracting unit 22 stores a plurality of pieces of input information that are sequentially input, and extracts the first piece of input information from the plurality of pieces of stored input information (step A3).

Next, the basic MAP information extraction unit 22 performs a basic MAP information search / extraction process on the extracted input information. The basic MAP information extracting unit 22 searches the basic MAP information storage unit 32 for basic MAP information corresponding to the specified product name, based on the product name of the input information specified by the input device 1, and searches only the basic MAP information to be used. Is extracted as a temporary file (temporary MAP file), and the extracted temporary MAP file is
(Step A4).

Next, the MAP diagram creation section 23 of the data processing device 2 performs a MAP diagram creation process using the extracted temporary MAP file. The MAP drawing section 23 extracts chip information from the chip information storage section 31 and basic MAP information from the basic MAP information storage section 32, and outputs the chip ID.
In order, determine the non-defective, semi-defective and defective products of each chip.
A symbol (quality display information for indicating the quality of a chip) on the MAP diagram is determined based on the result of the determination. Next, the determined symbol of each chip is replaced on each chip layout of the temporary MAP file supplied from the basic MAP information extraction unit 22. The MAP drawing section 23 completes the MAP drawing of one wafer by performing the processing for all the chips on the wafer, and stores the completed MAP drawing in the MAP drawing storage section 33 (step A5).

Next, the MAP diagram creating section 23 sends the basic MAP
A control signal for notifying the basic MAP information extracting unit 22 that the MAP diagram corresponding to the temporary MAP file supplied from the information extracting unit 22 is completed is sent to the basic MAP information extracting unit 22. The basic MAP information extraction unit 22
Based on the control signal from the P diagram creating unit 23, it is checked whether or not there is unprocessed input information including the next input information. As a result of the check, if there is unprocessed input information (step A6-NO), the data processing device 2 causes the basic MAP information extraction unit 22 to execute steps A3, A4, MAP
Step A5 is repeated in the diagram creating unit 23. On the other hand, as a result of checking, if there is no unprocessed input information (step A6-YES), the data processing device 2 ends the processing of all input information.

Next, the operation of the chip information generating process in the chip information collecting section 21 will be described in detail with reference to FIG.

FIG. 3 is a flowchart showing the operation of the chip information creation processing in the chip information collection unit of the semiconductor wafer test MAP diagram creation apparatus according to the first embodiment.

As shown in FIG. 3, the chip information collecting unit 21 creates a temporary file for storing chip information and opens it in the write mode (step B1 in FIG. 3).

Next, the chip information collecting unit 21 obtains (inputs) input information (lot number assigned to the product name, wafer ID, product name, log file name corresponding to the lot number) from the input device 1 (step). B2).

Next, the chip information collecting unit 21 checks whether or not input information for creating chip information has been obtained from the input device 1 (step B3). As a result of checking, if the chip information has not been acquired (step B3-NO), the chip information collecting unit 21 determines in which part of the specified log file the chip test result (corresponding to the chip ID and the chip ID arranged in the test order). BIN number) is described. That is, the chip information collecting unit 21 searches for a line in the log file in which the chip test result is described (step B4).

Next, the chip information collecting unit 21 checks whether or not the described line has been searched (step B5). As a result of checking, if no search has been made (step B
5-YES), the chip information collecting unit 21 takes in the data of the test result of the chip from the row (step B).
6).

Next, the chip information collecting unit 21 checks the chip test results (chip IDs arranged in the test order, BIN numbers corresponding to the chip IDs), lot numbers, and wafer IDs.
D is written to a temporary file (step B7),
Steps B4 to B7 are repeated for the data based on the test result of the next chip.

In step B5, when all the rows of the test result have been retrieved (step B5-NO), the chip information collecting section 21 returns to step B2 and shifts to processing of the next input information.

At step B3, the chip information collecting section 21
When the processing is completed for all the input information (step B3-YES), the temporary file is closed (step B8), and the temporary file is stored in the chip information storage unit 31 (step B9).

Next, the aforementioned basic MAP information extracting unit 22
Will be described in detail with reference to FIG.

FIG. 4 is a flowchart showing the operation of the basic MAP information search / extraction process in the basic MAP information extraction unit of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

As shown in FIG. 4, the basic MAP information extracting unit 22 opens a temporary file for temporarily storing the basic MAP information of the corresponding product name in the write mode (step C1).

Next, the basic MAP information extraction unit 22 searches the basic MAP information storage unit 32 for a line of "@ (applicable product name)" (step C2).

Next, the basic MAP information extracting unit 22 checks whether or not the target product name has been searched (step C3). As a result of the check, when the chip information is found or when there is no corresponding product name (step C3-YES), the chip information collecting unit 21 closes the temporary file (step C8) and abnormally ends. At this time, the chip information collecting unit 21 outputs to the output device 4 error information indicating that the search has been performed or that there is no corresponding product name. On the other hand, if the result of the check indicates that no search has been made (step C3-N
O), the chip information collecting unit 21 selects the next line (Step C4).

Next, the chip information collecting unit 21 checks whether or not “@@ (next product name)” is present in the selected row (step C5). As a result of checking, if there is no “@ (next product name)” (step C5-NO), the chip information collecting unit 21
Saves the selected line in a temporary file (step C7) and repeats steps C4, C5 and C7 to process the next line.

At step C5, the chip information collecting section 21
When there is "@ (next product name)" in the selected line (step C5-YES), the temporary file is closed (step C6), and the basic MAP information search / extraction process ends.

Next, the operation of the above-described MAP diagram creating process in the MAP diagram creating section 23 will be described in detail with reference to FIG.

FIG. 5 is a diagram showing an M-map drawing unit of the semiconductor wafer test MAP drawing apparatus according to the first embodiment.
It is a flow chart which shows operation of AP figure creation processing.

As shown in FIG. 5, the MAP diagram creating unit 2
3 is a temporary MAP from the basic MAP information extraction unit 22.
The file is received and opened in the read / write mode (step D1).

Next, the MAP drawing section 23 sorts the data in the chip information storage section 31 by chip ID, and extracts chip information in order of chip ID (step D2).

Next, the MAP drawing section 23 starts the line with “Good” and “S” from the temporary MAP file.
ub "line, the BIN number of the non-defective product and the non-defective product and the mark on the MAP diagram are obtained (step D3), and the processing chip number variable (CHIP) is initialized to 0 (step D).
4).

Next, the MAP diagram creator 23 adds 1 to the processing chip number variable (CHIP) (step D).
5). Next, the MAP diagram creator 23 checks whether or not the added processing chip variable corresponds to the number of all chips (step D6). As a result of the check, if the chip ID does not correspond (step D6-NO), the MAP drawing section 23 determines whether or not the chip ID of the chip to be processed is a BIN number indicating a non-defective product or a non-defective product (step D7). If the result of the determination is that the BIN number indicates a non-defective product or a non-defective product (step D7-YES), the MAP diagram creator 23 checks the temporary MAP file for "# (CHIP)"("#number" shown in FIG. 6). Is given on the MAP diagram indicating a non-defective or semi-defective product (step D8), and the process returns to step D5.

On the other hand, if the result of determination is that the BIN number is not a good or semi-good product (step D7-NO), M
The AP diagram creating unit 23 outputs the “#” of the temporary MAP file.
(CHIP) "(corresponding to"# number "shown in FIG. 6) is given a symbol" x "on the MAP diagram indicating a defective product (step D8 '), and the process returns to step D5.

In step D6, if the added processing chip variable corresponds to the number of all chips (step D6-YES), the MAP diagram creator 23 ends the processing of all chip IDs and temporarily "#" In the MAP file
(Number) "is completed as a MAP diagram converted into a symbol determined by the test result of each chip.

Next, the MAP diagram creator 23 closes the temporary file (step D9), and completes the M
The AP diagram is stored in the completed MAP diagram storage unit 33 (step D10). As a result, the MAP diagram creation unit 23
The diagram creation processing ends.

Next, the operation of the above-described semiconductor wafer test MAP diagram creating apparatus according to the first embodiment will be described in detail with reference to FIGS. 12 and 13.

FIG. 12 is a diagram showing input information and Log in the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.
It is a figure showing one file and chip information.

FIG. 13 is a diagram showing input information and basic M in the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.
It is a figure showing AP information.

As shown in FIG. 12, the input device 1
“Lot No” = “AAA”, “Wafer” as input information
It is assumed that “ID” = “1”, “article name” = “aaa”, and “log file name” = “Log1”. The input information is received by the chip information collecting unit 21. The chip information collection unit 21 opens the log file “Log1”, performs the above-described chip information creation processing, and stores the chip information in the chip information storage unit 31.

As shown in FIG. 13, the basic MAP information extracting unit 22 inputs input information from the input device 1 via the chip information collecting unit 21, and performs a basic MAP information search / extraction process. Here, the processing will be briefly described. Basic MA
The P information extraction unit 22 includes a basic MAP information storage unit 32
The AP information is extracted, and a line whose head is “@aaa” is searched. The basic MAP information extraction unit 22 starts with “@a
All lines from the line “aa” to the line starting with “＠＠” in the next line are output to the temporary MAP file. next,
The basic MAP information extracting unit 22 stores the input information and the temporary M
The AP file is supplied to the MAP diagram creating unit 23. MA
The P diagram creation unit 23 performs a MAP diagram creation process based on the input information and the temporary MAP file. Here, the processing will be briefly described. The MAP diagram creating unit 23 obtains the chip information sorted by the chip ID from the chip information storage unit 31, determines the quality of each chip, determines a mark on the MAP diagram, and replaces the mark with a temporary basic MAP file. . When all the processes are completed, for example, M shown in FIG.
An AP diagram is created, and the created MAP diagram is stored in the completed MAP diagram storage unit 33.

Thus, according to the semiconductor wafer test MAP diagram creator according to the first embodiment, the user creates the MAP diagram from the test results of the chips on the wafer, so that the user can obtain the test results of the chips on the wafer. Visually recognizable. Further, the semiconductor wafer test M according to the first embodiment
According to the AP diagram creating apparatus, the user can visually recognize by setting the test result of the chip on the wafer to a condition indicating a good product or a non-defective product. Further, according to the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment, it is possible to create a MAP diagram even when the condition of a good product or a semi-good product changes. In this case, the user only needs to correct or change the contents of the basic MAP information storage unit 32.

The semiconductor wafer test MAP diagram creating apparatus according to the first embodiment is not limited to the above description. Semiconductor wafer test MA according to the first embodiment
In the P diagram creating apparatus, the number of input information and the number of designated non-defective products are not limited.
Anything other than "も の" should be used. Further, the quality display information for indicating the quality of the chip in the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment is not limited to a symbol, and may be a character including a symbol, a numeral, and a word.

As described above, the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment can create a MAP diagram that allows the user to visually recognize the test results of the chips on the wafer. The MAP diagram is created without changing the other parts because it only replaces the necessary parts of the basic MAP information. Therefore, the user can easily change the format of the output MAP diagram.

Further, the semiconductor wafer test MAP diagram creation device according to the first embodiment stores the basic MAP information and the MAP diagram independently, so that the program of the test device for discriminating non-defective products by the semiconductor mass production line can be obtained. There is no need to change the program of the data processing device 2. For this reason, the semiconductor wafer test MAP diagram creation device according to the first embodiment can create a MAP diagram without changing the program of the device itself in advance.

Further, the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment can easily change the conditions for non-defective product discrimination. As a result, the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment stores the basic MAP information and the MAP diagram independently. You only need to modify and change information. For this reason, the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment does not need to change the program of the apparatus itself beforehand, without changing the wafer conditions (test conditions,
Change of the position of the chip).

(Embodiment 2) In Embodiment 1,
According to the semiconductor wafer test MAP diagram creating apparatus, a user creates a MAP diagram from a test result of a chip on a wafer using a symbol (quality indication information for indicating the quality of a chip), thereby enabling a user to make a chip on the wafer. Can visually recognize the test results. On the other hand, in the second embodiment, the number of non-defective products is counted from the test results of the chips on the wafer, and based on the counted results, the MAP using symbols (quality indication information for indicating the quality of the chips) is obtained from the test results. Figure and B
By creating a MAP diagram using an IN number, in addition to the effects of the first embodiment, it is possible to know the details of the test results.

Semiconductor wafer test M according to the second embodiment
The AP diagram creating apparatus will be described with reference to FIG.
The basic M in the semiconductor memory device according to the second embodiment
Specific examples of the AP information and the MAP diagram are the same as those in the first embodiment, and thus description thereof will be omitted.

FIG. 8 is a block diagram showing a configuration of a semiconductor wafer test MAP diagram creating apparatus according to the second embodiment.

As shown in FIG. 8, the semiconductor wafer test MAP diagram creation device according to the second embodiment includes an input device 6 including a keyboard and a mouse, a data processing device 7 operated by a program to be executed by a computer,
It comprises a storage device 8 for storing information, an output device 9 including a display device, a printing device, and a display device. Further, a test apparatus 100 that generates test results of a plurality of chips arranged at predetermined positions on a wafer is connected to the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment.

First, the storage device 8 will be described.

The storage device 8 includes a chip information storage unit 81,
Basic MAP information storage unit 82 and completed MAP diagram storage unit 8
And a second completed MAP diagram storage unit 84.

The basic MAP information storage unit 82 stores the input device 6
A basic MAP data file (hereinafter, basic MAP data) including a plurality of basic MAP information that can be easily modified / changed via the data processing device 7 by the above operation is stored in a text format. In the basic MAP data, a plurality of pieces of basic MAP information are arranged in the order of product names. The basic MAP information is electronic information corresponding to the coordinates of each wafer and the test results of chips on each wafer (a plurality of measurement results created by a program of the test apparatus 100). In the wafer test (test of a chip on a wafer), a program of the test apparatus 100 converts a test result of each chip into a character string called a BIN number to determine a non-defective product or a non-defective product. The BIN number is used as a condition for discriminating a non-defective product, a semi-defective product, and a defective product, and is quality data indicating the quality of the chip.

The chip information storage section 81 stores the above-mentioned BIN number from the data processing device 7 and a symbol (quality display information for indicating the quality of the chip) on the MAP diagram indicating a non-defective product or a non-defective product corresponding to the BIN number. Is stored.

The completed MAP drawing storage unit 83 stores a first MA using a symbol (quality indication information for indicating the quality of a chip) created by the data processing device 7 based on the basic MAP information.
A P diagram file (hereinafter, a first MAP diagram) is stored. The completed MAP diagram storage unit 83 stores first MAP diagrams of a plurality of wafers. The first MAP of the stored wafer is taken out via the data processing device 7 by operating the input device 6.

The second completed MAP diagram storage unit 84 stores the basic MA
BIN created by data processing device 7 based on P information
2nd MAP figure file using numbers (hereinafter referred to as 2nd MAP file)
Figure) is stored. The second completed MAP diagram storage unit 84 stores the second MAP diagrams of a plurality of wafers. The stored second MAP of the wafer is taken out via the data processing device 7 by operating the input device 6.

Next, the data processing device 7 will be described.

The data processing device 7 includes a chip information collecting unit 7
1, a basic MAP information extraction unit 72, and a good product number calculation unit 74
And a MAP diagram creating unit 73 and a second MAP diagram creating unit 75.

The chip information collecting section 71 is provided for the test apparatus 10
A plurality of measurement result files (or log files) created by the program No. 0 are input and stored.
The chip information collecting unit 71 searches for a log file based on the measurement result file name (log file name) of each wafer specified by the input device 6 and extracts (collects) only the chip test result information from the log file. Chip information is created based on the collected test result information and stored in the chip information storage unit 81. Further, the chip information collecting unit 71 outputs the collected test result information, the generated chip information, and the like to the output device 9. The output device 9 displays or outputs collected test result information, created chip information, and the like.

The input device 6 stores log files (chip IDs arranged in test order, BIN numbers corresponding to chip IDs, BI
(Including a comment corresponding to the N number), input information including the lot number attached to the product name, the wafer ID corresponding to the lot number, the product name, and the log file name is specified. The input device 6 can specify a plurality of pieces of input information for a plurality of log files stored by the chip information collecting unit 71. The chip information collecting unit 71 inputs a plurality of pieces of input information from the input device 6.

The chip information collecting section 71 performs a chip information creating process for the input information according to the program. Chip information collection unit 71 that performs chip information creation processing
Is based on the log file name from the input device 6,
Search for files, and among the found log files,
Test result information including chip IDs arranged in the test order and BIN numbers corresponding to the chip IDs is collected. At this time, the collection of the basic MAP information by the chip information collection unit 71 is a copy, and the contents of the log file are not changed. Further, based on the collected test result information, the chip information collecting unit 71 includes a designated lot number, a wafer ID corresponding to the designated lot number, a chip ID arranged in a test order corresponding to the wafer ID, Chip information including a BIN number corresponding to the chip ID is created, and the created chip information is stored in the chip information storage unit 81.

A plurality of pieces of input information specified by the input device 6 are sequentially input to the basic MAP information extracting section 72 via the chip information collecting section 71. Basic MAP information extraction unit 72
Stores a plurality of pieces of input information input in order, and extracts the first piece of input information from the plurality of pieces of stored input information. This basic MAP information extraction unit 72
A basic MAP information search / extraction process is performed on input information according to a program.

The basic MAP information extraction unit 72 for performing the basic MAP information search / extraction process is based on the product name of the input information specified by the input device 6, based on the product name specified by the basic MAP information storage unit 82. The MAP information is searched, and only the basic MAP information to be used is extracted as a temporary file (temporary MAP file), and the extracted temporary MAP file is supplied to the number-of-goods calculating section 74. Further, the basic MAP information extraction unit 72 checks whether or not there is unprocessed input information based on the first control signal from the second MAP diagram creation unit 75. As a result of the examination, if there is unprocessed input information, the basic MAP information extraction unit 72 extracts the first input information from the stored plurality of input information, and To perform basic MAP information search and extraction processing. The basic MAP information search / extraction process is performed on all input information specified by the input device 6. Further, the basic MAP information extraction unit 72 outputs the extracted temporary MAP file and the like to the output device 9. The output device 9 displays or outputs the extracted temporary MAP file or the like.

The number-of-goods calculating section 74 performs a good-number calculating process using the temporary MAP file extracted by the basic MAP information extracting section 72 according to a program. The non-defective number calculation unit 74 that performs the non-defective number calculation process includes the chip information stored in the chip information
The basic MAP information is extracted from the chip information and the basic MA.
The number of non-defective products of each chip is counted based on the P information.
The non-defective item calculation unit 74 outputs the non-defective item number information to the second MAP diagram generation unit 75 via the MAP diagram generation unit 73 and the MAP diagram generation unit 73 based on the counted result.

[0124] The MAP diagram creating section 73 performs a MAP diagram creating process using the temporary MAP file extracted by the basic MAP information extracting section 72 according to a program.
The MAP diagram creation unit 73 that performs the MAP diagram creation process extracts the chip information from the chip information storage unit 81 and the basic MAP information from the basic MAP information storage unit 82. A defective product is determined, and a symbol (quality display information for indicating the quality of a chip) on the MAP diagram is determined based on the result of the determination. Next, the determined symbol of each chip is replaced on each chip layout of the temporary MAP file supplied from the basic MAP information extraction unit 72.

By performing these processes for all the chips on each wafer, the MAP drawing section 73 determines that the chip ID indicates a non-defective, semi-defective, or defective product based on the test result. A MAP diagram replaced with (quality display information for indicating the quality of the chip) is created (completed), and the completed MAP diagram is stored in the MAP diagram storage unit 83. Further, the MAP diagram creating unit 73 notifies the second MAP diagram creating unit 75 that the MAP diagram corresponding to the temporary MAP file supplied from the basic MAP information extracting unit 72 has been completed.
The second control signal for notifying the second MAP diagram creating unit 7
Send to 5. Further, the MAP diagram creating unit 73 outputs the created M
The AP diagram and the like are output to the output device 9. The output device 9 displays or outputs the created MAP diagram or the like.

The second MAP drawing section 75 receives the second control signal from the MAP drawing section 73 according to the program, and performs the second MAP drawing processing using the temporary MAP file extracted by the basic MAP information extracting section 72. . MAP diagram creator 75 for performing the second MAP diagram creation process
Is the chip information from the chip information storage unit 81 and the basic MA
The basic MAP information is extracted from the P information storage unit 82, and B indicating good, semi-defective, and defective products of each chip is arranged in the order of chip ID.
Determine the IN number. Next, the confirmed BI of each chip
The N number is replaced on each chip layout of the temporary MAP file supplied from the basic MAP information extraction unit 72. In addition, the second MAP diagram creation unit 75 receives the number of non-defective items indicating the number of non-defective items from the non-defective number calculation unit 74, and describes the non-defective number information in a temporary MAP file.

By performing these processes for all the chips on each wafer, the second MAP diagram creator 75
The second MA in which the chip ID is replaced with a BIN number indicating a non-defective product, a non-defective product, or a defective product based on the test result (here, the BIN number is quality indication information for indicating the quality of the chip).
A P diagram is created (completed), and the completed second MAP diagram is stored in the second MAP diagram storage unit 84. Further, the second MAP diagram creating unit 75 sends a first control signal for notifying the basic MAP information extracting unit 72 that the second MAP diagram corresponding to the temporary MAP file supplied from the basic MAP information extracting unit 72 is completed. It is sent to the basic MAP information extraction unit 72.
The MAP diagram creation process and the second MAP diagram creation process are performed on all temporary MAs corresponding to all the input information designated by the input device 6.
Performed on P files. Also, the MAP diagram creation unit 7
5 outputs the created second MAP diagram and the like to the output device 9. The output device 9 displays or outputs the created second MAP diagram or the like.

Thus, according to the semiconductor wafer test MAP diagram creator according to the second embodiment, the user creates the MAP diagram from the test results of the chips on the wafer, so that the user can obtain the test results of the chips on the wafer. Visually recognizable. Further, the semiconductor wafer test M according to the second embodiment
According to the AP diagram creating apparatus, the user can know the details of the test results of the chips on the wafer by creating the second MAP diagram from the test results of the chips on the wafer. Further, according to the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment, the user can visually recognize by setting the test result of the chip on the wafer to a condition indicating a non-defective product or a non-defective product. Embodiment 2
According to the semiconductor wafer test MAP diagram creating apparatus according to
It is possible to create a MAP diagram and a second MAP diagram even when the condition of a good product or a semi-good product changes. In this case, the user only needs to correct or change the contents of the basic MAP information storage unit 82.

Next, the operation of the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment will be described in detail with reference to FIG. Note that the chip information creation processing and the basic MAP in the semiconductor memory device according to the second embodiment
The information search / extraction process and the MAP diagram creation process are the same as those in the first embodiment, and thus description thereof will be omitted.

FIG. 9 is a flowchart showing the operation of the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment.

As shown in FIG. 9, the input device 6 receives the log file (the chip I arranged in the test order) stored by the chip information collecting section 71 of the data processing device 7.
D, a BIN number corresponding to the chip ID, a comment corresponding to the BIN number, etc.), input information including the lot number assigned to the product name, the wafer ID corresponding to the lot number, the product name, and the log file name. specify. The input device 6 can specify a plurality of pieces of input information for a plurality of log files stored by the chip information collecting unit 71. The chip information collecting unit 71 inputs a plurality of pieces of input information from the input device 6 (Step A11).

Next, the chip information collecting section 71 performs a chip information creating process on the input information. The chip information collecting unit 71 searches for a log file based on the log file name from the input device 6, and includes, in the searched log files, chip IDs arranged in a test order and BIN numbers corresponding to the chip IDs. Collect test result information. Based on the collected test result information, the chip information collecting unit 71 includes a designated lot number, a wafer ID corresponding to the designated lot number, a chip ID arranged in a test order corresponding to the wafer ID, and a chip ID. Is generated, and the generated chip information is stored in the chip information storage unit 81 (step A).
12).

Next, a plurality of pieces of input information specified by the input device 6 are sequentially input to the basic MAP information extracting unit 72 of the data processing device 7 via the chip information collecting unit 71.
The basic MAP information extraction unit 72 stores a plurality of input information input in order, and extracts the first input information from the stored plurality of input information (step A13).

Next, the basic MAP information extracting section 72 performs a basic MAP information search / extraction process on the extracted input information. The basic MAP information extracting unit 72 searches the basic MAP information storage unit 82 for basic MAP information corresponding to the specified product name, based on the product name of the input information specified by the input device 6, and searches only the basic MAP information to be used. Is extracted as a temporary file (temporary MAP file), and the extracted temporary MAP file is supplied to the conforming item number calculation unit 74 (step A14).

Next, the number-of-goods calculation section 7 of the data processing device 7
No. 4 performs a non-defective number calculation process using the extracted temporary MAP file. The number-of-goods calculation section 74 stores the chip information from the chip information storage section 81 and the basic MAP information storage section 8.
2 to extract chip information and basic M information.
The number of good chips is counted based on the AP information. The non-defective number calculation unit 74 converts the non-defective number information into the MAP diagram generation unit 73 and the MAP diagram generation unit
Then, the data is output to the second MAP diagram creator 75 through Step 3 (Step A15).

Next, the MAP drawing section 73 of the data processing device 7 performs a MAP drawing process using the extracted temporary MAP file. The MAP drawing section 73 extracts chip information from the chip information storage section 81 and basic MAP information from the basic MAP information storage section 82, and outputs the chip ID.
In order, determine the non-defective, semi-defective and defective products of each chip.
A symbol (quality display information for indicating the quality of a chip) on the MAP diagram is determined based on the result of the determination. Next, the determined symbol of each chip is replaced on each chip layout of the temporary MAP file supplied from the basic MAP information extraction unit 72. The MAP drawing section 73 completes the MAP drawing of one wafer by performing the processing for all the chips on the wafer, and stores the completed MAP drawing in the MAP drawing storage section 83 (step A16). Next, the MAP diagram creator 73 outputs a second control signal for notifying the second MAP diagram creator 75 that the MAP diagram corresponding to the temporary MAP file supplied from the basic MAP information extractor 72 has been completed. It is sent to the 2MAP diagram creation unit 75.

Next, the MAP drawing section 75 of the data processing device 7 receives the second control signal from the MAP drawing section 73, and performs the second MAP drawing processing using the extracted temporary MAP file. 2nd MAP diagram creation unit 75
Is the chip information from the chip information storage unit 81 and the basic MA
The basic MAP information is extracted from the P information storage unit 82, and B indicating good, semi-defective, and defective products of each chip is arranged in the order of chip ID.
Determine the IN number. Next, the confirmed BI of each chip
The N number is replaced on each chip layout of the temporary MAP file supplied from the basic MAP information extraction unit 72. In addition, the second MAP diagram creation unit 75 receives the number of non-defective items indicating the number of non-defective items from the non-defective number calculation unit 74, and describes the non-defective number information in a temporary MAP file. The MAP drawing section 73 completes the second MAP drawing of one wafer by performing the processing for all the chips on the wafer, and stores the completed second MAP drawing in the MAP drawing storage section 83 (step A17).

Next, the second MAP diagram creator 75 creates the basic M
The fact that the second MAP diagram corresponding to the temporary MAP file supplied from the AP information extraction unit 72 is completed
A first control signal for notifying the AP information extraction unit 72 is sent to the basic MAP information extraction unit 72. Based on the first control signal from the second MAP diagram creating unit 75, the basic MAP information extracting unit 72 checks whether or not there is unprocessed input information including the next input information. As a result of the examination, if there is unprocessed input information (step A18-NO), the data processing device 7 executes steps A13 and A14 in the basic MAP information extraction unit 72 and step A in the non-defective number calculation unit 74.
15. Step A16, the second M
Step A17 is repeated in the AP diagram creation section 75. On the other hand, as a result of checking, if there is no unprocessed input information (step A18-YES), the data processing device 7 ends the processing of all the input information.

Next, the operation of the above-described non-defective number calculation section 75 in the non-defective number calculation section 75 will be described in detail with reference to FIG.

FIG. 10 is a flowchart showing the operation of the non-defective number calculation process in the non-defective number calculation unit of the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment.

As shown in FIG. 10, the non-defective product number calculation section 7
5 is a temporary MAP from the basic MAP information extraction unit 22.
The file is received and opened in the write mode (step E1 in FIG. 10).

Next, the number of non-defective products calculating section 75
Chip input information from the AP file (lot number attached to product name, wafer ID corresponding to lot number, product name, l
og file name) (step E2).

Next, the non-defective number calculation section 75 initializes the non-defective number variable in the temporary MAP file (non-defective number = 0) (step E3).

Next, the number-of-goods calculating section 75 calculates the designated l
A search is made as to which part of the og file has a BIN number indicating a non-defective product in which the chip test result is described. In other words, the number of non-defective items is calculated by the non-defective item calculation unit 75 by searching the line of “Good” in which the test result of the chip in the log file is described (step E).
4).

Next, the conforming item number calculation unit 75 extracts the chip information in order of chip ID (step E5). Next, the conforming item number calculation unit 75 checks whether or not the extracted chip ID corresponds to the number of all chips (step E6). As a result of checking, if the chip ID does not correspond (step E6-NO), the conforming item number calculation unit 75 determines whether or not the chip ID is a BIN number indicating a conforming item (step E7). As a result of checking, if the BIN number indicates a non-defective product (step E7-
YES), the non-defective number calculation unit 75 adds 1 to the non-defective number variable (step E9). BIN indicating good product
If it is not a number (step E7-NO), the non-defective number calculation unit 75 returns to step E5.

Further, in step E6, the number of non-defective products
5, when the extracted chip ID corresponds to the number of all chips (step E6-YES), the temporary file is closed, and the temporary file is output to the MAP diagram creating unit 73 and the second MAP diagram creating unit 75 (step S6). E8).

Next, the operation of the second MAP diagram creation process in the second MAP diagram creation section 75 will be described in detail with reference to FIG.

FIG. 11 is a flowchart showing the operation of the second MAP diagram creation process in the second MAP diagram creation unit of the semiconductor wafer test MAP diagram creation apparatus according to the second embodiment.

As shown in FIG. 11, the second MAP diagram creator 75 sends a temporary MAP
The file is received and opened in the read / write mode (step F1).

Next, the second MAP drawing unit 75 sorts the data in the chip information storage unit 81 by chip ID, extracts chip information in order of chip ID (step F2), and sets the processing chip number variable (CHIP) to 0. initialize.

Next, the second MAP diagram creator 75 adds 1 to the processing chip number variable (CHIP) (step F).
3). Next, the second MAP diagram creator 75 checks whether or not the added processing chip variable corresponds to the number of all chips (step F4). As a result of the check, if they do not correspond (step F4-NO), the second MAP diagram creator 75
"# (CHIP)" of the temporary MAP file (FIG. 6
Non-defective, semi-defective,
It is converted into a BIN number indicating a defective product (step F5), and the process returns to step F3.

On the other hand, as a result of the check, when the added processing chip variable corresponds to the number of all chips (step F4-
YES), the second MAP diagram creator 75 outputs all the chips I
D is completed, and the temporary MAP file “#
(Number) ”is completed as the second MAP diagram converted into the BIN number determined by the test result of each chip.

Next, the second MAP diagram creating section 75 closes the temporary file and stores the completed second MAP diagram in the second completed MAP diagram storage section 84 (step F).
6). As a result, the second MAP diagram creator 75
The AP diagram creation processing ends.

Thus, according to the semiconductor wafer test MAP diagram creator according to the second embodiment, the user creates the MAP diagram from the test results of the chips on the wafer, so that the user can obtain the test results of the chips on the wafer. Visually recognizable. Further, the semiconductor wafer test M according to the second embodiment
According to the AP diagram creating apparatus, the user can know the details of the test results of the chips on the wafer by creating the second MAP diagram from the test results of the chips on the wafer. Further, according to the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment, the user can visually recognize by setting the test result of the chip on the wafer to a condition indicating a non-defective product or a non-defective product. Embodiment 2
According to the semiconductor wafer test MAP diagram creating apparatus according to
It is possible to create a MAP diagram and a second MAP diagram even when the condition of a good product or a semi-good product changes. In this case, the user only needs to correct or change the contents of the basic MAP information storage unit 82.

The semiconductor wafer test MAP diagram creating apparatus according to the second embodiment is not limited to the above description. Semiconductor wafer test MA according to the second embodiment
In the P diagram creating apparatus, the number of input information and the number of designated non-defective products are not limited.
Anything other than "も の" should be used. Further, the quality display information for indicating the quality of the chip in the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment is not limited to a symbol, but may be a character including a symbol, a numeral, and a word.

As described above, according to the semiconductor wafer test MAP diagram creator according to the second embodiment, the second MAP diagram is created from the test results of the chips on the wafer. The user can know details about the test results of the chips on the wafer.

[0157]

The semiconductor wafer test MAP diagram creating apparatus of the present invention can create a MAP diagram that allows a user to visually recognize the test results of chips on a wafer.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor wafer test MAP diagram creating apparatus according to a first embodiment;

FIG. 2 is a flowchart illustrating an operation of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment;

FIG. 3 is a flowchart illustrating an operation of a chip information creating process in a chip information collecting unit of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment;

FIG. 4 is a flowchart showing an operation of a basic MAP information search / extraction process in a basic MAP information extracting unit of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

FIG. 5 is a MAP in a MAP creating section of the semiconductor wafer test MAP creating apparatus according to the first embodiment;
It is a flowchart which shows operation | movement of a figure preparation process.

FIG. 6 is a specific example of basic MAP information of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

FIG. 7 is a specific example of a MAP diagram of the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment.

FIG. 8 is a block diagram showing a configuration of a semiconductor wafer test MAP diagram creating apparatus according to a second embodiment.

FIG. 9 is a flowchart showing an operation of the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment.

FIG. 10 is a flowchart illustrating an operation of a non-defective number calculation process in a non-defective number calculation unit of the semiconductor wafer test MAP diagram creating device according to the second embodiment;

FIG. 11 is a flowchart showing an operation of a second MAP diagram creating process in a second MAP diagram creating unit of the semiconductor wafer test MAP diagram creating apparatus according to the second embodiment.

FIG. 12 is an example of input information, Log1 in the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment;
It is a figure showing a file and chip information.

FIG. 13 is a diagram illustrating input information and a basic MA in the semiconductor wafer test MAP diagram creating apparatus according to the first embodiment;
It is a figure showing P information.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input device 2 data processing device 3 storage device 4 output device 6 input device 7 data processing device 8 storage device 9 output device 21 chip information collection unit 22 basic MAP information extraction unit 23 MAP diagram creation unit 31 chip information storage unit 32 basic MAP Information storage unit 33 Completed MAP diagram storage unit 71 Chip information collection unit 72 Basic MAP information extraction unit 73 MAP diagram creation unit 74 Number of conforming products calculation unit 75 Second MAP diagram creation unit 81 Chip information storage unit 82 Basic MAP information storage unit 83 Completed MAP Diagram storage unit 84 Second completed MAP diagram storage unit 100 Test device

Claims (11)

[Claims] A data processing device for inputting test results of each of a plurality of chips on a wafer;
A display device, the quality data of the chip corresponding to the test result, quality display information for indicating the quality of the chip, and a chip ID corresponding to the chip. And a basic MAP information storage unit for storing basic MAP information including the arranged coordinates, wherein the data processing device performs MAP based on the basic MAP information.
A semiconductor wafer test MAP diagram creating apparatus in which a diagram is created and the MAP diagram is output to the display device, and in the MAP diagram, the chip ID is replaced with the quality display information based on the test result. 2. The semiconductor wafer test M according to claim 1, wherein:
A semiconductor wafer test MAP diagram creating apparatus, further comprising a completed MAP diagram storage unit for storing the MAP diagram. 3. The semiconductor wafer test MAP diagram creating device according to claim 1, wherein the basic MAP information includes search information indicating a product name of the chip, and the data processing device is configured to execute a search based on the search information. A basic MA for extracting the basic MAP information corresponding to the product name.
A semiconductor wafer test MAP diagram creating apparatus having a P information extracting unit. 4. The semiconductor wafer test MAP diagram creating apparatus according to claim 1, wherein said data processing apparatus inputs said test result, and said quality data of said chip is obtained from said test result. A semiconductor wafer test MAP diagram creating device, comprising: a chip information collecting unit for collecting the quality data; and a chip information storing unit for storing the collected quality data. 5. The semiconductor wafer test M according to claim 4, wherein
In the AP diagram creating device, the data processing device determines the quality data of the chip included in the test result and the stored quality data, and based on the determination result, the extracted basic MAP A semiconductor wafer test MAP diagram creating apparatus for determining the quality indication information to be replaced from information. 6. The semiconductor wafer test MAP diagram creating apparatus according to claim 1, wherein the quality indication information is a character including a symbol, a number, and a word. . 7. A step of: (a) inputting a test result including quality data indicating quality of each of a plurality of chips on a wafer; (b) said quality data of said chip corresponding to said test result; Storing basic MAP information including quality display information for indicating the quality of the chip and coordinates at which a chip ID corresponding to the chip is arranged; and (c) storing the chip ID from the basic MAP information.
Creating a MAP diagram in which is replaced with the quality indication information based on the test result; and (d) the MA
And a step of outputting a P diagram. 8. The semiconductor wafer test M according to claim 7,
The method for creating an AP diagram, further comprising: (e) storing the MAP diagram. 9. The method for creating a semiconductor wafer test MAP diagram according to claim 7, wherein the basic MAP information includes search information indicating a product name of the chip, and (f) based on the search information. A method for creating a semiconductor wafer test MAP diagram, further comprising a step of extracting the basic MAP information corresponding to a product name. 10. The semiconductor wafer test MAP diagram creation method according to claim 7, wherein:
(G) inputting the test result and collecting the quality data of the chip from the test result;
And (h) storing the quality data. 11. The semiconductor wafer test MAP diagram creating method according to claim 10, wherein the step (c) comprises: (i) the quality data of the chip and the stored quality data included in the test result. And (j) determining the quality indication information to be replaced from the extracted basic MAP information based on the result of the determination.