CN117976567A - Processing method and equipment for double-core continuous scribing MAP (MAP) slice-taking product - Google Patents

Processing method and equipment for double-core continuous scribing MAP (MAP) slice-taking product Download PDF

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Publication number
CN117976567A
CN117976567A CN202410383394.7A CN202410383394A CN117976567A CN 117976567 A CN117976567 A CN 117976567A CN 202410383394 A CN202410383394 A CN 202410383394A CN 117976567 A CN117976567 A CN 117976567A
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map
bin
column
double
core
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CN117976567B (en
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闵卫涛
陈宏明
孙文强
唐明波
王昱琮
李建明
杜文康
汪文博
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Huayi Microelectronics Co ltd
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Huayi Microelectronics Co ltd
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Abstract

The invention discloses a processing method of a double-core continuous scribing MAP (MAP) chip taking product, which comprises the following steps: performing double-core dicing on the blind sealing wafer of the target chip by using a dicing saw according to the chip size in a dicing process, and providing a first MAP of the blind sealing wafer; acquiring information of a first MAP, and converting and combining the MAP according to the information of the first MAP to obtain a second MAP; and (3) the upper core uses the generated second MAP, and the chip position and the second MAP position are calibrated after corresponding, and the processing can be performed after the calibration is completed. The method can convert the single chip MAP of the double-core continuous scribing wafer into the MAP graph of the double-core continuous scribing, can solve the problem that the double-core continuous scribing product can only be subjected to blind sealing under the condition of the MAP graph, effectively solves the yield loss caused by manual dotting in blind sealing and taking, reduces material waste, and greatly improves the equipment utilization rate and the product packaging yield.

Description

Processing method and equipment for double-core continuous scribing MAP (MAP) slice-taking product
Technical Field
The invention relates to the technical field of semiconductor device packaging, in particular to a processing method and equipment of a double-core continuous scribing MAP (MAP) chip taking product.
Background
The wafer can be cut into single-die chips, dual-die chips (dual-die bond scribe), or multi-die chips, wherein the dual-die bond scribe is a process in which the wafer cuts two chips into a single chip. The chip packaging process comprises three modes of blind packaging, ink dot and MAP chip taking.
When MAP is taken, each chip of the wafer needs to be tested before leaving a factory or scribing the wafer, an MAP graph is generated through testing the wafer, characters are used for replacing the chips in the MAP graph, each character represents each chip on the corresponding wafer, a common double-core continuous scribing product is double (double-core continuous scribing) when the upper chip is taken because the MAP file is a single chip, the MAP cannot be taken, blind sealing can only be carried out (the chips which are good and bad after the edge chips are manually dotted and removed are packaged simultaneously), and after packaging, the packaging materials are wasted, product breakage corners and other quality anomalies can be caused in a manual dotting link during blind sealing, the packaging yield of the product is reduced, and meanwhile, the equipment utilization rate is also reduced.
Disclosure of Invention
The invention provides a processing method and equipment of a double-core continuous scribing MAP (MAP) chip taking product, and aims to solve the problems in the prior art.
The technical scheme provided by the invention is as follows:
The invention provides a processing method of a double-core continuous scribing MAP (MAP) chip taking product, which comprises the following steps of:
s1, performing double-chip dicing on a blind sealing wafer of a target chip by using a dicing saw according to the chip size in a dicing process, and providing a first MAP of the blind sealing wafer;
S2, acquiring information of the first MAP, and converting and combining the MAP according to the information of the first MAP to obtain a second MAP, wherein the information of the first MAP comprises BIN number, chip type, notch direction, wafer number, wafer lot number and column number;
And S3, using the generated second MAP to correspond the chip position to the second MAP, calibrating, and processing after the calibration is completed.
Further, in step S2, the step of obtaining the information of the first MAP, converting and merging the MAP according to the information of the first MAP, to obtain a second MAP, includes the following steps:
S201, acquiring information of the first MAP, and displaying the information of the first MAP in a coordinate axis taking the upper left corner as an origin of coordinates, wherein each character or vacancy obtains a corresponding coordinate;
S202, acquiring MAP information to be combined in the first MAP according to a coordinate starting point and a coordinate ending point;
And S203, uniformly rotating the directions of the double-core streets of the wafer in the X direction, converting the acquired MAP directions to be combined into the directions of the double-core streets to be consistent, combining according to a combining rule, and obtaining the second MAP after combining.
Further, in step S203, the merging rule specifically includes:
Determining the column number of the first MAP and the column number of the blind sealing wafer, classifying BINs in the first MAP, marking all good BINs by 1, and marking all bad BINs by 1" "Identify, empty BIN" identify, edge BIN "identify.
Further, the classification of the BIN in the first MAP is performed, all good BINs are identified by "1", and all bad BINs are identified by "1""Identification, empty BIN" identification, edge BIN "identification, specifically:
if the number of columns of the blind sealing wafer minus the number of columns of the first MAP is an odd multiple of 2, the 1 st column of the first MAP is the 1 st column of the second MAP, the 2 nd column and the 3 rd column of the first MAP are combined into one column, and the 2 nd column of the second MAP is combined until all columns in the first MAP are combined or a column is left finally; identifying BIN information in the first column of coordinates during combination, and converting good BIN and bad BIN into bad BIN " Identifying BIN information in coordinates of the 2 nd column and the 3 rd column during merging, merging into good BIN if the 2 nd column and the 3 rd column are both good BIN, merging into bad BIN if bad BIN or empty BIN exists in the 2 nd column and the 3 rd column, and using "/>"Identification; if the 2 nd column and the 3 rd column are both empty BIN, merging the two columns into the empty BIN for using an 'sign'; if the edge BIN exists in the 2 nd column and the 3 rd column, merging the edge BIN into the edge BIN by using a "#" sign based on the situation that the edge BIN exists, and merging the other columns of the first MAP according to a merging mode of the 2 nd column and the 3 rd column;
If the number of columns of the blind sealing wafer minus the number of columns of the first MAP is 0 or an even multiple of 2, merging the 1 st column and the 2 nd column of the coordinate axis into the 1 st column of the second MAP, merging the 3 rd column and the 4 th column into the 2 nd column of the second MAP until all columns in the first MAP are merged or a column is left finally, wherein the merging mode is the same as that in the odd multiple of the number of columns of the blind sealing wafer minus the number of columns of the first MAP is 2;
If the first MAP has 1 column at last, if the BIN type in the coordinates is a null BIN, the BIN is in the second MAP after conversion, if the BIN type is an edge BIN, the BIN is in the second MAP after conversion, if the BIN type is a good BIN, the BIN is in the second MAP after conversion, if the BIN type is a bad BIN, the BIN is in the second MAP after conversion.
Further, the first column of chips of the double-core scribed path is reserved as a single chip when all the blind sealing wafers are cut, and the first column is started as a double chip.
The second aspect of the invention provides a processing device, which is processed by the processing method of the double-core continuous scribing MAP chip taking product.
Compared with the prior art, the invention has the beneficial effects that:
The invention provides a processing method of a double-core continuous scribing MAP (MAP access point) chip-taking product, which can convert a single chip MAP of a double-core continuous scribing wafer into a double-core continuous scribing MAP, can solve the problem that the double-core continuous scribing product can only be subjected to blind sealing under the condition of the MAP, effectively solves the yield loss caused by manual dotting in blind sealing chip-taking, reduces material waste, and greatly improves the equipment utilization rate and the product packaging yield.
Drawings
FIG. 1 is a flow chart of a processing method of a double-core continuous scribing MAP (MAP) chip taking product provided by the invention;
FIG. 2 is a schematic diagram of a blind seal wafer according to an embodiment of the present invention;
FIG. 3 is a schematic illustration of dicing a single wafer in an embodiment of the invention;
FIG. 4 is a schematic diagram of a dual-core scribe wafer in accordance with an embodiment of the present invention, wherein the dashed lines indicate that the wafer is not diced and is dual-core;
FIG. 5 is a MAP of a single chip wafer in an embodiment of the invention;
FIG. 6 is a MAP diagram of a program open in an embodiment of the present invention;
FIG. 7 is a MAP of a dual-core joint line after merging using a program in an embodiment of the present invention;
FIG. 8 is a dual-core co-scribing MAP fragment diagram of a txt format derived using a program in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the embodiments described below are some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Accordingly, the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, is intended to represent only selected embodiments of the application, and not to limit the scope of the application as claimed. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on the embodiments of the present application, are within the scope of the present application.
It should be understood that in the description of embodiments of the invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first," "second," etc. may explicitly or implicitly include one or more of the described features.
In describing embodiments of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific circumstances.
Referring to fig. 1, the invention provides a processing method of a double-core continuous scribing MAP (MAP) chip taking product, which comprises the following steps:
s1, performing double-chip dicing on a blind sealing wafer of a target chip by using a dicing machine according to the chip size in a dicing process, and providing a first MAP of the blind sealing wafer.
S2, acquiring information of a first MAP, and converting and combining the MAP according to the information of the first MAP to obtain a second MAP, wherein the information of the first MAP comprises the number of BIN, the chip type, the notch direction, the wafer number, the wafer lot number and the column number.
And S3, using the generated second MAP to correspond the chip position to the second MAP, calibrating, and processing after the calibration is completed.
Further, in step S2, information of a first MAP is obtained, and the MAP is converted and combined according to the information of the first MAP to obtain a second MAP, which includes the following steps:
s201, acquiring information of a first MAP, and displaying the information of the first MAP in a coordinate axis taking the upper left corner as an origin of coordinates, wherein each character or vacancy obtains a corresponding coordinate.
S202, acquiring MAP information to be combined in the first MAP according to the coordinate starting point and the coordinate ending point.
And S203, uniformly rotating the directions of the double-core streets of the wafer in the X direction, converting the obtained MAP directions to be combined into the directions of the double-core streets to be consistent, combining according to a combining rule, and obtaining a second MAP after combining.
Optionally, in step S203, the merging rule specifically includes:
Determining the column number of the first MAP and the column number of the blind sealing wafer, classifying the BINs in the first MAP, marking all good BINs by using 1, and marking all bad BINs by using 1" "Identify, empty BIN" identify, edge BIN "identify.
Optionally, the BIN categories in the first MAP are categorized, all good BINs are identified by a "1", and all bad BINs are identified by a "1""Identification, empty BIN" identification, edge BIN "identification, specifically:
if the number of columns of the blind sealing wafer minus the number of columns of the first MAP is an odd multiple of 2, the 1 st column of the first MAP is the 1 st column of the second MAP, the 2 nd column and the 3 rd column of the first MAP are combined into one column, and the 2 nd column of the second MAP is used until all columns in the first MAP are combined or a column is left at last; identifying BIN information in the first column of coordinates during combination, and converting good BIN and bad BIN into bad BIN " Identifying BIN information in coordinates of the 2 nd column and the 3 rd column during merging, merging into good BIN if the 2 nd column and the 3 rd column are both good BIN, merging into bad BIN if bad BIN or empty BIN exists in the 2 nd column and the 3 rd column, and using "/>"Identification; if the 2 nd column and the 3 rd column are both empty BIN, merging the two columns into the empty BIN for using an 'sign'; if there is an edge BIN in the 2 nd and 3 rd columns, merging is performed as indicated by "#" based on the case that there is an edge BIN, and the remaining columns of the first MAP are also merged according to the merging manner of the 2 nd and 3 rd columns.
If the number of columns of the blind sealing wafer minus the number of columns of the first MAP is 0 or an even multiple of 2, the 1 st column and the 2 nd column of the coordinate axes are combined to form the 1 st column of the second MAP, the 3 rd column and the 4 th column are combined to form the 2 nd column of the second MAP, and the combination mode is the same as the combination mode in which the number of columns of the blind sealing wafer minus the number of columns of the first MAP is an odd multiple of 2 until all columns in the first MAP are combined or a column is left finally.
If the first MAP is left with 1 column at last, if the BIN type in the coordinates is empty BIN, the BIN is empty BIN in the second MAP after conversion, if the BIN type is edge BIN, the BIN is edge BIN in the second MAP after conversion, if the BIN type is good BIN, the BIN is bad BIN in the second MAP after conversion, and if the BIN type is bad BIN, the BIN is bad BIN in the second MAP after conversion.
Optionally, all the blind sealing wafers are cut while the first column of chips of the double-core scribe lanes are left as single chips, and the second column is started as double chips.
The invention also provides processing equipment which utilizes the processing method of the double-core continuous scribing MAP chip taking product to process.
Example 1
In this embodiment, taking an S6P97085 chip as an example, the wafer taking mode is MAP taking and double-core continuous scribing, and "1" in the MAP (including the first MAP and the second MAP) is good BIN, and "null BIN" and "X" is bad BIN. The processing method of the double-core continuous scribing MAP chip-taking product is adopted for processing, and a scribing machine is used for carrying out double-core scribing on the blind seal wafer of the chip type according to the chip size in the scribing process.
The column number of the first MAP is calculated to be 51 columns, the column number of the blind sealing wafer (calculated according to a single chip) is calculated to be 53 columns, the column number of the blind sealing wafer minus the column number of the first MAP is 2 or is even times of 2, and the double-core continuous-dividing MAP is combined according to the MAP of the 1 st column.
Clicking the classifying button after inputting to classify, wherein good BIN is represented by 1, and bad BIN is represented byThe empty BIN is represented.
And (3) selecting and merging the 1 st column, clicking a merging button, merging the first MAP, and merging the second MAP obtained after merging is shown in fig. 7.
And clicking the export button to output the file as a second MAP in TXT format which can be identified by the device, namely, a double-core continuous-drawing MAP.
And (3) the upper core uses the generated second MAP, and the chip position and the second MAP position are calibrated after corresponding, and the chip can be processed after the calibration is completed.
It should be noted that, the conversion rule in the application can be compiled into a program by using a programming language to realize automatic conversion, and the used codes are as follows;
leading in MAP files, selecting good BIN in MAP by a user, identifying bad BIN by B, identifying empty BIN by K, identifying edge BIN by T, and the code is as follows:
<input type="file" id="fileInput">
<div id="classificationOptions">
<label for="goodBin">G:</label>
< input type= "text" id= "goodBin" placeholder= "means good bin like 1,2" >
<label for="badBin">B:</label>
< Input type= "text" id= "badBin" placeholder= "indicates bad bin as 3,4" >
<label for="emptyBin">K:</label>
< Input type= "text" id= "emptyBin" placeholder= "means that the space bin is as" > "
<label for="edgeBin">T:</label>
< Input type= "text" id= "edgeBin" placeholder= "means edge bin as 5,6" >
In the application, the good BIN after combination is denoted by 1, and the bad BIN is denoted byThe empty BIN is represented, the edge BIN is represented by #, a MAP grid is created, the code is as follows:
< button id= "applyClassificationButton" > Classification </button >)
< Label > < input type= "checkbox" id= "mergeFirstColumn" > merge first column ]
< Button id= "mergeButton" > combination-
<div class="grid-container" id="gridContainer">
</I > -dynamic creation of mesh and characters-
</div>
<div id="classificationCount">
Dynamic display of classification statistics
</div>
<script>
document.getElementById('fileInput').addEventListener('change', function (event) {
const file = event.target.files[0];
if (!file) {
return;
}
const reader = new FileReader();
reader.onload = function (e) {
const text = e.target.result;
createGridWithLabels(text);
};
reader.readAsText(file);
});
function createGridWithLabels(text) {
const gridContainer = document.getElementById('gridContainer');
GridContainer InnerHTML=';// grid before purging
const rows = text.split('\n');
const maxColumns = rows.reduce((max, row) =>Math.max(max, row.length), 0);
Const gridSize = 20;// size of each grid
Column label creation
for (let x = 0; x<= maxColumns; x++) {
const colLabel = document.createElement('div');
colLabel.classList.add('col-label');
colLabel.textContent = x;
colLabel.style.top = '0';
colLabel.style.left = `${xgridSize}px`;
gridContainer.appendChild(colLabel);
}
Line labels and grids are created
for (let y = 0; y<rows.length; y++) {
const row = rows[y];
Creation of line labels
const rowLabel = document.createElement('div');
rowLabel.classList.add('row-label');
RowLabel.textContent=y+1;// line number starts from 1
rowLabel.style.top = `${(y + 1)gridSize}px`;
rowLabel.style.left = '0';
gridContainer.appendChild(rowLabel);
for (let x = 0; x<maxColumns; x++) {
const char = x<row.length ? row[x] : ' ';
const gridItem = document.createElement('div');
gridItem.classList.add('grid-item');
gridItem.textContent = char;
gridItem.style.top = `${(y + 1)gridSize}px`;
gridItem.style.left = `${(x + 1)gridSize}px`;
gridContainer.appendChild(gridItem);
}
}
Size of/(setting grid container)
gridContainer.style.width = `${(maxColumns + 1)gridSize}px`;
gridContainer.style.height = `${(rows.length + 1)gridSize}px`;
}document.getElementById('applyClassificationButton').addEventListener('click', function () {
const goodBinChars = document.getElementById('goodBin').value.split(',');
const badBinChars = document.getElementById('badBin').value.split(',');
const emptyBinChars = document.getElementById('emptyBin').value.split(',');
const edgeBinChars = document.getElementById('edgeBin').value.split(',');
const classificationMap = new Map();
classificationMap.set('1', goodBinChars);
classificationMap.set('', badBinChars);
classificationMap.set('.', emptyBinChars);
classificationMap.set('#', edgeBinChars);
const gridItems = document.querySelectorAll('.grid-item');
const classificationCounts = {
'1': 0,
'': 0,
'.': 0,
'#': 0,
'': 0
};
gridItems.forEach(function (item) {
const char = item.textContent;
let classification = '';
for (const [type, chars] of classificationMap) {
if (chars.includes(char)) {
classification = type;
break;
}
}
item.textContent = classification;
classificationCounts[classification]++;
});
Class statistics for/(and update)
updateClassificationCount(classificationCounts);
});
The merging rule codes in the application are as follows:
function updateClassificationCount(classificationCounts) {
const classificationCount = document.getElementById('classificationCount');
classicationcount inc =';// statistics before purging
for (const classification in classificationCounts) {
if (classificationCounts.hasOwnProperty(classification)) {
const count = classificationCounts[classification];
const div = document.createElement('div');
div.textContent = `${classification}:${count}`;
classificationCount.appendChild(div);
}
}
}
document.addEventListener('DOMContentLoaded', (event) =>{
const mergeButton = document.getElementById('mergeButton');
const mergeFirstColumnCheckbox = document.getElementById('mergeFirstColumn');
Check box for/call
mergeButton.addEventListener('click', mergeGrid);
function mergeGrid() {
const gridItems = document.querySelectorAll('.grid-item');
const mergeFirstColumn = mergeFirstColumnCheckbox.checked;
Check box for/call
if (mergeFirstColumn) {
for (let i = 0; i<gridItems.length; i += 2) {
If (GRIDITEMS [ i+1 ])// ensures that there is a second column
const content1 = gridItems[i].textContent;
const content2 = gridItems[i + 1].textContent;
const mergedContent = mergeContent(content1, content2);
gridItems[i].textContent = mergedContent;
GRIDITEMS [ i+1 ]. TextContent = ''; v/empty the second column of content
}
}
}
else {
for (let i = 1; i<gridItems.length; i += 2) {
If (GRIDITEMS [ i+1 ])// ensures that there is a second column
const content1 = gridItems[i].textContent;
const content2 = gridItems[i + 1].textContent;
const mergedContent = mergeContent(content1, content2);
gridItems[i].textContent = mergedContent;
GRIDITEMS [ i+1 ]. TextContent = ''; v/empty the second column of content
}
}
}
}
function mergeContent(content1, content2) {
if (content1 === content2) {
return content1;
} else if ((content1 === '1'&&content2 === '') || (content1 === '/>'&&content2 === '1') || (content1 === '1'&&content2 === '.') || (content1 === '1'&&content2 === '1') || (content1 === '/>'&&content2 === '.') || (content1 === '.'&&content2 === '/>')) {
return '';
} else if ((content1 === '1'&&content2 === '#') || (content1 === '#'&&content2 === '1') || (content1 === ''&&content2 === '#') || (content1 === '#'&&content2 === '/>') || (content1 === '.'&&content2 === '#') || (content1 === '#'&&content2 === '.')) {
return '#';
} else if (content1 === '1'&&content2 === '') {
return '';
} else {
Return content 1;// if there is no matching rule, the first column of content is maintained
}
}
});
</script>
A schematic diagram of the blind sealing wafer mentioned in this embodiment is shown in fig. 2; a schematic illustration of dicing a single wafer is shown in fig. 3; a schematic diagram of a dual-core dicing wafer is shown in fig. 4, wherein the broken line indicates that the wafer is not diced and is dual-core; a single chip wafer MAP is shown in fig. 5; a first MAP using program open is shown in fig. 6; the second MAP of the double-core link after merging using the program is shown in fig. 7; a dual-core co-scribing MAP-taking MAP using the program-derived txt format is shown in fig. 8.
The method provided by the application can convert the single chip MAP of the double-core continuous scribing wafer into the MAP graph of the double-core continuous scribing, can solve the problem that the double-core continuous scribing product can only be subjected to blind sealing under the condition of the MAP graph, effectively solves the yield loss caused by manual dotting in the blind sealing and taking process, reduces the material waste, and greatly improves the equipment utilization rate and the product packaging yield.
The foregoing description is merely illustrative of the preferred embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present application should be covered. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (6)

1. The processing method of the double-core continuous scribing MAP tablet-taking product is characterized by comprising the following steps of:
s1, performing double-chip dicing on a blind sealing wafer of a target chip by using a dicing saw according to the chip size in a dicing process, and providing a first MAP of the blind sealing wafer;
S2, acquiring information of the first MAP, and converting and combining the MAP according to the information of the first MAP to obtain a second MAP, wherein the information of the first MAP comprises BIN number, chip type, notch direction, wafer number, wafer lot number and column number;
And S3, using the generated second MAP to correspond the chip position to the second MAP, calibrating, and processing after the calibration is completed.
2. The processing method of the dual-core continuous scribing MAP slicing product according to claim 1, wherein in step S2, the information of the first MAP is obtained, and the MAP is converted and combined according to the information of the first MAP to obtain a second MAP, which comprises the following steps:
S201, acquiring information of the first MAP, and displaying the information of the first MAP in a coordinate axis taking the upper left corner as an origin of coordinates, wherein each character or vacancy obtains a corresponding coordinate;
S202, acquiring MAP information to be combined in the first MAP according to a coordinate starting point and a coordinate ending point;
And S203, uniformly rotating the directions of the double-core streets of the wafer in the X direction, converting the acquired MAP directions to be combined into the directions of the double-core streets to be consistent, combining according to a combining rule, and obtaining the second MAP after combining.
3. The method for processing a dual-core co-scribing MAP chip-taking product according to claim 2, wherein in step S203, the merging rule specifically includes:
Determining the column number of the first MAP and the column number of the blind sealing wafer, classifying BINs in the first MAP, marking all good BINs by 1, and marking all bad BINs by 1" "Identify, empty BIN" identify, edge BIN "identify.
4. The method of claim 3, wherein the BIN of the first MAP is classified, all good BINs are identified by "1", and all bad BINs are identified by "1""Identification, empty BIN" identification, edge BIN "identification, specifically:
if the number of columns of the blind sealing wafer minus the number of columns of the first MAP is an odd multiple of 2, the 1 st column of the first MAP is the 1 st column of the second MAP, the 2 nd column and the 3 rd column of the first MAP are combined into one column, and the 2 nd column of the second MAP is combined until all columns in the first MAP are combined or a column is left finally; identifying BIN information in the first column of coordinates during combination, and converting good BIN and bad BIN into bad BIN " Identifying BIN information in coordinates of the 2 nd column and the 3 rd column during merging, merging into good BIN if the 2 nd column and the 3 rd column are both good BIN, merging into bad BIN if bad BIN or empty BIN exists in the 2 nd column and the 3 rd column, and using "/>"Identification; if the 2 nd column and the 3 rd column are both empty BIN, merging the two columns into the empty BIN for using an 'sign'; if the edge BIN exists in the 2 nd column and the 3 rd column, merging the edge BIN into the edge BIN by using a "#" sign based on the situation that the edge BIN exists, and merging the other columns of the first MAP according to a merging mode of the 2 nd column and the 3 rd column;
If the number of columns of the blind sealing wafer minus the number of columns of the first MAP is 0 or an even multiple of 2, merging the 1 st column and the 2 nd column of the coordinate axes into the 1 st column of the second MAP, merging the 3 rd column and the 4 th column into the 2 nd column of the second MAP until all columns in the first MAP are merged or a column is left finally, wherein the merging mode is the same as that in the odd multiple of the number of columns of the blind sealing wafer minus the number of columns of the first MAP is 2;
If the first MAP has 1 column at last, if the BIN type in the coordinates is a null BIN, the BIN is in the second MAP after conversion, if the BIN type is an edge BIN, the BIN is in the second MAP after conversion, if the BIN type is a good BIN, the BIN is in the second MAP after conversion, if the BIN type is a bad BIN, the BIN is in the second MAP after conversion.
5. The method for processing the double-core continuous scribing MAP (MAP) flaking product according to any one of claims 1 to 4, wherein the method comprises the following steps:
and the first column of chips of the double-core scribing lane are reserved as single chips when all the blind sealing wafers are cut, and the second column is started as double chips.
6. A processing apparatus, characterized in that the processing apparatus processes with the processing method of the dual core link MAP chip-taking product according to any one of claims 1 to 5.
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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217260A (en) * 2001-01-19 2002-08-02 Nec Informatec Systems Ltd Device and method for fabrication of semiconductor wafer test map chart
CN102163591A (en) * 2010-12-02 2011-08-24 天水华天科技股份有限公司 Spherical grating array IC (integrated circuit) chip packaging part and production method thereof
US20120161328A1 (en) * 2010-12-22 2012-06-28 Via Technologies, Inc. Reticle set modification to produce multi-core dies
CN106447030A (en) * 2016-08-30 2017-02-22 深圳市诺比邻科技有限公司 Computing resource optimization method and system of convolutional neural network
CN110176420A (en) * 2019-07-11 2019-08-27 上海艾为电子技术股份有限公司 A kind of chip MAP coordinate marking method, device and encapsulation chip
CN212303634U (en) * 2020-04-29 2021-01-05 常州旺童半导体科技有限公司 Do benefit to centrosymmetric chip architecture of encapsulation
CN114372097A (en) * 2021-12-30 2022-04-19 北京达梦数据库技术有限公司 Efficient connection comparison implementation method and device for data set serialization
CN114546964A (en) * 2022-04-25 2022-05-27 南京品微智能科技有限公司 Automatic management system and method for advanced semiconductor packaging wafer map
CN114823642A (en) * 2022-04-28 2022-07-29 华天科技(南京)有限公司 Double-chip stacking packaging structure and method
WO2023034642A1 (en) * 2021-09-06 2023-03-09 Metaland Llc Encapsulating a metal inlay with thermosetting resin and method for making a metal transaction card
CN116844989A (en) * 2023-09-04 2023-10-03 北京智芯微电子科技有限公司 MAP generation method, and identification method and system for chip failure reasons
CN117116798A (en) * 2023-09-21 2023-11-24 上海积塔半导体有限公司 Wafer defect scanning method

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217260A (en) * 2001-01-19 2002-08-02 Nec Informatec Systems Ltd Device and method for fabrication of semiconductor wafer test map chart
CN102163591A (en) * 2010-12-02 2011-08-24 天水华天科技股份有限公司 Spherical grating array IC (integrated circuit) chip packaging part and production method thereof
US20120161328A1 (en) * 2010-12-22 2012-06-28 Via Technologies, Inc. Reticle set modification to produce multi-core dies
CN102543862A (en) * 2010-12-22 2012-07-04 威盛电子股份有限公司 Reticle set modification to produce multi-core dies
CN106447030A (en) * 2016-08-30 2017-02-22 深圳市诺比邻科技有限公司 Computing resource optimization method and system of convolutional neural network
CN110176420A (en) * 2019-07-11 2019-08-27 上海艾为电子技术股份有限公司 A kind of chip MAP coordinate marking method, device and encapsulation chip
CN212303634U (en) * 2020-04-29 2021-01-05 常州旺童半导体科技有限公司 Do benefit to centrosymmetric chip architecture of encapsulation
WO2023034642A1 (en) * 2021-09-06 2023-03-09 Metaland Llc Encapsulating a metal inlay with thermosetting resin and method for making a metal transaction card
CN114372097A (en) * 2021-12-30 2022-04-19 北京达梦数据库技术有限公司 Efficient connection comparison implementation method and device for data set serialization
CN114546964A (en) * 2022-04-25 2022-05-27 南京品微智能科技有限公司 Automatic management system and method for advanced semiconductor packaging wafer map
CN114823642A (en) * 2022-04-28 2022-07-29 华天科技(南京)有限公司 Double-chip stacking packaging structure and method
CN116844989A (en) * 2023-09-04 2023-10-03 北京智芯微电子科技有限公司 MAP generation method, and identification method and system for chip failure reasons
CN117116798A (en) * 2023-09-21 2023-11-24 上海积塔半导体有限公司 Wafer defect scanning method

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