JP2002214802A - Method for producing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the dimensional change of a resist pattern formed through photolithography. SOLUTION: In the method for producing a semiconductor device with a coating step, in which an object is coated with a photoresist and an exposure- development step in which the photoresist is patternwise exposed and developed to form a resist pattern, prebaking is not carried out or prebaking at a low temperature is carried out in the coating step, and prebaking is carried out in the beginning of the exposure-development step. The exposure-development step thus follows the prebaking in a short time and the change of the resist pattern can be reduced. Since the time from prebaking to exposure is made fixed, dimensional errors among lots or between wafers in the same lot can be diminished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photolithography technique for forming a resist mask on a semiconductor wafer or the like, and more particularly to a technique effective when applied to a pre-bake applied to a photoresist before exposure.

[0002]

2. Description of the Related Art In microfabrication of a semiconductor wafer or the like, a resist pattern formed in a photolithography process is used as a mask for various kinds of etching or the like to selectively process a metal film formed on the semiconductor wafer. Then, a pattern such as wiring is formed, and after processing, the resist pattern is removed.

In such a photolithography process, FIG.
As shown in the process flow, first, in a resist coating step, in order to improve the adhesiveness of a resist pattern to be formed, pre-coating treatment such as removal of foreign matter is performed on a semiconductor wafer as an object, for example, by a coater. Spin coating, for example, a positive type chemically amplified photoresist containing a novolak resin, etc., to increase the adhesion between the applied photoresist film and the base, and remove the organic solvent in the applied photoresist,
At the same time, prebake is performed to diffuse the acid generated by the exposure.

Next, in a photo-exposure / development step, a photomask or a reticle on which a mask pattern is formed is positioned and irradiated with ultraviolet light or a KrF excimer laser.
The mask pattern is selectively exposed to the photoresist on the semiconductor wafer, and an acid serving as a catalyst is generated in the exposed portion.
Subsequently, after the photoresist exposure, a post-exposure bake (PEB: Post Exposure Bak) for improving the pattern shape is performed.
e), a developing solution is adhered to the surface of the photoresist, and a developing process is performed for a predetermined time. Then, the developing solution is washed and removed with pure water and dried, and a soluble portion of the exposed photoresist is dissolved and removed with the developing solution. Then, the mask pattern is transferred to the photoresist, and a resist pattern corresponding to the mask pattern is formed. After that, post-baking is performed to improve the adhesiveness between the photoresist and the base, improve the etching resistance, and remove moisture inside the photoresist.

[0005]

After the pre-baking of the coating process is completed, the semiconductor wafer is transported or processed in a state of being stored in a storage container for each lot, depending on the state of the next photosensitive / developing process. It is temporarily stored while waiting. For this reason, the set-up time between the coating process and the exposure / development process varies for each lot.

The present inventors have investigated the effect of the chemically amplified resist due to the difference in the laying time between the coating step and the exposure / development step. FIG. 2 is a graph showing the results.
As shown in this graph, the resist dimensions changed according to the withdrawal time, and after 10 hours, the dimensional changes were about 6% to 7%, and after 48 hours, about 11% to 12%.

This is because a chemical change occurs in the resist itself even during the leaving time, and the size of the resist pattern fluctuates due to the chemical change. For example, MI
It is known that the threshold voltage, drain current, and the like, which are the basic performances of an SFET, depend on the gate length. In highly integrated and high-performance devices, the effect of the dimensional change of the gate length appears more remarkably. If the gate length formed using the resist as a mask due to the dimensional change of the resist pattern, this change The characteristics and yield of the product and the target performance depend on the product. With the progress of miniaturization of the element pattern of the semiconductor device, the pattern of the resist pattern becomes finer and the pattern interval is narrowed. For this reason, a variation in the pattern dimension causes a relatively large error, which is an obstacle to the miniaturization of the pattern. Therefore, it is an issue to further improve the precision of the pattern dimension.

In order to eliminate such dimensional fluctuation of the resist pattern and to stabilize the resist pattern, it is conceivable to set a certain restriction on the leaving time and process the product within a predetermined time. In this case, it is necessary to process the lot within the time limit, so that there is a lot to be processed preferentially and a lot to be on standby, and as a result, the overall processing capacity is reduced. Then, even if the size is reduced within the limit, each lot still has a difference in the laying time, and the laying time differs for each wafer of the same lot depending on the processing order. These differences also cause dimensional variations, and are not a fundamental solution.

Further, as shown in the flow chart of FIG. 3, a line for consistently processing the coating step and the exposure / development step may be constructed. However, in the case of existing equipment, there is a space problem. Therefore, since the processing is performed consistently, the entire processing is rate-limited by the processing having the slowest processing speed among the processing apparatuses, and the work efficiency of each processing apparatus is reduced.

An object of the present invention is to provide a technique capable of solving such a problem and preventing a dimensional change of a resist pattern due to a leaving time after application of a resist.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a method of manufacturing a semiconductor device having a coating step of applying a photoresist to an object and a photo-development step of forming a resist pattern by exposing the photoresist to a pattern to perform development, the resist coating step Prebaking is not performed or prebaking is performed at a low temperature, and prebaking is performed at the beginning of the photo-development and development process.

(Operation) According to the above-described means, it is possible to continuously shift from the pre-bake to the exposure / development process in a short time, and it is possible to reduce the fluctuation of the resist pattern. That is, since the time from prebaking to exposure is constant, dimensional errors between lots or between wafers of the same lot can be reduced.

Hereinafter, the configuration of the present invention will be described together with embodiments. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0016]

FIG. 4 is a diagram showing a process flow of a photolithography process according to an embodiment of the present invention. In the photolithography process according to the present embodiment, prebaking, which was conventionally performed at the end of the coating process, is performed at the beginning of the exposure / development process.

In the resist coating step of the present embodiment, first, a pre-coating process such as removal of foreign matter is performed on the semiconductor wafer as an object in order to improve the adhesion of the formed resist pattern to the semiconductor wafer.

Subsequently, for example, a positive type chemically amplified photoresist containing a novolak resin or the like is spin-coated with a coater, and a resist coating for forming a uniform photoresist film to a thickness of about 0.2 μm to 0.3 μm is performed. . In the resist coating step of the present embodiment, prebaking is not performed or prebaking is performed at a low temperature of about 50 ° C. to 60 ° C., and the semiconductor wafer coated with the photoresist is stored in a storage container for each lot, and then subjected to the following process. Depending on the condition of the processing apparatus in the process (1), the wafer is conveyed or waits for processing and is temporarily stored.

Next, in the exposure / development step, first, a pre-bake is performed for about 90 minutes at a predetermined temperature of about 80 ° C. to 110 ° C. using a hot plate or the like to increase the adhesiveness between the photoresist film and the base, The organic solvent remaining in the applied photoresist is volatilized and removed, and the acid generated by the exposure is diffused.

Subsequently, the photomask or reticle on which the mask pattern is formed is positioned, and the mask pattern is selectively exposed to the photoresist on the semiconductor wafer by irradiating ultraviolet rays or a KrF excimer laser or the like to the photosensitive portion. A photosensitive process for generating an acid serving as a catalyst is performed.

Subsequently, after the photoresist exposure, post-exposure baking is performed to improve the pattern shape, and if necessary, cooling is performed to avoid the influence of heat due to the post-exposure baking.

Subsequently, after a developing solution is attached to the surface of the photoresist and a developing process is performed for a predetermined time, a developing process of washing and removing the developing solution with pure water and drying is performed, and the soluble portion of the exposed photoresist is removed. After being dissolved and removed with a developing solution, the mask pattern is transferred to the photoresist, and a resist pattern corresponding to the mask pattern is formed.

Thereafter, post-baking is performed at a temperature of about 110 ° C. for improving the adhesion between the resist pattern and the base, improving the etching resistance, and removing the moisture inside the resist.

In the photolithography of this embodiment, the wafer is cooled by performing pre-baking at the beginning of the photo-exposure / development step, and the photo-exposure, post-exposure bake, development, and post-bake are successively performed. That is, the pre-bake is performed immediately before the photosensitive processing. Here, “immediately before” means that the processing is continuously performed after the baking and the cooling without accommodating the wafer in the container.

For this reason, it is possible to continuously shift from the pre-bake to the exposure / development process in a short time, and it is possible to reduce the fluctuation of the resist pattern. That is, since the time from prebaking to exposure is constant, dimensional errors between lots or between wafers of the same lot can be reduced.

As described above, according to the present invention, the dimensional fluctuation of the resist pattern can be suppressed. Therefore, a semiconductor device which has been miniaturized, for example, a wiring pattern having a width of about 0.13 μm and an arrangement pitch of about 0.26 μm, or 0.17 diameter
It is suitable for improving the accuracy of photolithography for forming a resist mask used for forming a hole pattern of about μm or the like. Further, the equipment is changed only by relocation or new installation of the pre-bake device, and can be easily performed.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. For example, the present invention can be applied to photolithography other than the semiconductor wafer described above.

[0028]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, it is possible to expose and
It is possible to shift to the developing step, and there is an effect that fluctuations in the resist pattern can be reduced. (2) According to the present invention, since the time from pre-bake to exposure is constant, there is an effect that dimensional errors between lots or between wafers of the same lot can be reduced. (3) According to the present invention, the effects (1) and (2) have an effect that the accuracy of the resist pattern can be improved. (4) According to the present invention, according to the effect (3), there is an effect that it is possible to improve the yield of a miniaturized semiconductor device. (5) According to the present invention, only the transfer or new installation of the pre-bake device is performed, and there is an effect that the equipment can be easily changed.

[Brief description of the drawings]

FIG. 1 is a view showing a process flow of a conventional photolithography process.

FIG. 2 is a graph showing a change in a resist pattern due to a difference in a withdrawal time between a coating process and a photosensitive / developing process in a conventional photolithography process.

FIG. 3 is a diagram showing a process flow of a modified example of a conventional photolithography process.

FIG. 4 is a view showing a process flow of a photolithography step which is an embodiment of the present invention.

Continued on the front page (72) Inventor Yoshiko Murakumo F-term (reference) 2H025 AB16 BE00 BE10 BG00 CB41 EA10 FA01 FA12 FA41 2H096 AA25 CA20 DA01 FA01 at Hitachi, Ltd. Device Development Center 6-16, Shinmachi, Ome-shi, Tokyo HA11 5F046 AA28

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: a coating step of applying a photoresist to an object; and a photo-development step of exposing and developing a pattern on the photoresist to form a resist pattern. A method of manufacturing a semiconductor device, wherein prebaking is not performed or low-temperature prebaking is performed in a process, and prebaking is performed at the beginning of the photo-developing / developing process.