JP2002208672A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002208672A
JP2002208672A JP2001003167A JP2001003167A JP2002208672A JP 2002208672 A JP2002208672 A JP 2002208672A JP 2001003167 A JP2001003167 A JP 2001003167A JP 2001003167 A JP2001003167 A JP 2001003167A JP 2002208672 A JP2002208672 A JP 2002208672A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor
base
semiconductor device
electrode pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001003167A
Other languages
Japanese (ja)
Inventor
Yoshihiro Basho
義博 芭蕉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001003167A priority Critical patent/JP2002208672A/en
Publication of JP2002208672A publication Critical patent/JP2002208672A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized, highly reliable semiconductor device in which many electronic circuits are formed in a highly integrated manner at a high density in a small area, and a wire is precisely jointed to the electrode pad of a semiconductor element. SOLUTION: This semiconductor device 7 is composed of an external terminal 4, base body 1, first semiconductor element 2 arranged on the base body 1 and provided with a plurality of first electrode pads 2a on an upper surface, second semiconductor element 3 arranged on the first semiconductor element 2 and provided with a plurality of second electrode pads 3a on the upper surface, wire 5 electrically connecting the first electrode pads 2a and second electrode pads 3a of the first semiconductor element 2 and the second semiconductor element 3 and the external terminal 4, and resin-coating material 6 coating the first semiconductor element 2 and the second semiconductor element 3. If the external dimensions of the first semiconductor element and the second semiconductor element are defined respectively as T1 and T2, then T1>T2 and 40>=T1-T2>=1.3 (mm) hold.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は情報処理装置や、携
帯電話等の電子装置に実装される半導体装置に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device and a semiconductor device mounted on an electronic device such as a mobile phone.

【0002】[0002]

【従来の技術】従来、コンピュータなどの情報処理装置
や携帯電話等の電子装置に実装される樹脂被覆タイプの
半導体装置は、一般に、半導体素子と、鉄−ニッケル−
コバルト合金や鉄−ニッケル合金等の金属材料から成る
基体及び複数個の外部端子と、エポキシ樹脂等の熱硬化
樹脂から成る樹脂被覆材とから構成されており、基体上
に半導体素子を金−シリコン共晶合金等のロウ材を介し
て固定するとともに半導体素子の各電極パッドを外部端
子にボンディング用のワイヤを介して電気的に接続し、
しかる後、前記半導体素子、基体及び外部端子の一部を
樹脂被覆材で被覆することによって製作されている。
2. Description of the Related Art Conventionally, a resin-coated semiconductor device mounted on an information processing device such as a computer or an electronic device such as a mobile phone generally includes a semiconductor element and an iron-nickel-type semiconductor device.
A base made of a metal material such as a cobalt alloy or an iron-nickel alloy, and a plurality of external terminals, and a resin coating material made of a thermosetting resin such as an epoxy resin. Fixing via a brazing material such as a eutectic alloy and electrically connecting each electrode pad of the semiconductor element to an external terminal via a bonding wire,
Thereafter, the semiconductor element, the base, and a part of the external terminal are manufactured by coating with a resin coating material.

【0003】前記半導体装置は、外部端子の外部導出端
部を外部電気回路基板の配線導体に半田等の接合材を介
し接合することによって外部電気回路基板上に実装さ
れ、同時に半導体素子の各電極パッドが外部端子を介し
て外部電気回路に電気的に接続されるようになってい
る。
[0003] The semiconductor device is mounted on the external electric circuit board by joining the external lead-out end of the external terminal to a wiring conductor of the external electric circuit board via a bonding material such as solder, and at the same time, each electrode of the semiconductor element is connected. The pad is electrically connected to an external electric circuit via an external terminal.

【0004】近年、コンピュータや携帯電話等の電子装
置は小型化、情報処理の高速化、高機能化が急激に進
み、これら電子装置に実装される半導体装置も半導体素
子に形成される電子回路を高密度、高集積化することが
強く要求されている。
In recent years, electronic devices such as computers and mobile phones have been rapidly reduced in size, faster in information processing, and more sophisticated, and semiconductor devices mounted on these electronic devices have also become electronic circuits formed of semiconductor elements. There is a strong demand for high density and high integration.

【0005】しかしながら、一個の半導体素子に多数の
電子回路を高密度、高集積に形成するには限界があり、
一個の半導体素子で電子装置の要求を達成することは困
難となってきている。
However, there is a limit in forming a large number of electronic circuits with high density and high integration in one semiconductor device.
It has become difficult to achieve the requirements of electronic devices with one semiconductor element.

【0006】そこで上記欠点を解消するために電気絶縁
性の基体の上下両面に半導体素子をロウ材等で接着固定
するとともに、各半導体素子の電極パッドを基体の接続
パッド等にワイヤを介して電気的に接続し、しかる後、
半導体素子、基体および必要に応じて外部端子の一部を
樹脂被覆材で被覆して成る半導体装置が提案されてい
る。
Therefore, in order to solve the above-mentioned drawbacks, the semiconductor elements are bonded and fixed to the upper and lower surfaces of the electrically insulating base with a brazing material or the like, and the electrode pads of each semiconductor element are electrically connected to the connection pads of the base via wires. Connected, and then
There has been proposed a semiconductor device in which a semiconductor element, a base, and, if necessary, a part of an external terminal are covered with a resin coating material.

【0007】この半導体装置によれば、半導体素子が基
体の上下両面にそれぞれ実装されていることから半導体
装置の平面面積を増加させることなく、容易に半導体装
置における電子回路の高密度、高集積化を図ることがで
きる。
According to this semiconductor device, since the semiconductor element is mounted on each of the upper and lower surfaces of the base, the electronic circuit in the semiconductor device can be easily formed with high density and high integration without increasing the planar area of the semiconductor device. Can be achieved.

【0008】しかしながら、上記半導体装置において
は、まず1個の半導体素子を基体の上面にロウ材等を介
して接着固定するとともに、この半導体素子の電極パッ
ドを基体の接続パッド等にワイヤを介して接続し、次に
前記基体を裏返して基体下面に他の半導体素子を接着固
定するとともに、この基体下面に固定した半導体素子の
電極パッドを基体の下面に形成した接続パッド等にワイ
ヤを介して接続しなければならず製造工程が複雑で長
く、生産性が悪いという欠点を有する。
However, in the above-described semiconductor device, first, one semiconductor element is bonded and fixed to the upper surface of the base via a brazing material or the like, and the electrode pads of the semiconductor element are connected to connection pads or the like of the base via wires. Then, the substrate is turned upside down and another semiconductor element is bonded and fixed to the lower surface of the substrate, and the electrode pads of the semiconductor element fixed to the lower surface of the substrate are connected to connection pads formed on the lower surface of the substrate via wires. The manufacturing process is complicated, long, and has the disadvantage of low productivity.

【0009】また基体を裏返して基体下面に他の半導体
素子を接着固定するとともに、この基体下面に固定した
半導体素子の電極パッドを基体の下面に形成した接続パ
ッド等にワイヤを介して接続する際、基体の上面側に固
定された半導体素子に接続されているワイヤが外れた
り、切れたりして製品としての半導体装置の信頼性およ
び歩留まりが大きく低下するという欠点を有する。
In addition, the substrate is turned upside down and another semiconductor element is adhered and fixed to the lower surface of the substrate, and an electrode pad of the semiconductor element fixed to the lower surface of the substrate is connected to a connection pad formed on the lower surface of the substrate via a wire. In addition, the wire connected to the semiconductor element fixed on the upper surface side of the base is detached or cut off, and the reliability and yield of the semiconductor device as a product are greatly reduced.

【0010】更に基体の下面に他の半導体素子を接着固
定する際、及び基体下面に接着固定した半導体素子の電
極パッドと基体の下面に形成した接続パッド等とをワイ
ヤを介して接続する際、上面側に半導体素子が接着固定
されている基体を保持するのに上面側の半導体素子の形
状を考慮した特殊な冶具が個々に必要となってしまい、
この汎用性のない特殊な冶具の使用によって製品として
の半導体装置を高価としてしまう欠点を有する。
Further, when another semiconductor element is bonded and fixed to the lower surface of the base, and when the electrode pads of the semiconductor element bonded and fixed to the lower surface of the base are connected to connection pads formed on the lower surface of the base via wires, A special jig considering the shape of the semiconductor element on the top side is individually required to hold the base on which the semiconductor element is bonded and fixed on the top side,
There is a disadvantage that the use of the special jig having no versatility makes the semiconductor device as a product expensive.

【0011】そこで更に、基体の上面に2個の半導体素
子を上下に積層、接着して固定するとともに各半導体素
子の電極パッドを、基体の接続パッドや外部端子にワイ
ヤを介して電気的に接続し、しかる後、半導体素子およ
び基体の一部を樹脂被覆材で被覆して成る半導体装置が
提案されている。
Further, two semiconductor elements are vertically stacked, adhered and fixed on the upper surface of the base, and the electrode pads of each semiconductor element are electrically connected to connection pads and external terminals of the base via wires. Thereafter, a semiconductor device in which a semiconductor element and a part of a base are covered with a resin coating material has been proposed.

【0012】この半導体装置によれば、2個の半導体素
子がともに基体の上面に積層して固定されていることか
ら、半導体装置の平面面積を増加させることなく容易に
半導体装置の高密度化を図ることができる。また同時に
この半導体装置は基体の同一面に2個の半導体素子が接
着固定されているため基体に半導体素子を接着固定する
際、或いは各半導体素子の電極パッドを、基体の接続パ
ッドや外部端子にワイヤを介して電気的に接続する際等
において基体をいちいち裏返す必要は全くなく、その結
果、基体を保持するのに汎用性のない特殊な冶具の使用
が不要となるとともに基体の接続パッドや外部端子と各
半導体素子の電極パッドとを接続するワイヤに外れや切
断が生じることはほとんどなくなり、製品としての半導
体装置の信頼性および歩留まり、生産性を大きく向上さ
せることができる。
According to this semiconductor device, since the two semiconductor elements are both stacked and fixed on the upper surface of the base, the density of the semiconductor device can be easily increased without increasing the planar area of the semiconductor device. Can be planned. At the same time, in this semiconductor device, two semiconductor elements are bonded and fixed to the same surface of the base, so that when the semiconductor elements are bonded and fixed to the base, electrode pads of each semiconductor element are connected to connection pads and external terminals of the base. There is no need to turn the substrate over, such as when making electrical connections via wires, and as a result, there is no need to use special jigs that are not versatile to hold the substrate, and the connection pads and external The wire connecting the terminal and the electrode pad of each semiconductor element is hardly disconnected or cut, and the reliability, yield, and productivity of the semiconductor device as a product can be greatly improved.

【0013】[0013]

【発明が解決しようとする課題】しかしながら、従来、
各種半導体素子はその外形寸法が近似する場合が多く、
外形寸法が近似する2個の半導体素子を上下に積層した
場合、基体に接着固定した下側に位置する半導体素子の
上面外周縁と上側に位置する半導体素子の外側壁との間
の距離が、例えば約0.5mm以下の非常に短いものと
なり、その結果、下側に位置する半導体素子の上面外周
縁に電極パッドを形成するのが困難となるとともに下側
に位置する半導体素子の上面に形成した電極パッドにボ
ンディング用のワイヤを周知の超音波ボンディング装置
等を使用して接合する際、ボンディング装置のキャピラ
リが上側に位置する半導体素子に接触して、下側に位置
する半導体素子の電極パッドにワイヤを正確、強固に接
合させることができず、半導体装置としての信頼性が低
下するという欠点が誘発されてしまう。
However, conventionally,
Various semiconductor elements often have similar external dimensions,
When two semiconductor elements having similar outer dimensions are vertically stacked, the distance between the outer peripheral edge of the upper surface of the lower semiconductor element bonded and fixed to the base and the outer wall of the upper semiconductor element, For example, it is very short, about 0.5 mm or less. As a result, it is difficult to form an electrode pad on the outer peripheral edge of the upper surface of the lower semiconductor element, and it is difficult to form an electrode pad on the upper surface of the lower semiconductor element. When a bonding wire is bonded to the formed electrode pad using a well-known ultrasonic bonding device or the like, the capillary of the bonding device contacts the semiconductor device located on the upper side and the electrode pad of the semiconductor device located on the lower side. In this case, the wire cannot be bonded accurately and firmly, and the reliability of the semiconductor device is reduced.

【0014】本発明は、上記諸欠点に鑑み案出されたも
ので、その目的は小面積にして多数の電子回路を高密度
に、高集積に形成することができ、かつ半導体素子の電
極パッドにワイヤが正確に接合された小型、高信頼性の
半導体装置を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to reduce the area and to form a large number of electronic circuits with high density and high integration. Another object of the present invention is to provide a small and highly reliable semiconductor device in which wires are accurately joined.

【0015】[0015]

【課題を解決するための手段】本発明の半導体装置は、
外部端子と、基体と、該基体上に配され、上面に複数個
の第1電極パッドを有する第1半導体素子と、該第1半
導体素子上に配され、上面に複数個の第2電極パッドを
有する第2半導体素子と、前記第1半導体素子及び第2
半導体素子の第1電極パッドと第2電極パッドと外部端
子とを電気的に接続するワイヤと、前記第1半導体素子
及び第2半導体素子を被覆する樹脂被覆材とから成る半
導体装置であって、前記第1半導体素子及び第2半導体
素子の外形寸法をそれぞれT1、T2としたとき、T1
2であり、かつ40≧T1−T2≧1.3(mm)であ
ることを特徴とするものである。
According to the present invention, there is provided a semiconductor device comprising:
An external terminal, a base, a first semiconductor element disposed on the base and having a plurality of first electrode pads on the upper surface, and a plurality of second electrode pads disposed on the first semiconductor element and on the upper surface A second semiconductor element having the first semiconductor element and the second semiconductor element.
A semiconductor device comprising: a wire for electrically connecting a first electrode pad, a second electrode pad, and an external terminal of a semiconductor element; and a resin coating material for covering the first semiconductor element and the second semiconductor element, When the outer dimensions of the first semiconductor element and the second semiconductor element are T 1 and T 2 , respectively, T 1 >
T 2 and 40 ≧ T 1 −T 2 ≧ 1.3 (mm).

【0016】本発明の半導体装置によれば、基体上に第
1半導体素子、第2半導体素子の2個の半導体素子を上
下に積層するとともに、第1半導体素子の第1電極パッ
ドと第2半導体素子の第2電極パッドと外部端子とをワ
イヤを介し電気的に接続するようにしたことから、半導
体装置の平面面積を増加させることなく半導体装置にお
ける電子回路の高密度化、高集積化を図ることができ
る。
According to the semiconductor device of the present invention, two semiconductor elements of a first semiconductor element and a second semiconductor element are vertically stacked on a base, and the first electrode pad of the first semiconductor element and the second semiconductor element are connected to each other. Since the second electrode pad of the element and the external terminal are electrically connected via the wire, the electronic circuit in the semiconductor device is increased in density and integration without increasing the planar area of the semiconductor device. be able to.

【0017】また本発明の半導体装置によれば、基体の
同一面に2個の半導体素子が接着固定されているため基
体に半導体素子を接着固定する際、或いは各半導体素子
の電極パッドを外部端子等にワイヤを介して電気的に接
続する際等において、基体をいちいち裏返す必要は全く
なく、その結果、基体を保持するのに汎用性のない特殊
な冶具の使用が不要となるとともに外部端子等と各半導
体素子の電極パッドとを接続するワイヤに外れや切断が
生じることはほとんどなくなり、製品としての半導体装
置の信頼性および歩留まり、生産性を大きく向上させる
ことができる。
According to the semiconductor device of the present invention, two semiconductor elements are bonded and fixed to the same surface of the base, so that the semiconductor elements are bonded and fixed to the base or the electrode pads of each semiconductor element are connected to the external terminals. There is no need to turn over the base at all when electrically connecting to the base via wires, etc. As a result, the use of special jigs that are not versatile to hold the base is unnecessary, and external terminals etc. There is almost no disconnection or breakage in the wire connecting the semiconductor device and the electrode pad of each semiconductor element, and the reliability, yield, and productivity of the semiconductor device as a product can be greatly improved.

【0018】更に本発明の半導体装置によれば、第1半
導体素子及び第2半導体素子の外形寸法をそれぞれ
1、T2としたとき、T1>T2であり、かつ40≧T1
−T2≧1.3(mm)としたことから、基体上に第1
半導体素子、第2半導体素子を順次接着固定したとき、
第1半導体素子の上面外周縁に電極パッドを容易に形成
し得、かつ該電極パッドにワイヤを接合するためのボン
ディング装置のキャピラリ等が入り込むに十分なスペー
スを確保することができ、これによって第1半導体素子
に電極パッドを確実に形成することが可能となるととも
に第1半導体素子の電極パッドと、第2半導体素子の電
極パッドおよび外部端子とをワイヤを介して確実に接続
することができる。
Further, according to the semiconductor device of the present invention, when the outer dimensions of the first semiconductor element and the second semiconductor element are T 1 and T 2 , respectively, T 1 > T 2 and 40 ≧ T 1
−T 2 ≧ 1.3 (mm), the first
When the semiconductor element and the second semiconductor element are sequentially bonded and fixed,
An electrode pad can be easily formed on the outer peripheral edge of the upper surface of the first semiconductor element, and a sufficient space for a capillary or the like of a bonding apparatus for joining a wire to the electrode pad can be secured. The electrode pads of one semiconductor element can be reliably formed, and the electrode pads of the first semiconductor element, the electrode pads of the second semiconductor element, and the external terminals can be reliably connected via wires.

【0019】[0019]

【発明の実施の形態】次に本発明の半導体装置につい
て、添付の図面を基に詳細に説明する。図1は本発明の
半導体装置の一実施例を示す断面図であり、図1におい
て、1は基体、2は第1半導体素子、3は第2半導体素
子、4は外部端子、5はボンディング用のワイヤ、6は
樹脂被覆材であり、これらの基体1、第1半導体素子
2、第2半導体素子3、外部端子4、ワイヤ5、樹脂被
覆材6により半導体装置7が形成される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In FIG. 1, reference numeral 1 denotes a base, 2 denotes a first semiconductor element, 3 denotes a second semiconductor element, 4 denotes an external terminal, and 5 denotes a bonding terminal. A wire 6 is a resin coating material, and a semiconductor device 7 is formed by the base 1, the first semiconductor element 2, the second semiconductor element 3, the external terminal 4, the wire 5, and the resin coating material 6.

【0020】前記基体1は、第1半導体素子2、第2半
導体素子3を搭載、支持する作用をなし、銅、銅合金、
鉄−ニッケル合金、鉄−ニッケル−コバルト合金、アル
ミニウム、アルミニウム合金等の金属材料により形成さ
れている。
The base 1 has a function of mounting and supporting the first semiconductor element 2 and the second semiconductor element 3, and is made of copper, copper alloy,
It is formed of a metal material such as an iron-nickel alloy, an iron-nickel-cobalt alloy, aluminum, and an aluminum alloy.

【0021】前記基体1は、例えば、銅等の金属材料か
ら成るインゴット(塊)に対し適当な圧延加工、打抜き
加工等の金属加工を施すことによって形成される。
The base 1 is formed by subjecting an ingot (a lump) made of a metal material such as copper to a suitable metal working such as rolling or punching.

【0022】また前記基体1の外側にはリード端子等の
外部端子4が配されており、該外部端子4は第1半導体
素子2および第2半導体素子3の電子回路を外部の電気
回路に接続する作用をなす。
An external terminal 4 such as a lead terminal is arranged outside the base 1, and the external terminal 4 connects an electronic circuit of the first semiconductor element 2 and the second semiconductor element 3 to an external electric circuit. To act.

【0023】前記外部端子4は、銅、銅合金、鉄−ニッ
ケル合金、鉄−ニッケル−コバルト合金、アルミニウ
ム、アルミニウム合金等の金属材料から成り、基体1と
同様の方法によって所定の形状に形成される。
The external terminals 4 are made of a metal material such as copper, copper alloy, iron-nickel alloy, iron-nickel-cobalt alloy, aluminum, and aluminum alloy, and are formed in a predetermined shape by the same method as that of the base 1. You.

【0024】なお前記外部端子4は通常、基体1と同種
の材料により形成され、基体1とは吊りリード等を介し
て一体化している。
The external terminals 4 are usually formed of the same material as the base 1, and are integrated with the base 1 via suspension leads or the like.

【0025】また前記基体1の上面には第1半導体素子
2が搭載されており、該第1半導体素子2はロウ材やガ
ラス、有機樹脂等の接着材を介して基体1の上面に接着
固定されている。この場合、接着材は弾性係数の低い有
機樹脂等を使用することが望ましく、接着材として弾性
係数が低い有機樹脂を使用すると第1半導体素子2と基
体1との熱膨張係数の差に起因して生じる熱応力を接着
材が効果的に吸収緩和し、第1半導体素子2と基体1と
の間に発生する熱応力によって第1半導体素子2にクラ
ック等の機械的な破壊が生じるのを有効に防止すること
ができる。
A first semiconductor element 2 is mounted on the upper surface of the base 1, and the first semiconductor element 2 is bonded and fixed to the upper surface of the base 1 via an adhesive such as brazing material, glass, or organic resin. Have been. In this case, it is desirable to use an organic resin or the like having a low elastic coefficient as the adhesive. If an organic resin with a low elastic coefficient is used as the adhesive, the difference is caused by a difference in thermal expansion coefficient between the first semiconductor element 2 and the base 1. The adhesive effectively absorbs and alleviates the thermal stress generated by the adhesive, and it is effective that the thermal stress generated between the first semiconductor element 2 and the base 1 causes the first semiconductor element 2 to be mechanically broken such as a crack. Can be prevented.

【0026】前記第1半導体素子2は、その上面の外周
縁に複数個の第1電極パッド2aが形成されており、該
電極パッド2aは第1半導体素子2の電子回路を外部端
子4や後述する第2半導体素子3の第2電極パッド3a
に接続する際の端子として作用し、ボンディング用のワ
イヤ5が接合される。
The first semiconductor element 2 has a plurality of first electrode pads 2a formed on the outer peripheral edge of the upper surface thereof. The electrode pads 2a are used to connect the electronic circuit of the first semiconductor element 2 to the external terminals 4 and to be described later. Electrode pad 3a of the second semiconductor element 3 to be
, And the bonding wire 5 is joined.

【0027】更に前記第1半導体素子2の上面には第2
半導体素子3が搭載されており、該第2半導体素子3は
ロウ材やガラス、有機樹脂等の接着材を介して第1半導
体素子2の上面に接着固定されている。この場合、接着
材は弾性係数の低い有機樹脂等を使用することが望まし
く、接着材として弾性係数が低い有機樹脂を使用すると
第1半導体素子2と第2半導体素子3との熱膨張係数の
差に起因して生じる熱応力を接着材が効果的に吸収緩和
し、第1半導体素子2と第2半導体素子3との間に発生
する熱応力によって第1半導体素子2や第2半導体素子
3にクラック等の機械的な破壊が生じるのを有効に防止
することができる。
Further, on the upper surface of the first semiconductor element 2, a second
The semiconductor element 3 is mounted, and the second semiconductor element 3 is bonded and fixed to the upper surface of the first semiconductor element 2 via an adhesive such as brazing material, glass, or organic resin. In this case, it is desirable to use an organic resin or the like having a low elastic coefficient as the adhesive. If an organic resin with a low elastic coefficient is used as the adhesive, the difference in the thermal expansion coefficient between the first semiconductor element 2 and the second semiconductor element 3 is obtained. The adhesive material effectively absorbs and relaxes the thermal stress caused by the first semiconductor element 2 and the second semiconductor element 3 due to the thermal stress generated between the first semiconductor element 2 and the second semiconductor element 3. It is possible to effectively prevent mechanical destruction such as cracks from occurring.

【0028】前記第2半導体素子3は、その上面に複数
個の電極パッド3aが形成されており、該電極パッド3
aは第2半導体素子3の電子回路を第1半導体素子2や
外部端子4に接続する際の端子として作用し、ボンディ
ング用のワイヤ5が接合される。
The second semiconductor element 3 has a plurality of electrode pads 3a formed on the upper surface thereof.
“a” acts as a terminal when the electronic circuit of the second semiconductor element 3 is connected to the first semiconductor element 2 and the external terminal 4, and the bonding wire 5 is joined.

【0029】本発明においては基体1上に第1半導体素
子2と第2半導体素子3とを上下に積層しておくことが
重要である。基体1の上面に第1半導体素子2と第2半
導体素子3を順次積層すると半導体装置7の平面面積を
増加させることなく半導体装置7における電子回路の高
密度化、高集積化を図ることができる。
In the present invention, it is important that the first semiconductor element 2 and the second semiconductor element 3 are vertically stacked on the base 1. When the first semiconductor element 2 and the second semiconductor element 3 are sequentially stacked on the upper surface of the base 1, the electronic circuit in the semiconductor device 7 can have higher density and higher integration without increasing the planar area of the semiconductor device 7. .

【0030】また同時に基体1の同一面に2個の半導体
素子2,3が接着固定されているため基体1に半導体素
子2,3を接着固定する際、或いは各半導体素子2,3
の電極パッド2a,3aを外部端子4等にワイヤ5を介
して電気的に接続する際等において、基体1をいちいち
裏返す必要は全くなく、その結果、基体1を保持するの
に汎用性のない特殊な治具の使用が不要となるとともに
外部端子4等と各半導体素子2,3の電極パッド2a,
3aとを接続するワイヤ5に外れや切断が生じることは
ほとんどなくなり、製品としての半導体装置7の信頼性
および歩留まり、生産性を大きく向上させることができ
る。
At the same time, the two semiconductor elements 2 and 3 are bonded and fixed to the same surface of the base 1, so that the semiconductor elements 2 and 3 are bonded and fixed to the base 1,
When the electrode pads 2a and 3a are electrically connected to the external terminals 4 and the like via the wires 5, there is no need to turn over the base 1 at all, and as a result, there is no versatility to hold the base 1. The use of a special jig becomes unnecessary, and the external terminals 4 and the like and the electrode pads 2a,
The wire 5 connecting to the wire 3a is hardly detached or cut, and the reliability, yield, and productivity of the semiconductor device 7 as a product can be greatly improved.

【0031】更に本発明においては、前記第1半導体素
子及び第2半導体素子の外形寸法をそれぞれT1、T2
したとき、T1>T2とし、かつ40≧T1−T2≧1.3
(mm)としておくことが重要である。
Further, in the present invention, when the outer dimensions of the first semiconductor element and the second semiconductor element are T 1 and T 2 , respectively, T 1 > T 2 and 40 ≧ T 1 −T 2 ≧ 1 .3
(Mm) is important.

【0032】前記第1半導体素子及び第2半導体素子の
外形寸法をそれぞれT1、T2としたとき、T1>T2
し、かつ40≧T1−T2≧1.3(mm)としておくと
基体1上に第1半導体素子2、第2半導体素子3を順次
接着固定したとき、第1半導体素子2の上面外周縁に電
極パッド2aを形成し得、かつ該電極パッド2aにワイ
ヤ5を接合するためのボンディング装置のキャピラリ等
が入り込むに十分なスペースを確保することができ、こ
れによって第1半導体素子2に電極パッド2aを確実に
形成することが可能となるとともに第1半導体素子2の
電極パッド2aと、第2半導体素子3の電極パッド3a
および外部端子4とをワイヤ5を介して確実に接続する
ことができる。
When the outer dimensions of the first semiconductor element and the second semiconductor element are T 1 and T 2 , respectively, T 1 > T 2 and 40 ≧ T 1 −T 2 ≧ 1.3 (mm). In other words, when the first semiconductor element 2 and the second semiconductor element 3 are sequentially bonded and fixed on the base 1, an electrode pad 2 a can be formed on the outer peripheral edge of the upper surface of the first semiconductor element 2, and the wire 5 is connected to the electrode pad 2 a. Can secure a sufficient space for a capillary or the like of a bonding device for joining the first semiconductor element 2 to be formed, whereby the electrode pads 2a can be reliably formed on the first semiconductor element 2 and the first semiconductor element 2 Electrode pad 2a of the second semiconductor element 3
And the external terminal 4 can be reliably connected via the wire 5.

【0033】なお、前記第1半導体素子2及び第2半導
体素子3の外形寸法をそれぞれT1、T2としたとき、T
1−T2<1.3(mm)となると、第1半導体素子2の
上面外周縁に形成できるスペースが狭くなり、第1半導
体素子2に電極パッド2aを形成するのが困難となると
ともに、第1半導体素子2の電極パッド2aにワイヤ5
をボンディング装置を用いて正確に接続することができ
なくなってしまう。従って、前記第1半導体素子2及び
第2半導体素子の外形寸法をそれぞれT1、T2としたと
き、T1−T2≧1.3(mm)に特定される。
When the outer dimensions of the first semiconductor element 2 and the second semiconductor element 3 are T 1 and T 2 , respectively,
When 1− T 2 <1.3 (mm), the space that can be formed on the outer peripheral edge of the upper surface of the first semiconductor element 2 becomes narrow, and it becomes difficult to form the electrode pad 2 a on the first semiconductor element 2. The wire 5 is connected to the electrode pad 2a of the first semiconductor element 2.
Cannot be accurately connected using a bonding apparatus. Therefore, assuming that the outer dimensions of the first semiconductor element 2 and the second semiconductor element are T 1 and T 2 , respectively, they are specified as T 1 −T 2 ≧ 1.3 (mm).

【0034】また前記第1半導体素子2及び第2半導体
素子3の外形寸法をそれぞれT1、T2としたとき、40
<T1−T2(mm)となると、第1半導体素子2の上面
外周縁に形成されるスペースが大きくなりすぎ、第1半
導体素子2の電極パッド2aと、第2半導体素子3の電
極パッド3aおよび外部端子4とを接続するワイヤ5の
長さが不要に長くなって、ワイヤの倒れや切断が起こり
易くなり、半導体装置7の信頼性が低下してしまう。従
って、前記第1半導体素子2、第2半導体素子3の外形
寸法をそれぞれT1、T2としたとき、40≧T1−T
2(mm)に特定される。
When the outer dimensions of the first semiconductor element 2 and the second semiconductor element 3 are T 1 and T 2 , respectively,
If <T 1 −T 2 (mm), the space formed on the outer peripheral edge of the upper surface of the first semiconductor element 2 becomes too large, and the electrode pads 2 a of the first semiconductor element 2 and the electrode pads of the second semiconductor element 3 are formed. The length of the wire 5 connecting the 3a and the external terminal 4 becomes unnecessarily long, so that the wire is likely to fall or be cut, and the reliability of the semiconductor device 7 is reduced. Therefore, when the outer dimensions of the first semiconductor element 2 and the second semiconductor element 3 are T 1 and T 2 , respectively, 40 ≧ T 1 −T
2 (mm).

【0035】前記外部端子4の一部、基体1、該基体1
上に固定されている第1半導体素子2及び第2半導体素
子3はその表面が樹脂被覆材6で被覆されており、該樹
脂被覆材6によって第1半導体素子2及び第2半導体素
子3が気密に封止されている。
Part of the external terminal 4, the base 1, and the base 1
The surfaces of the first semiconductor element 2 and the second semiconductor element 3 fixed thereon are covered with a resin coating material 6, and the first semiconductor element 2 and the second semiconductor element 3 are hermetically sealed by the resin coating material 6. Is sealed.

【0036】前記樹脂被覆材6はエポキシ樹脂、シリコ
ーン樹脂、ポリアミド樹脂、ポリイミド樹脂等の樹脂、
またはこれらの樹脂に適当な充填材を混合したものが用
いられ、例えば、熱硬化性のエポキシ樹脂からなる場合
であれば、所定の金型内に外部端子4と、上面に第1半
導体素子2及び第2半導体素子3が順次積層されている
基体1とをセットするとともに金型内にエポキシ樹脂等
の液状樹脂を注入し、しかる後、注入した樹脂に180
℃程度の温度を加えて熱硬化させることによって外部端
子4の一部、基体1、該基体1上に固定されている第1
半導体素子2及び第2半導体素子3の表面に被着され
る。この場合、基体1をアルミニウムもしくは銅を主成
分とする金属で形成しておくと該アルミニウム等はエポ
キシ樹脂から成る樹脂被覆材6と密着性が良いことから
基体1表面に樹脂被覆材6を極めて強固に接合させるこ
とができる。従って、樹脂被覆材6をエポキシ樹脂で形
成する場合には、基体1はアルミニウムもしくは銅を主
成分とする金属で形成しておくことが好ましい。
The resin coating material 6 is made of a resin such as an epoxy resin, a silicone resin, a polyamide resin, and a polyimide resin.
Alternatively, a mixture of these resins mixed with an appropriate filler is used. For example, in the case of a thermosetting epoxy resin, the external terminals 4 are provided in a predetermined mold and the first semiconductor element 2 is provided on the upper surface. Then, the base 1 on which the second semiconductor element 3 is sequentially laminated is set, and a liquid resin such as an epoxy resin is injected into a mold.
A part of the external terminal 4, the base 1, and the first
It is attached to the surface of the semiconductor element 2 and the second semiconductor element 3. In this case, if the base 1 is formed of a metal containing aluminum or copper as a main component, the aluminum or the like has good adhesion to the resin coating 6 made of an epoxy resin. It can be firmly joined. Therefore, when the resin coating material 6 is formed of an epoxy resin, the base 1 is preferably formed of a metal containing aluminum or copper as a main component.

【0037】また前記樹脂被覆材6は、その内部に熱伝
導率が50W/m・K以上の無機物もしくは金属粉末を
2乃至30重量%の割合で添加しておくと樹脂被覆材6
の熱伝導率が高く、熱を伝導しやすいものとなって第1
半導体素子2および第2半導体素子3が作動時に発する
熱を樹脂被覆材6を介して大気中に良好に放散すること
ができ、半導体装置7の信頼性をより一層良好とするこ
とができる。従って、前記樹脂被覆材6は、その内部に
熱伝導率が50W/m・K以上の無機物もしくは金属粉
末を2乃至30重量%の割合で添加しておくことが好ま
しい。なおこの樹脂被覆材6に添加する熱伝導率が50
W/m・K以上の無機物もしくは金属粉末としては、窒
化アルミニウム粉末、炭化珪素粉末、窒化ホウ素粉末等
の無機物粉末、あるいはアルミニウム、銅もしくはその
合金等の金属粉末が好適に使用される。
The resin coating material 6 can be prepared by adding an inorganic or metal powder having a thermal conductivity of 50 W / m · K or more at a rate of 2 to 30% by weight.
Has high thermal conductivity and is easy to conduct heat.
The heat generated during operation of the semiconductor element 2 and the second semiconductor element 3 can be satisfactorily radiated into the atmosphere via the resin coating material 6, and the reliability of the semiconductor device 7 can be further improved. Therefore, it is preferable to add an inorganic or metal powder having a thermal conductivity of 50 W / m · K or more in the resin coating material 6 at a ratio of 2 to 30% by weight. The thermal conductivity added to the resin coating material 6 is 50
As the inorganic or metal powder of W / m · K or more, an inorganic powder such as an aluminum nitride powder, a silicon carbide powder, a boron nitride powder, or a metal powder such as aluminum, copper, or an alloy thereof is preferably used.

【0038】かくして上述の半導体装置7は外部端子4
の外部導出端部を外部電気回路基板の配線導体に半田等
の接合材を介し接合することによって外部電気回路基板
上に実装され、同時に第1半導体素子2及び第2半導体
素子3の各電極パッド2a、3aが外部端子4を介して
外部電気回路に電気的に接続されるようになっている。
Thus, the above-described semiconductor device 7 has the external terminal 4
Of the first semiconductor element 2 and the second semiconductor element 3 are simultaneously mounted on the external electric circuit board by joining the external lead-out end to the wiring conductor of the external electric circuit board via a bonding material such as solder. 2a and 3a are electrically connected to an external electric circuit via the external terminal 4.

【0039】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、上述の実施例において第1半
導体素子2及び第2半導体素子3は、それぞれがメモリ
ー素子等の同種の機能を有する半導体素子であっても、
また制御素子とメモリー素子等、異種の機能を有する半
導体素子であってもよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Even if the second semiconductor element 3 is a semiconductor element having the same kind of function as a memory element,
Further, semiconductor elements having different functions, such as a control element and a memory element, may be used.

【0040】[0040]

【発明の効果】本発明の半導体装置によれば、基体上に
第1半導体素子、第2半導体素子の2個の半導体素子を
上下に積層するとともに、第1半導体素子の第1電極パ
ッドと第2半導体素子の第2電極パッドと外部端子とを
ワイヤを介し電気的に接続するようにしたことから、半
導体装置の平面面積を増加させることなく半導体装置に
おける電子回路の高密度化、高集積化を図ることができ
る。
According to the semiconductor device of the present invention, two semiconductor elements, a first semiconductor element and a second semiconductor element, are vertically stacked on a base, and the first electrode pad of the first semiconductor element and the first electrode pad are stacked. (2) Since the second electrode pads of the semiconductor elements and the external terminals are electrically connected via wires, the density and density of electronic circuits in the semiconductor device are increased without increasing the planar area of the semiconductor device. Can be achieved.

【0041】また本発明の半導体装置によれば、基体の
同一面に2個の半導体素子が接着固定されているため基
体に半導体素子を接着固定する際、或いは各半導体素子
の電極パッドを外部端子等にワイヤを介して電気的に接
続する際等において、基体をいちいち裏返す必要は全く
なく、その結果、基体を保持するのに汎用性のない特殊
な冶具の使用が不要となるとともに外部端子等と各半導
体素子の電極パッドとを接続するワイヤに外れや切断が
生じることはほとんどなくなり、製品としての半導体装
置の信頼性および歩留まり、生産性を大きく向上させる
ことができる。
According to the semiconductor device of the present invention, since two semiconductor elements are bonded and fixed to the same surface of the base, the semiconductor elements are bonded and fixed to the base, or the electrode pads of each semiconductor element are connected to the external terminals. There is no need to turn over the base at all times when electrically connecting to the base via wires, etc. As a result, there is no need to use special jigs that are not versatile to hold the base and external terminals etc. There is almost no disconnection or breakage in the wire connecting the semiconductor device and the electrode pad of each semiconductor element, and the reliability, yield, and productivity of the semiconductor device as a product can be greatly improved.

【0042】更に本発明の半導体装置によれば、第1半
導体素子及び第2半導体素子の外形寸法をそれぞれ
1、T2としたとき、T1>T2であり、かつ40≧T1
−T2≧1.3(mm)としたことから、基体上に第1
半導体素子、第2半導体素子を順次接着固定したとき、
第1半導体素子の上面外周縁に電極パッドを形成し得、
かつ該電極パッドにワイヤを接合するためのボンディン
グ装置のキャピラリ等が入り込むに十分なスペースを確
保することができ、これによって第1半導体素子に電極
パッドを確実に形成することが可能となるとともに第1
半導体素子の電極パッドと、第2半導体素子の電極パッ
ドおよび外部端子とをワイヤを介して確実に接続するこ
とができる。
Further, according to the semiconductor device of the present invention, when the outer dimensions of the first semiconductor element and the second semiconductor element are T 1 and T 2 , respectively, T 1 > T 2 and 40 ≧ T 1
−T 2 ≧ 1.3 (mm), the first
When the semiconductor element and the second semiconductor element are sequentially bonded and fixed,
An electrode pad may be formed on the outer peripheral edge of the upper surface of the first semiconductor element,
In addition, it is possible to secure a sufficient space for a capillary or the like of a bonding device for bonding a wire to the electrode pad, thereby making it possible to reliably form the electrode pad on the first semiconductor element. 1
The electrode pads of the semiconductor element, the electrode pads of the second semiconductor element, and the external terminals can be reliably connected via wires.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の一実施例を示す断面図で
ある。
FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・・基体 2・・・・・・・第1半導体素子 2a・・・・・・第1電極パッド 3・・・・・・・第2半導体素子 3a・・・・・・第2電極パッド 4・・・・・・・外部端子 5・・・・・・・ワイヤ 6・・・・・・・樹脂被覆材 7・・・・・・・半導体装置 1 Base 2 First semiconductor element 2a First electrode pad 3 Second semiconductor element 3a · 2nd electrode pad 4 · · · · · · external terminals 5 · · · · · · wires 6 · · · · · resin coating 7 · · · · · · · · semiconductor device

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】外部端子と、基体と、該基体上に配され、
上面に複数個の第1電極パッドを有する第1半導体素子
と、該第1半導体素子上に配され、上面に複数個の第2
電極パッドを有する第2半導体素子と、前記第1半導体
素子及び第2半導体素子の第1電極パッドと第2電極パ
ッドと外部端子とを電気的に接続するワイヤと、前記第
1半導体素子及び第2半導体素子を被覆する樹脂被覆材
と、から成る半導体装置であって、前記第1半導体素子
及び第2半導体素子の外形寸法をそれぞれT1、T2とし
たとき、T1>T2であり、かつ40≧T1−T2≧1.3
(mm)であることを特徴とする半導体装置。
1. An external terminal, a base, and disposed on the base,
A first semiconductor device having a plurality of first electrode pads on an upper surface, and a plurality of second semiconductor devices disposed on the first semiconductor device and having an upper surface;
A second semiconductor element having an electrode pad; wires for electrically connecting the first electrode pad, the second electrode pad, and the external terminal of the first semiconductor element and the second semiconductor element; A resin coating material for covering the two semiconductor elements, wherein T 1 > T 2 when the outer dimensions of the first semiconductor element and the second semiconductor element are T 1 and T 2 , respectively. And 40 ≧ T 1 −T 2 ≧ 1.3
(Mm).
JP2001003167A 2001-01-11 2001-01-11 Semiconductor device Pending JP2002208672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001003167A JP2002208672A (en) 2001-01-11 2001-01-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001003167A JP2002208672A (en) 2001-01-11 2001-01-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2002208672A true JP2002208672A (en) 2002-07-26

Family

ID=18871558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001003167A Pending JP2002208672A (en) 2001-01-11 2001-01-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2002208672A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8142677B2 (en) 2004-03-26 2012-03-27 Tdk Corporation Piezoelectric ceramic composition

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8142677B2 (en) 2004-03-26 2012-03-27 Tdk Corporation Piezoelectric ceramic composition

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