JP2002208660A - Mounting board and module for electronic element chip - Google Patents
Mounting board and module for electronic element chipInfo
- Publication number
- JP2002208660A JP2002208660A JP2001003226A JP2001003226A JP2002208660A JP 2002208660 A JP2002208660 A JP 2002208660A JP 2001003226 A JP2001003226 A JP 2001003226A JP 2001003226 A JP2001003226 A JP 2001003226A JP 2002208660 A JP2002208660 A JP 2002208660A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electronic element
- element chip
- board
- metal substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子素子チップ用
載置基板及び電子素子チップモジュールに関し、特に、
絶縁体基板と金属基板とを接合してなり、少なくとも一
つの電子素子チップを載置する電子素子チップ用載置基
板とこの載置基板を備える電子素子チップモジュールに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting substrate for an electronic device chip and an electronic device chip module.
The present invention relates to a mounting substrate for an electronic element chip, which is formed by bonding an insulator substrate and a metal substrate and mounts at least one electronic element chip, and an electronic element chip module including the mounting substrate.
【０００２】[0002]
【従来の技術】従来、この種の電子素子チップを載置す
る載置基板として、窒化アルミニウムから形成された絶
縁体基板とアルミニウムから形成された金属基板とを接
合したものが提案されている。この載置基板では、窒化
アルミニウムとアルミニウムとは共に熱伝導率が高い材
料であるので、電子素子チップからの熱を載置基板で効
率よく放熱することができる。2. Description of the Related Art Heretofore, as a mounting substrate on which such an electronic element chip is mounted, a substrate in which an insulating substrate formed of aluminum nitride and a metal substrate formed of aluminum are joined has been proposed. In this mounting substrate, since aluminum nitride and aluminum are both materials having high thermal conductivity, heat from the electronic element chip can be efficiently radiated by the mounting substrate.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この載
置基板では、窒化アルミニウムとアルミニウムとは互い
に熱膨張率が異なっているので、絶縁体基板と金属基板
との間の熱膨張差により接合部に熱応力が生じ、絶縁体
基板と金属基板とが剥離したり、接合部にクラックが発
生したりする。However, in this mounting substrate, aluminum nitride and aluminum have different coefficients of thermal expansion. Therefore, due to the difference in thermal expansion between the insulator substrate and the metal substrate, the aluminum nitride and the aluminum substrate have different thermal expansion coefficients. Thermal stress is generated, and the insulating substrate and the metal substrate are separated from each other, and cracks are generated at the joints.
【０００４】本発明は、上記課題を解決するためになさ
れたものであり、絶縁体基板と金属基板との接合部に発
生する熱応力を抑制することを目的とする。[0004] The present invention has been made to solve the above-mentioned problem, and has as its object to suppress thermal stress generated at a joint between an insulator substrate and a metal substrate.
【０００５】[0005]
【課題を解決するための手段】本発明の電子素子チップ
用載置基板は、絶縁体基板と金属基板とを接合してな
り、少なくとも一つの電子素子チップを載置する電子素
子チップ用載置基板であって、前記金属基板は、前記絶
縁体基板の材料と同じ材料の粒子を分散させてなること
を特徴とする。According to the present invention, there is provided an electronic device chip mounting substrate comprising an insulating substrate and a metal substrate joined to each other to mount at least one electronic device chip. A substrate, wherein the metal substrate is formed by dispersing particles of the same material as the material of the insulator substrate.
【０００６】本発明の電子素子チップ用載置基板では、
金属基板に絶縁体基板の材料と同じ材料の粒子を分散さ
せているので、絶縁体基板と金属基板との間の熱膨張の
差が小さくなる。この結果、絶縁体基板と金属基板との
接合部に発生する熱応力を抑制することができる。In the mounting substrate for an electronic element chip of the present invention,
Since particles of the same material as the material of the insulator substrate are dispersed in the metal substrate, the difference in thermal expansion between the insulator substrate and the metal substrate is reduced. As a result, it is possible to suppress the thermal stress generated at the joint between the insulator substrate and the metal substrate.
【０００７】本発明の電子素子チップ用載置基板におい
て、前記金属基板は、前記粒子の含有率が１〜２０％で
あるものとすることもできる。こうすれば、絶縁体基板
と金属基板との接合強度の低下を許容範囲内に抑えるこ
とができる。In the electronic device chip mounting substrate according to the present invention, the metal substrate may have a particle content of 1 to 20%. In this case, it is possible to suppress a decrease in the bonding strength between the insulator substrate and the metal substrate within an allowable range.
【０００８】本発明の電子素子チップモジュールは、本
発明の前記電子素子チップ用載置基板と、前記電子素子
チップ用載置基板に載置された少なくとも一つの電子素
子チップと、を備えることを特徴とする。An electronic element chip module according to the present invention includes: the electronic element chip mounting substrate according to the present invention; and at least one electronic element chip mounted on the electronic element chip mounting substrate. Features.
【０００９】本発明の電子素子チップモジュールでは、
電子素子チップ用載置基板の金属基板に絶縁体基板の材
料と同じ材料の粒子を分散させているので、絶縁体基板
と金属基板との間の熱膨張差が小さくなる。この結果、
絶縁体基板と金属基板との接合部に発生する熱応力を抑
制することができる。In the electronic element chip module of the present invention,
Since particles of the same material as the material of the insulator substrate are dispersed in the metal substrate of the mounting substrate for electronic element chips, the difference in thermal expansion between the insulator substrate and the metal substrate is reduced. As a result,
It is possible to suppress a thermal stress generated at a joint between the insulator substrate and the metal substrate.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態（以下
実施形態という）を、図面に従って説明する。Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.
【００１１】図１は、本実施形態の電子素子チップモジ
ュール１００の構成の概略を示す側面図であり、図２
は、電子素子チップモジュール１００を図１のＡ方向か
ら眺めたときの平面図である。電子素子チップモジュー
ル１００は、載置基板１０の表面に半田３０により接合
された電子素子チップ４０と、載置基板１０の裏面に半
田３０により接合された放熱板５０とを備える。FIG. 1 is a side view schematically showing the structure of an electronic element chip module 100 according to this embodiment.
FIG. 2 is a plan view when the electronic element chip module 100 is viewed from a direction A in FIG. 1. The electronic element chip module 100 includes an electronic element chip 40 joined to the surface of the mounting substrate 10 by solder 30 and a heat sink 50 joined to the back surface of the mounting substrate 10 by solder 30.
【００１２】電子素子チップ４０は、駆動条件によって
はＩＧＢＴ（Insulated Gate Bipolar Transistor），
パワーＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Fiel
d-Effect Transistor），パワートランジスタやダイオ
ードなどが含まれるものとする。The electronic element chip 40 has an IGBT (Insulated Gate Bipolar Transistor), depending on driving conditions.
Power MOSFET (Metal-Oxide-Semiconductor Fiel)
d-Effect Transistor), power transistors and diodes.
【００１３】放熱板５０は、熱伝導性の高い材料、例え
ば銅や銅−モリブデン，アルミニウム，ステンレスなど
の金属を用いて、空気や水などの冷却媒体に熱を放出す
る部材として構成されている。例えば、その内部に冷却
媒体の流路を有していたり、他の部材とによって冷却媒
体の流路を形成したりする。また、冷却媒体の流路に面
した部位に放熱効果を高めるためフィンが形成されてい
るものも含まれる。The heat radiating plate 50 is made of a material having high thermal conductivity, for example, a metal such as copper, copper-molybdenum, aluminum, and stainless steel, and is configured as a member for releasing heat to a cooling medium such as air or water. . For example, a cooling medium flow path is provided inside the cooling medium, or a cooling medium flow path is formed by other members. In addition, a case where a fin is formed at a portion facing the flow path of the cooling medium to enhance a heat radiation effect is also included.
【００１４】載置基板１０は、窒化アルミニウムから形
成され厚さ約０．８ｍｍの絶縁体基板１２と、絶縁体基
板１２の表面と裏面とにろう付けされた二つの金属基板
１４と、各金属基板１４のろう付けされない面に形成さ
れたニッケルメッキ層１６とを備える。The mounting substrate 10 includes an insulating substrate 12 made of aluminum nitride and having a thickness of about 0.8 mm, two metal substrates 14 brazed to the front and back surfaces of the insulating substrate 12, A nickel plating layer 16 formed on the surface of the substrate 14 that is not brazed.
【００１５】金属基板１４は、厚さが約０．４ｍｍであ
り、アルミニウムの母材中に粒径約２〜１０μｍの絶縁
体基板１２と同じ材料である窒化アルミニウム粒子が所
定量分散された材料から形成されている。このような金
属基板１４は、約７５０℃の純アルミニウムの原料溶湯
中に粒径約２〜１０μｍの窒化アルミニウム粒が均一に
分散するように撹拌溶解したものを冷間圧延加工して製
造される。The metal substrate 14 has a thickness of about 0.4 mm and is made of a material in which aluminum nitride particles, which are the same material as the insulating substrate 12 having a particle size of about 2 to 10 μm, are dispersed in a predetermined amount in an aluminum base material. Is formed from. Such a metal substrate 14 is manufactured by cold-rolling a material obtained by stirring and dissolving aluminum nitride particles having a particle size of about 2 to 10 μm uniformly in a raw melt of pure aluminum at about 750 ° C. so as to be uniformly dispersed. .
【００１６】こうして構成された電子素子チップモジュ
ール１００では、電子素子チップ４０で発生する熱が載
置基板１０を介して放熱板５０から放熱される。載置基
板１０の金属基板１４には、絶縁体基板１２の材料と同
じ材料の窒化アルミニウム粒子が分散しているので、金
属基板１４と絶縁体基板１２との熱膨張の差が小さくな
っている。この結果、金属基板１４と絶縁体基板１２と
の接合部での熱応力が抑制され、絶縁体基板１２と金属
基板１４との剥離や接合部でのクラックの発生を抑制す
ることができる。In the electronic element chip module 100 configured as described above, heat generated in the electronic element chip 40 is radiated from the radiator plate 50 through the mounting substrate 10. Since aluminum nitride particles of the same material as the material of the insulator substrate 12 are dispersed in the metal substrate 14 of the mounting substrate 10, the difference in thermal expansion between the metal substrate 14 and the insulator substrate 12 is reduced. . As a result, thermal stress at the joint between the metal substrate 14 and the insulator substrate 12 is suppressed, and peeling between the insulator substrate 12 and the metal substrate 14 and generation of cracks at the joint can be suppressed.
【００１７】なお、載置基板１０では、金属基板１４
は、アルミニウムの母材中に窒化アルミニウム粒子を所
定量分散させたものとしたが、所定量は、金属基板１４
と絶縁体基板１２との接合強度の低下を許容範囲内に抑
えると共に金属基板１４と絶縁体基板１２との熱膨張差
を充分小さくする程度の量とするのがよい。図３は、金
属基板１４の全体積に対する粒径２〜１０μｍの窒化ア
ルミニウム粒子の含有率と金属基板１４の絶縁体基板１
２との接合面の様子との関係を示す表である。図３に示
すように、含有率が高くなるほど金属基板１４の接合面
にうねりが生じるので、金属基板１４と絶縁体基板１２
との接合強度が低下する。一方、含有率が低すぎると金
属基板１４と絶縁体基板１２との熱膨張差が大きくなっ
てしまう。載置基板１０では、金属基板１４中の窒化ア
ルミニウムの含有率を１〜２０％程度にすることで、金
属基板１４と絶縁体基板１２との接合強度の低下を許容
範囲内に抑えると共に金属基板１４と絶縁体基板１２と
の熱膨張差を充分小さくすることができる。In the mounting substrate 10, the metal substrate 14
Was prepared by dispersing a predetermined amount of aluminum nitride particles in an aluminum base material.
It is preferable that the decrease in the bonding strength between the metal substrate 14 and the insulator substrate 12 be kept within an allowable range and the thermal expansion difference between the metal substrate 14 and the insulator substrate 12 be sufficiently small. FIG. 3 shows the content of aluminum nitride particles having a particle size of 2 to 10 μm with respect to the total volume of the metal substrate 14 and the insulating substrate 1 of the metal substrate 14.
6 is a table showing a relationship between the bonding surface and No. 2; As shown in FIG. 3, the higher the content, the more undulation occurs on the bonding surface of the metal substrate 14.
And the bonding strength with the alloy decreases. On the other hand, if the content is too low, the difference in thermal expansion between the metal substrate 14 and the insulator substrate 12 increases. In the mounting substrate 10, by reducing the content of aluminum nitride in the metal substrate 14 to about 1 to 20%, a decrease in bonding strength between the metal substrate 14 and the insulator substrate 12 is suppressed to an allowable range, and The difference in thermal expansion between the substrate 14 and the insulator substrate 12 can be made sufficiently small.
【００１８】本実施形態の電子素子チップモジュール１
００では、絶縁体基板１２の材料と金属基板１４の母材
中に分散させる粒子とが同じ材料で形成されていればよ
く、窒化アルミニウムの他に窒化珪素，酸化アルミニウ
ムなどを材料としてもよい。Electronic device chip module 1 of the present embodiment
In the case of 00, the material of the insulator substrate 12 and the particles dispersed in the base material of the metal substrate 14 need only be formed of the same material, and may be silicon nitride, aluminum oxide, or the like in addition to aluminum nitride.
【００１９】本実施形態の電子素子チップモジュール１
００では、金属基板１４はアルミニウムを母材とするも
のとしたが、アルミニウム合金，銅，銅合金，黄銅，鉄
などを母材としてもよい。Electronic device chip module 1 of the present embodiment
In 00, the metal substrate 14 is made of aluminum as a base material, but may be made of aluminum alloy, copper, copper alloy, brass, iron, or the like as a base material.
【００２０】本実施形態の電子素子チップモジュール１
００では、載置基板１０上に一つの電子素子チップ４０
を載置するものとしたが、電子素子チップを複数個載置
するものとすることもできる。Electronic device chip module 1 of the present embodiment
00, one electronic element chip 40 on the mounting substrate 10
Is mounted, but a plurality of electronic element chips may be mounted.
【００２１】以上、本発明の実施の形態について実施例
を用いて説明したが、本発明はこうした実施例に何等限
定されるものではなく、本発明の要旨を逸脱しない範囲
内において、種々なる形態で実施し得ることは勿論であ
る。Although the embodiments of the present invention have been described with reference to the embodiments, the present invention is not limited to these embodiments at all, and various embodiments may be made without departing from the gist of the present invention. Of course, it can be carried out.
【００２２】[0022]
【発明の効果】本発明の電子素子チップ用載置基板で
は、金属基板に絶縁体基板の材料と同じ材料の粒子を分
散させているので、絶縁体基板と金属基板との間の熱膨
張の差が小さくなる。この結果、絶縁体基板と金属基板
との接合部に発生する熱応力を抑制することができる。According to the electronic device chip mounting substrate of the present invention, the particles of the same material as the material of the insulator substrate are dispersed in the metal substrate, so that the thermal expansion between the insulator substrate and the metal substrate is reduced. The difference becomes smaller. As a result, it is possible to suppress the thermal stress generated at the joint between the insulator substrate and the metal substrate.
【００２３】また、本発明の電子素子チップモジュール
では、電子素子チップ用載置基板の金属基板に絶縁体基
板の材料と同じ材料の粒子を分散させているので、絶縁
体基板と金属基板との間の熱膨張の差が小さくなる。こ
の結果、絶縁体基板と金属基板との接合部に発生する熱
応力を抑制することができる。Further, in the electronic element chip module of the present invention, the particles of the same material as the material of the insulator substrate are dispersed in the metal substrate of the mounting substrate for the electronic element chip. The difference in thermal expansion between them. As a result, it is possible to suppress the thermal stress generated at the joint between the insulator substrate and the metal substrate.
【図１】 本実施形態の電子素子チップモジュール１０
０の構成の概略を示す側面図である。FIG. 1 is an electronic element chip module 10 of the present embodiment.
FIG. 2 is a side view showing the outline of the configuration of FIG.
【図２】 電子素子チップモジュール１００を図１のＡ
方向から眺めたときの平面図である。FIG. 2 shows the electronic element chip module 100 in FIG.
FIG. 3 is a plan view when viewed from a direction.
【図３】 金属基板１４の全体積に対する粒径２〜１０
μｍの窒化アルミニウム粒子の含有率と金属基板１４と
絶縁体基板１２との金属基板１４側接合界面の様子との
関係を示す表である。FIG. 3 shows a particle size of 2 to 10 with respect to the total volume of the metal substrate 14.
4 is a table showing the relationship between the content of aluminum nitride particles of μm and the state of the bonding interface between the metal substrate 14 and the insulator substrate 12 on the metal substrate 14 side.
１０ 載置基板、１２ 絶縁体基板、１４ 金属基板、
４０ 電子素子チップ、１００ 電子素子チップモジュ
ール。10 mounting substrate, 12 insulator substrate, 14 metal substrate,
40 electronic element chips, 100 electronic element chip modules.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 和明 愛知県豊田市トヨタ町１番地 トヨタ自動 車株式会社内 (72)発明者 新居 良英 愛知県豊田市トヨタ町１番地 トヨタ自動 車株式会社内 (72)発明者 今井 誠 愛知県豊田市トヨタ町１番地 トヨタ自動 車株式会社内 Ｆターム(参考） 5E315 AA03 GG01 5F036 AA01 BB08 BD01 BD13 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuaki Sato 1 Toyota Town, Toyota City, Aichi Prefecture Inside Toyota Motor Corporation (72) Inventor Yoshihide Arai 1 Toyota Town, Toyota City, Aichi Prefecture Inside Toyota Motor Corporation (72) Inventor Makoto Imai 1 Toyota Town, Toyota City, Aichi Prefecture Toyota Motor Corporation F-term (reference) 5E315 AA03 GG01 5F036 AA01 BB08 BD01 BD13
Claims (3)
り、少なくとも一つの電子素子チップを載置する電子素
子チップ用載置基板であって、 前記金属基板は、前記絶縁体基板の材料と同じ材料の粒
子を分散させてなることを特徴とする電子素子チップ用
載置基板。1. An electronic device chip mounting substrate on which an insulator substrate and a metal substrate are bonded and on which at least one electronic device chip is mounted, wherein the metal substrate is made of a material for the insulator substrate. A mounting substrate for an electronic element chip, wherein particles of the same material as described above are dispersed.
〜２０％であることを特徴とする請求項１に記載の電子
素子チップ用載置基板。2. The method according to claim 1, wherein the metal substrate has a particle content of 1%.
2. The mounting substrate for an electronic element chip according to claim 1, wherein:
用載置基板と、 前記電子素子チップ用載置基板に載置された少なくとも
一つの電子素子チップと、を備えることを特徴とする電
子素子チップモジュール。3. An electronic element chip mounting substrate according to claim 1 or 2, and at least one electronic element chip mounted on the electronic element chip mounting substrate. Electronic element chip module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001003226A JP2002208660A (en) | 2001-01-11 | 2001-01-11 | Mounting board and module for electronic element chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001003226A JP2002208660A (en) | 2001-01-11 | 2001-01-11 | Mounting board and module for electronic element chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002208660A true JP2002208660A (en) | 2002-07-26 |
Family
ID=18871601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001003226A Pending JP2002208660A (en) | 2001-01-11 | 2001-01-11 | Mounting board and module for electronic element chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002208660A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009164413A (en) * | 2008-01-08 | 2009-07-23 | Mitsubishi Materials Corp | Power module substrate and power module |
| JP2012004534A (en) * | 2010-05-18 | 2012-01-05 | Showa Denko Kk | Heat radiation insulating substrate and method of manufacturing the same |
| US10475777B2 (en) | 2015-11-16 | 2019-11-12 | Sumitomo Electric Device Innovations, Inc. | Semiconductor apparatus installing passive device |
-
2001
- 2001-01-11 JP JP2001003226A patent/JP2002208660A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009164413A (en) * | 2008-01-08 | 2009-07-23 | Mitsubishi Materials Corp | Power module substrate and power module |
| JP2012004534A (en) * | 2010-05-18 | 2012-01-05 | Showa Denko Kk | Heat radiation insulating substrate and method of manufacturing the same |
| US10475777B2 (en) | 2015-11-16 | 2019-11-12 | Sumitomo Electric Device Innovations, Inc. | Semiconductor apparatus installing passive device |
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