JP2002201098A - Method of manufacturing silicon carbide substrate and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a 3C-SiC single crystal reduced in generation of stacking fault with good reproducibility. SOLUTION: The method of manufacturing the SiC single crystal is as follows: after forming a plurality of line and space ups and downs on the Si substrate, performing epitaxial growth of a 1st 3C-SiC layer 21 on the surface of Si substrate 11; after removing Si substrate 11 from the 1st 3C-SiC layer 21, performing epitaxial growth of a 2nd 3C-SiC layer 22 on the exposed surface having ups and downs of the 1st 3C-SiC layer 21; flattening the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a 3C (cubic) system.
3C-SiC having excellent crystallinity, particularly desirable for manufacturing semiconductor devices,
The present invention relates to a method for manufacturing a single crystal substrate and a method for manufacturing a semiconductor device using the substrate.

[0002]

2. Description of the Related Art Conventionally, SiC (silicon carbide) is grown by bulk crystal growth by a sublimation method, and a gas phase in which a source gas of a Si compound and a source gas of a C compound are supplied onto a substrate to generate SiC by reaction. It has been classified into thin film formation by an epitaxial growth method.

[0003] In bulk crystal growth by sublimation, <000 000 of hexagonal 6H SiC which is a polymorph of a high-temperature stable phase and 4H SiC which is also a hexagonal but slightly low-temperature phase is used.
1> Growth is possible, and such (0001)
Until the SiC substrate is sold. However, the density of defects called microvibes is still high,
In addition, it was difficult to increase the substrate area.

On the other hand, when the vapor phase epitaxial growth method on a single crystal substrate is used, controllability of impurity addition is remarkably improved, and a large-area epitaxial growth film can be easily obtained by enlarging the substrate area. The aforementioned reduction in the microvibe density can be realized. However, in the vapor phase epitaxial growth method, the substrate material and the SiC are often used.
The problem is an increase in defect density due to a difference in lattice constant of the film. In particular, a common Si as a substrate used during growth
Has a large lattice constant difference from SiC,
-Twin or anti-phase region boundary surface (APB: Anti
Phase Boundary) was remarkable, which hindered the realization of the SiC semiconductor device.

3C-S by vapor phase epitaxial growth
As a method of reducing defects in the iC film, for example, a step of providing a growth region on a growth target substrate,
There has been proposed a technique for growing a C single crystal so that its thickness is equal to or greater than a thickness specific to the growth plane orientation of the substrate, and reducing plane defects after the specific thickness. (Japanese Patent Publication No. 6-41400). However, the two types of anti-phase regions included in 3C-SiC have a characteristic of expanding in a direction orthogonal to each other as the thickness of 3C-SiC increases, so that the anti-phase region boundary interface is formed. It cannot be reduced effectively. Furthermore, since the orientation of the superstructure formed on the surface of the grown 3C-SiC cannot be arbitrarily controlled, for example, when discrete growth regions are combined with each other during the growth, a new anti-reaction occurs at the joint. A phase region boundary surface is formed, and desired electrical characteristics cannot be realized.

As a method of effectively reducing the anti-phase region boundary surface, a surface normal axis is slightly inclined from the [100] direction to the [110] direction (off-angle is introduced) on a Si (001) plane substrate. A growth method has been proposed (see Abride Physics Letters, vol. 50, 1987, p. 1888). In this method, the substrate is slightly inclined, so that atomic-level steps are introduced at equal intervals in one direction.
The surface defect propagates in a direction parallel to the introduced step, while suppressing the propagation of the surface defect in a direction perpendicular to the introduced step (a direction crossing the step). As the SiC film thickness increases, of the two types of anti-phase regions included in the film, the anti-phase region expanding in the direction parallel to the introduced step becomes the anti-phase region expanding in the orthogonal direction. Since the expansion is preferentially performed as compared with the above, it is possible to effectively reduce the anti-phase region boundary surface. However, this method has a problem in that the step density at the SiC / Si interface is increased, thereby causing an unintended generation of an anti-phase region boundary surface, and the anti-phase region boundary surface is not completely eliminated. .

On the other hand, there has been proposed a method of providing a plurality of undulations extending parallel to one direction on all or a part of the surface of a substrate to be grown, and growing SiC on the surface of the substrate (Japanese Patent Laid-Open No. 2000-2000). 178740). According to this method, since the crystal surface of the SiC to be grown is introduced at a density that is statistically balanced with the steps oriented in a mirror-symmetrical orientation, the steps in the SiC layer unintentionally introduced by the steps of the surface of the substrate to be grown are introduced. The phase region boundaries are effectively associated with each other, and an SiC film in which the anti-phase region boundary is completely eliminated can be obtained. Furthermore, in this method, since the individual growth regions are all in-phase regions that expand in the same direction by introducing the off-angle, even when discrete growth regions are coupled with each other during growth, the anti-phase region remains in the coupling portion. There is an advantage that no boundary surface occurs.

However, even with a semiconductor device manufactured using a 3C-SiC substrate manufactured by using this method, desired characteristics cannot be obtained. The present inventors have conducted detailed studies on the reason, and as a result, have concluded that stacking faults on the (111) plane, which are included in a large amount in 3C-SiC, hinder the characteristics of the semiconductor device. For example, there is a difference in lattice constant of about 20% between a Si single crystal widely used as a substrate to be grown and a 3C-SiC single crystal. Therefore, a 3C-SiC single crystal is grown on a Si substrate by a conventional method. 3C-S
iC has many stacking faults on the (111) plane.

[0009]

As described above, conventionally, an SiC layer is grown on a Si (001) substrate by introducing an off angle in order to form a SiC single crystal substrate as an element forming substrate of a semiconductor device. A method and a method of growing a SiC layer on a substrate having undulations extending parallel to one direction have been proposed. However, any of the methods can be used to produce a 3C-SiC single crystal with reduced stacking faults. It is difficult to obtain with good reproducibility. Therefore, 3C-Si having such excellent crystallinity is obtained.
There is a need for a manufacturing method capable of stably supplying C single crystals on an industrial scale.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a silicon carbide single crystal substrate capable of producing a 3C—SiC single crystal with reduced stacking faults with good reproducibility. It is an object of the present invention to provide a manufacturing method and a method for manufacturing a semiconductor device using the substrate.

[0011]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, according to the present invention, in a method of manufacturing a silicon carbide single crystal substrate, a bulk crystal substrate (an ingot grown by a melt growth method of a Si substrate or the like) is cut out with a diamond blade or the like and polished to a predetermined thickness. A step of forming a plurality of undulations on at least a part of the surface of the formed wafer; and a step of epitaxially growing a cubic first SiC layer on the surface of the crystal substrate having the undulations formed thereon.
Removing the crystal substrate from the first SiC layer, flattening the surface by epitaxially growing a cubic second SiC layer on the surface of the first SiC layer exposed by removing the crystal substrate; And a step.

The present invention also provides a method of manufacturing a silicon carbide single crystal substrate, comprising the steps of: epitaxially growing a cubic first SiC layer on a surface of a bulk crystal substrate; Forming a plurality of undulations in the portion, removing the crystal substrate from the first SiC layer, and then growing a cubic second SiC layer on the undulated surface of the first SiC layer And flattening the surface.

Here, preferred embodiments of the present invention include the following. (1) The bulk crystal substrate is made of Si, Ge, or SiGe.

(2) The plurality of undulations formed on the surface of the crystal substrate are line-and-space in which the top and bottom are formed continuously in one direction and the top and bottom are periodically arranged at regular intervals. Be a pattern. (3) The plurality of undulations formed on the surface of the first SiC layer is a line-and-space shape in which the top and bottom are formed continuously in one direction and the top and bottom are periodically arranged at regular intervals. Be a pattern.

(4) The plurality of undulations formed on the surface of the crystal substrate is a line and space shape in which the top and bottom are formed continuously in one direction and the top and bottom are periodically arranged at regular intervals. The patterns must be grid-like patterns that are orthogonal to each other. (5) The plurality of undulations formed on the surface of the first SiC layer is a line-and-space shape in which the top and bottom are formed continuously in one direction and the top and bottom are periodically arranged at regular intervals. The patterns must be grid-like patterns that are orthogonal to each other.

(6) The plane orientation of the crystal substrate is (001), and the line and space pattern is inclined several degrees from the <110> direction. (7) When removing a single crystal substrate, the substrate is mechanically polished halfway, and the remainder is etched using a solution.

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
Forming a cubic n ⁺ -type SiC single crystal substrate composed of a C layer; and forming a cubic n ⁻ on the SiC single crystal substrate.
And epitaxially growing the type SiC layer.

(Operation) According to the present invention, a first cubic S is formed on the surface of a bulk crystal substrate having a plurality of undulations.
By removing the crystal substrate from the first SiC layer after epitaxially growing the iC layer, a SiC layer having a plurality of undulations on the surface can be formed.

Here, since the surface layer of the first SiC layer is in contact with the bulk crystal substrate, it contains many crystal defects and strains. However, for example, by removing the oxide film after performing thermal oxidation or removing the outermost surface by reactive ion etching, high quality Si
The surface of the homoepitaxial substrate for growing the C single crystal has sufficient crystallinity and can serve as a substrate to be grown having a plurality of desired undulations. Since this surface has a plurality of undulations, even if twins, anti-phase region boundary surfaces, stacking faults, and the like exist on the slopes of each undulation on the surface of the SiC single crystal, the off-angle of the above-described angle can be obtained. Since the introduction effect can be obtained, the propagation of these defects in the growth direction can be effectively prevented.

In addition, according to the present invention, a plurality of undulations extending in one direction parallel to one direction as disclosed in JP-A-2000-178740 can be formed on the surface of the first SiC layer. In the surface of the SiC layer, steps oriented in a mirror-symmetric direction are introduced at a statistically balanced density. For this reason, the anti-phase region boundaries in the SiC growth layer unintentionally introduced by the step on the surface of the first SiC layer effectively associate with each other, and the second phase in which the anti-phase region boundary is almost completely eliminated. Is obtained. Furthermore, due to the effect of the introduction of the off-angle, the individual growth regions are all in-phase regions that expand in the same direction. Therefore, even when discrete growth regions are coupled with each other during growth, a step may not be generated at the coupling portion. However, there is an advantage that an antiphase region boundary does not occur.

Here, if mechanical processing means is used to form a plurality of undulations on the surface of the first SiC layer, processing damage is unexpectedly formed in the depth direction, and the crushed layer is removed. Can be difficult. In this case, undulations are formed on the surface of the bulk crystal substrate in advance, and the first S
A method of growing an iC layer and transferring the undulation to a surface exposed by removing the bulk crystal substrate from the grown SiC layer is most desirable also from the viewpoint of easy process and good reproducibility. If the crushed layer can be easily removed by a mechanical processing means, the undulation may be formed directly on the first SiC layer.

Further, according to the present invention, since the epitaxial growth of the second SiC layer on the first SiC layer having a plurality of undulations is not heteroepitaxy, stacking faults due to stress or the like caused by a difference in the lattice constant of the substrate. Therefore, a high-quality low-defect SiC single crystal substrate having excellent reproducibility can be manufactured without any factor that induces a new defect such as the above. Moreover, since the bulk crystal substrate is removed from the first SiC layer when growing the second SiC layer, the first SiC layer is removed.
The growth can be performed in a state in which no strain remains in the layer due to the difference in lattice mismatch with the bulk crystal substrate, and thus, the occurrence of stacking faults due to the lattice mismatch can be prevented.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIGS. 1 to 3 illustrate a method of manufacturing a SiC single crystal substrate according to a first embodiment of the present invention, and FIG. FIG. 2 is a sectional view showing a step of forming undulations on the surface, FIG. 2 is a plan view showing a resist pattern formed on a bulk crystal substrate,
FIG. 3 is a cross-sectional view showing the step of growing the SiC layer.

In this embodiment, a Si (001) substrate is used as the bulk crystal substrate. As shown in FIG. 1A, after the surface of the Si substrate 11 is thermally oxidized, the surface of the Si substrate 11 is 1.5 μm wide by photolithography.
A resist pattern 12 having a length of 90 mm and a thickness of 1 μm and consisting of a line and space was formed. However, the line direction in the resist pattern 12 was parallel to the direction inclined by 2 ° from the <110> direction, as shown in FIG.

This substrate was placed on a hot plate at 180 ° C.
By heating for 10 minutes, the resist pattern 12
Spreads out in the direction orthogonal to the line, and FIG.
As shown in (b), a resist pattern having a wavefront cross section in which the top and bottom of the undulation were connected by a smooth curve was obtained. Next, as shown in FIG. 1C, the undulating shape and the planar line-and-space shape of the cross section of the resist pattern 12 'were transferred to the Si substrate 11 by dry etching. Specifically, by etching the resist and the Si by the RIE method under substantially the same etching rate, the top and the bottom are continuously formed in one direction on the surface of the Si substrate 11, and the top and the bottom are formed. And line-and-space undulations 13 whose bottoms are periodically arranged at regular intervals.

Here, the resist pattern 12 formed on the Si substrate 11 is not necessarily limited to the line-and-space pattern as shown in FIG. 2A, but may be formed as shown in FIG. May be a grid-like pattern in which are orthogonal to each other.

Next, the laser remaining on the surface of the Si substrate 11 is
The dist is removed in a mixture of aqueous hydrogen peroxide and sulfuric acid.
After that, on the Si substrate 11 having the undulations 13 formed on the surface,
As shown in FIG. 3A, the formation of the first 3C-SiC layer 21 is performed.
Went long. Here, the conductivity type of the SiC layer 21 is p-type, n-type.
Any type may be used, but generally, a high concentration n-type (n ⁺
Type) is desirable.

The growth of SiC is divided into a carbonization step on the surface of the Si substrate and a SiC growth step by alternately supplying a source gas. First, in the carbonization step, the processed Si substrate 11 was heated from room temperature to 1050 ° C. for about 2 hours in a reduced-pressure acetylene atmosphere at a furnace pressure of 2.7 Pa. At this time, the supply amount of acetylene was 10 sccm. After this carbonization step, while maintaining the temperature at 1050 ° C., dichlorosilane and acetylene were alternately exposed to the substrate surface at 20 sccm for 10 seconds each and the gas supply interval was 5 seconds to grow the 3C-SiC layer 21. Was done. At this time, the furnace pressure was 2.7 Pa at the minimum and 27 Pa at the maximum.

By increasing the number of supply cycles of the source gas, the thickness of the first 3C-SiC layer 21 is increased, and
It was grown to 0 μm. The thickness of the 3C-SiC layer 21 can be appropriately changed, but is preferably 50 μm or more in order to obtain a good crystal with few defects.

Next, the above sample was taken out after cooling to room temperature, and a mixed acid of HF and HNO ₃ (HF: HNO ₃ =
7: 1), as shown in FIG.
The Si substrate 11 was removed from the first 3C-SiC layer 21. Here, when the Si substrate 11 is thick, it may be etched by using the above-described mixed acid after being mechanically polished halfway. After that, 3C-
Reactive ion etching was performed using CF ₄ (40 sccm) and O ₂ (10 sccm) as an etching gas in order to remove a high defect density layer on the outermost surface of the SiC layer 21. Instead of performing this reactive ion etching, 3C—SiC layer 2
After performing the thermal oxidation of the exposed surface of No. 1, the oxide film may be removed.

Next, the first 3C-SiC layer 21 thus processed was accommodated in a reaction vessel with the processed surface facing upward, and the second 3C-SiC layer 22 was grown.
Since the growth of SiC at this stage results in homoepitaxy, the carbonization step may be omitted. Furnace pressure 2.7 Pa
The 3C-SiC layer 21 was heated from room temperature to 1050 ° C. in about 5 minutes in a reduced-pressure acetylene atmosphere. At this time,
The supply amount of acetylene was 10 sccm. After this carbonization step, while maintaining the temperature at 1050 ° C., dichlorosilane and acetylene were exposed to the substrate surface alternately at 20 sccm for 10 seconds each, and each gas supply interval was 5 seconds to grow 3C-SiC. went. At this time, the furnace pressure was 2.7 Pa at the minimum and 27 Pa at the maximum.

Then, by increasing the number of supply cycles of the source gas, the thickness of the second 3C-SiC layer 22 is increased, and when the second 3C-SiC layer 22 is grown to 100 μm, the source supply flow rate is reduced to 5 sccm and the growth rate is substantially reduced. The last 50 μm was grown in a quarter.

Thus, according to the present embodiment, the total thickness 300
A 3 μm-μm 3C—SiC substrate was obtained. The surface of the substrate grown in this manner was subjected to AFM observation to measure the density of the anti-phase region boundary surface. As a result, no anti-phase region boundary surface was observed in the observation region. In order to examine the state of occurrence of stacking faults, the grown substrate was cleaved on the (110) plane, and the cross section was observed with a transmission electron microscope. Although it was observed, it did not propagate along the growth direction, and no stacking faults were observed at all more than 5 μm from the undulation.

As described above, according to the present embodiment, line-and-space undulations 13 are provided on the surface of the Si substrate 11, and the first 3C-SiC layer 21 is epitaxially grown thereon. 3C-SiC layer 21
The undulations can be transferred to the surface of the substrate. Then, by growing the second 3C-SiC layer 22 on the surface of the first 3C-SiC layer 21 having such undulations, twins, anti-phase region boundary surfaces, stacking faults, etc., grow in the growth direction. Propagation can be effectively prevented.

Further, since the steps oriented in mirror-symmetrical directions are introduced into the surface of the first 3C-SiC layer 21 at a statistically balanced density, the second 3C-SiC layer 22 is formed.
Is the anti-phase region boundary almost completely eliminated.
Further, no anti-phase region boundary surface occurs due to the effect of introducing the off angle. Moreover, the second substrate is removed in a state where the Si substrate 11 is removed.
3C-SiC layer 22 can be grown without any distortion remaining due to the difference in lattice mismatch between SiC and Si, thereby also preventing the occurrence of stacking faults due to the lattice mismatch. can do.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing step of the SiC single crystal substrate according to the embodiment. The same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, as shown in FIG. 4A, a first 3C-SiC
Layer 21 was grown epitaxially. The SiC growth conditions at this time were the same as in the first embodiment. That is, the Si substrate 1 was placed in a reduced-pressure acetylene atmosphere at a furnace pressure of 2.7 Pa.
1 was heated from room temperature to 1050 ° C. over about 2 hours, and then dichlorosilane and acetylene were exposed to the substrate surface alternately at 20 sccm for 10 seconds each at a gas supply interval of 5 seconds while maintaining the temperature at 1050 ° C. Then, the 3C-SiC layer 21 was grown. SiC layer 21
Was set to 150 μm as in the first embodiment.

Next, as shown in FIG.
Line-and-space undulations were formed on the surface of the layer 21. The method of forming the undulations may be the same as that formed on the Si substrate 11 in the first embodiment. That is, after forming a resist pattern composed of lines and spaces on the surface of the SiC layer 21 by using the photolithography technique, the resist pattern is deformed by a heat treatment to obtain a resist pattern shape having a wavy cross section. Then, the undulating shape and the planar line-and-space shape of the cross section of the resist pattern are transferred to the SiC layer 21 by dry etching. After that, the surface is cleaned by solution etching in order to remove a crushed layer by etching.

Next, as shown in FIG.
The Si substrate 11 was removed from the SiC layer 21. Si substrate 1
HF and HNO ₃ are removed in the same manner as in the first embodiment.
Was used.

Next, as shown in FIG. 4D, a second 3C-SiC layer 22 was epitaxially grown on the first 3C-SiC layer 21. The growth conditions at this time are the same as in the first embodiment. That is, after heating the 3C—SiC layer 21 from room temperature to 1050 ° C. in about 5 minutes in a reduced-pressure acetylene atmosphere with a furnace pressure of 2.7 Pa, the temperature is increased to 1050 ° C.
The dichlorosilane and acetylene were exposed to the substrate surface alternately at 20 sccm for 10 seconds each and the gas supply interval was 5 seconds while maintaining the second 3C-Si.
The C layer 22 was grown. The thickness of the SiC layer 22 is the first
The thickness was 150 μm as in the embodiment.

According to this embodiment, the first 3C-SiC
Since the epitaxial growth of the second 3C-SiC layer 22 is performed in a state where the surface of the layer 21 has line-and-space undulations, the same effect as in the first embodiment can be obtained.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a step of manufacturing the Schottky diode according to the embodiment. The same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, as in the first embodiment, FIG.
By the steps shown in FIGS. 3A to 3C and FIGS. 3A to 3C, a 3C-SiC substrate including the first and second 3C-SiC layers 21 and 22 was prepared. At this time, the SiC substrate was of a high concentration n type (n ⁺ type).

Next, as shown in FIG.
An n ⁻ -type 3C—SiC layer 25 was epitaxially grown on the SiC substrate 20. The growth conditions at this time may be the same as those for the growth of the second 3C-SiC layer 22 described in the first embodiment. Subsequently, as shown in FIG. 5B, an ion implantation layer 26 is formed on the surface layer of the SiC layer 25 by ion implantation of Ar, and TiAl is formed on the layer 26.
Was formed. Further, an electrode made of Pt or Au was provided on the back surface side of the SiC substrate 20.

In the Schottky diode thus formed, since the 3C-SiC substrate 20 is a high-quality crystal having no defect, the 3C-SiC layer 2 formed thereon is formed.
5 also becomes a high-quality crystal, and the element characteristics can be improved.

The present invention is not limited to the above embodiments. The growth temperature of 3C SiC is not limited to the above embodiment, and the growth can be performed in the range of 800 to 1200 ° C. In particular, 900 to obtain good crystals.
Temperatures in the range of １1100 ° C. are preferred. In the embodiment,
Although a Si substrate is used as a bulk substrate crystal, a single crystal substrate of Ge or SiGe can be used without being limited thereto. In the embodiment, the bulk substrate crystal or the first
Although the undulations are provided on the entire surface of the SiC layer, the undulations may be provided on a part of the surface when the element formation region is not the whole. Further, the shape of the undulations, the method for forming the undulations, and the like can be appropriately changed according to the specifications.

In the manufacture of a semiconductor device using the SiC single crystal substrate of the present invention, the SiC
The layer is not necessarily limited to the n ⁻ -type layer, but may be a p-type layer, and can be appropriately changed according to the element to be formed. Further, it is needless to say that the present invention can be applied not only to the Schottky diode but also to the manufacture of various elements. In addition, various modifications can be made without departing from the scope of the present invention.

[0050]

As described in detail above, according to the present invention, when manufacturing a SiC crystal substrate used as an element forming substrate, a plurality of undulations formed on the surface of a bulk crystal substrate are firstly formed.
Or a plurality of undulations are directly formed on the first 3C-SiC layer, and the first 3C-
Since the second 3C-SiC layer is epitaxially grown on the surface of the SiC layer, SiC having high crystal perfection with significantly reduced anti-phase region boundary surface and stacking faults is obtained.
A single crystal substrate can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a SiC single crystal substrate according to a first embodiment and showing a step of forming undulations on a surface of a bulk crystal substrate.

FIG. 2 is a plan view for explaining the method for manufacturing the SiC single crystal substrate according to the first embodiment and showing a resist pattern formed on the bulk crystal substrate.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the SiC single crystal substrate according to the first embodiment and illustrating a step of growing a SiC layer.

FIG. 4 is a sectional view showing a manufacturing process of the SiC single crystal substrate according to the second embodiment.

FIG. 5 is a sectional view showing a step of manufacturing the Schottky diode according to the third embodiment.

[Explanation of symbols]

11 ... Si substrate (bulk crystal substrate) 12 ... resist pattern 13 ... undulations 20 ... 3C-SiC single crystal substrate 21: first 3C-SiC layer 22: second 3C-SiC layer 25 ... n ^- -type SiC layer 26 ... Ion-implanted layer 27,28 ... Electrode

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Takashi Yotsuno, Inventor Takashi Yotsuka, Kawasaki-shi, Kanagawa 1st address, Toshiba R & D Center, Toshiba Corporation F-term (reference) 4G077 AA03 BE08 DB13 ED04 ED06 EE07 TC11 TK04 5F045 AA03 AB06 AC03 AC09 AD14 AE17 AF02 AF03 BB12 DA63

Claims (5)

[Claims] A step of forming a plurality of undulations on at least a part of a surface of a bulk crystal substrate; and a step of epitaxially growing a cubic first SiC layer on the surface of the crystal substrate on which the undulations are formed. Removing the crystal substrate from the first SiC layer; flattening the surface by epitaxially growing a cubic second SiC layer on the surface of the first SiC layer exposed by removing the crystal substrate; A method for manufacturing a silicon carbide single crystal substrate. 2. A cubic first substrate on a surface of a bulk crystal substrate.
Epitaxially growing a SiC layer of
forming a plurality of undulations on at least a portion of the surface of the iC layer; removing the crystal substrate from the first SiC layer; and then forming a cubic system on the undulated surface of the first SiC layer. Growing a second SiC layer and flattening the surface thereof. 3. The plurality of undulations formed on the surface of the crystal substrate or the first SiC layer are such that a top and a bottom are continuously formed in one direction, and the top and the bottom are periodically arranged at regular intervals. 3. The method of manufacturing a silicon carbide single crystal substrate according to claim 1, wherein the pattern is a line and space pattern. 4. A plurality of undulations formed on the surface of the crystal substrate or the first SiC layer, a top and a bottom are formed continuously in one direction, and the top and the bottom are periodically arranged at regular intervals. 3. The method for manufacturing a silicon carbide single crystal substrate according to claim 1, wherein the line-and-space pattern is a lattice-like pattern which is orthogonal to each other. 5. A step of forming a cubic n ⁺ -type SiC single crystal substrate comprising first and second SiC layers by the method according to claim 1, and said SiC single crystal. Epitaxially growing a cubic n ⁻ -type SiC layer on a substrate.