JP2002198543A - Package for optical semiconductor element - Google Patents

Package for optical semiconductor element

Info

Publication number
JP2002198543A
JP2002198543A JP2000396304A JP2000396304A JP2002198543A JP 2002198543 A JP2002198543 A JP 2002198543A JP 2000396304 A JP2000396304 A JP 2000396304A JP 2000396304 A JP2000396304 A JP 2000396304A JP 2002198543 A JP2002198543 A JP 2002198543A
Authority
JP
Japan
Prior art keywords
dielectric
optical
wiring layer
optical semiconductor
signal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000396304A
Other languages
Japanese (ja)
Other versions
JP4771588B2 (en
Inventor
Masanobu Ishida
政信 石田
Mitsuo Yanagisawa
美津夫 柳沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000396304A priority Critical patent/JP4771588B2/en
Publication of JP2002198543A publication Critical patent/JP2002198543A/en
Application granted granted Critical
Publication of JP4771588B2 publication Critical patent/JP4771588B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Optical Couplings Of Light Guides (AREA)
  • Light Receiving Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a package for an optical semiconductor element which can enhance the optical-to-electrical signal transducing speed and which can make the optical-to-electrical transducing speed high and smooth. SOLUTION: The housing package is provided with a bottom plate 2 having a mounting part 2a in which the optical semiconductor element 3 is mounted on the surface; a frame body 7 which is attached to, and mounted on, the bottom plate 2 so as to surround the mounting part 2a; a fixing member 11 which is attached to, and mounted on, a through hole 7b arranged and installed in the sidewall of the frame body 7, and which has a through hole 11a at the inside into which the transmission line 10 of a light signal is inserted; a first dielectric 16 which is formed so as to pass the frame body 7 and in which a signal wiring layer 18 is formed on the surface; an input/output terminal 24 for a second dielectric 17 which is bonded to the first dielectric 16 by sandwiching the wring layer 18, in such a way that both ends of the wiring layer 18 are exposed and which is arranged between the first dielectric 16 and the frame body 7 so as to pass the frame body 7 and a lid body 9 which is attached to, and mounted on, the surface of the frame body 7 and which airtightly seals the elements 3. A gap 26 is formed just under the exposed part 18a of the wiring layer 18 at the first dielectric 16.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明が属する技術分野】本発明は、光半導体素子を収
納する光半導体素子収納用パッケージに関し、特に、パ
ッケージ内から信号を入出力するための入出力端子の改
良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device housing package for housing an optical semiconductor device, and more particularly to an improvement of an input / output terminal for inputting / outputting a signal from inside the package.

【0002】[0002]

【従来技術】近年、光通信分野等で用いられる各種光半
導体素子を収納した光半導体収納用パッケージ(以下、
光パッケージという)が注目されている。かかる光パッ
ケージの一般的な構造は、図3の概略断面図に示すよう
に、金属製の基板30の上面に絶縁基体31の表面に光
半導体素子(以下、光素子と略す。)32が搭載される
実装基板33を載置する載置部30aを囲繞するように
金属製の枠体35が基板30の表面に接合、固定されて
いる。また、枠体35の上面には光素子32を気密に封
止するための蓋体36が配設され、基板30、枠体35
および蓋体36によって光素子32が気密に封止されて
いる。
2. Description of the Related Art In recent years, an optical semiconductor housing package (hereinafter, referred to as an optical semiconductor device) housing various optical semiconductor elements used in the field of optical communication and the like.
Optical package) is attracting attention. The general structure of such an optical package is, as shown in a schematic sectional view of FIG. 3, an optical semiconductor element (hereinafter abbreviated as an optical element) 32 mounted on an upper surface of a metal substrate 30 and a surface of an insulating base 31. A metal frame 35 is joined and fixed to the surface of the substrate 30 so as to surround the mounting portion 30 a on which the mounting substrate 33 to be mounted is mounted. Further, a lid 36 for hermetically sealing the optical element 32 is provided on the upper surface of the frame 35, and the substrate 30, the frame 35
The optical element 32 is hermetically sealed by the lid 36.

【0003】また、枠体35の側壁には貫通孔35aが
設けられ、枠体35の該貫通孔35aを囲む外壁面に
は、内部に光ファイバ等の光信号の伝送線路(以下、光
線路と略す。)37を挿入するための貫通孔38aを有
する固定部材38が接着、固定されており、固定部材3
8の貫通孔38a内に挿入された光線路37の先端から
出力された光信号を光素子32にて受光するように配置
されている。なお、光線路37は固定部材38の貫通孔
38a内に充填される半田等の接着剤39によって固定
部材38と接着される。
Further, a through hole 35a is provided in a side wall of the frame 35, and a transmission line (hereinafter referred to as an optical line) of an optical signal such as an optical fiber is provided inside an outer wall surrounding the through hole 35a of the frame 35. A fixing member 38 having a through hole 38a for inserting the 37 is adhered and fixed.
The optical element 32 is arranged to receive the optical signal output from the tip of the optical path 37 inserted into the through hole 38 a of the optical element 8. The optical path 37 is bonded to the fixing member 38 by an adhesive 39 such as solder filled in the through hole 38a of the fixing member 38.

【0004】一方、光素子32にて受光した信号は、実
装基板33に形成された配線回路(図示せず)やワイヤ
ボンディング40を介して、枠体35の側壁を貫通する
ように形成された2つの誘電体41、42間に信号配線
層43を形成した入出力端子44の該信号配線層43の
露出部と接続され、さらに、信号配線層43の他端の露
出部は、枠体35の外に形成されたリード端子45と接
続されて、リード端子45によって外部回路(図示せ
ず)とパッケージとを接続する構成からなる。
On the other hand, a signal received by the optical element 32 is formed so as to penetrate the side wall of the frame 35 via a wiring circuit (not shown) formed on the mounting substrate 33 or a wire bonding 40. The input / output terminal 44 having the signal wiring layer 43 formed between the two dielectrics 41 and 42 is connected to the exposed portion of the signal wiring layer 43, and the other end of the signal wiring layer 43 is connected to the frame 35. Is connected to a lead terminal 45 formed outside the package, and an external circuit (not shown) is connected to the package by the lead terminal 45.

【0005】また、入出力端子44の構造は、誘電体4
1の上面の中央部に信号配線層43を形成し、かつ誘電
体41の下面にグランド層(接地導体層)47を形成し
て、信号配線層43とグランド層47とによってマイク
ロストリップ線路が形成されており、また、誘電体42
は信号配線層43を挟んで誘電体41と接合されるとと
もに、信号配線層43の両端が露出するように誘電体4
2が誘電体41よりも短く形成された、いわゆるフィー
ドスル構造からなる。
[0005] The structure of the input / output terminal 44 is the same as that of the dielectric 4.
The signal wiring layer 43 is formed in the center of the upper surface of the first substrate 1, and the ground layer (ground conductor layer) 47 is formed on the lower surface of the dielectric 41. A microstrip line is formed by the signal wiring layer 43 and the ground layer 47. And the dielectric 42
Are bonded to the dielectric 41 with the signal wiring layer 43 interposed therebetween, and the dielectric 4 is connected so that both ends of the signal wiring layer 43 are exposed.
2 has a so-called feed-through structure formed shorter than the dielectric 41.

【0006】[0006]

【発明が解決しようとする課題】上記光半導体素子収納
用パッケージにおいては、光半導体素子およびそれに接
続される接続回路にて処理される光−電気の変換効率を
高めるために、パッケージ内で発生する容量(C)成分
を低減する必要があるが、上述した従来の光半導体素子
収納用パッケージでは、パッケージで発生する容量成分
が大きく、特に、上述した枠体の側壁を貫通するように
形成され、ライン長の長いフィードスルー部の信号配線
層の部分にて大きな容量が発生することから、光−電気
の変換速度が遅くなるために信号の処理能力が低下する
という問題があった。
In the above-mentioned optical semiconductor element housing package, the optical semiconductor element is generated in the package in order to increase the efficiency of photoelectric conversion performed by the optical semiconductor element and the connection circuit connected thereto. Although it is necessary to reduce the capacitance (C) component, the above-described conventional package for housing an optical semiconductor element has a large capacitance component generated in the package, and is particularly formed so as to penetrate the side wall of the frame described above. Since a large capacitance is generated in the signal wiring layer portion of the feedthrough portion having a long line length, there is a problem that the signal-processing capability is reduced due to a decrease in the optical-electric conversion speed.

【0007】本発明は、上記課題を解決するためになさ
れたものであり、その目的は、光−電気信号の変換速度
を向上でき、光−電気信号を高速に、かつ円滑に授受す
ることが可能な光半導体素子収納用パッケージを提供す
ることにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve the conversion speed of an optical-electrical signal and to transmit and receive optical-electrical signals at high speed and smoothly. It is an object of the present invention to provide a package for storing an optical semiconductor element.

【0008】[0008]

【課題を解決するための手段】本発明者等は、上記課題
に対し、上記入出力端子の構造について検討した結果、
該入出力端子の信号配線層が露出した部分の直下に位置
する誘電体に空隙部を形成することによって、信号配線
層にて発生する容量成分を低減でき、パッケージ全体と
しての容量成分を低減する結果、光−電気信号の変換速
度を向上して、光−電気信号を高速に、かつ円滑に授受
することができることを知見した。
The present inventors have studied the structure of the input / output terminals with respect to the above-mentioned problems.
By forming a void in the dielectric positioned immediately below the portion where the signal wiring layer of the input / output terminal is exposed, the capacitance component generated in the signal wiring layer can be reduced, and the capacitance component of the entire package is reduced. As a result, they have found that the conversion speed of the optical-electrical signal can be improved, and the optical-electrical signal can be transmitted and received at high speed and smoothly.

【0009】すなわち、本発明の光半導体素子収納用パ
ッケージは、上面に光半導体素子が搭載される搭載部を
有する底板と、前記光半導体素子搭載部を囲むように前
記底板表面に取着される枠体と、該枠体の側壁を貫通し
て形成されるか、または該枠体の側壁に配設された貫通
孔に取着され、かつ内部に光信号の伝送線路を挿入する
ための貫通孔を有する筒状の固定部材と、前記枠体を貫
通して形成され、かつ表面に前記光半導体素子と電気的
に接続される信号配線層を形成した第1の誘電体と、該
第1の誘電体の信号配線層の両端が露出するように前記
信号配線層を挟んで前記第1の誘電体と接合され、該第
1の誘電体と前記枠体との間に配設される第2の誘電体
と、を備えた入出力端子と、前記枠体の上面に取着さ
れ、前記光半導体素子を気密に封止する蓋体と、を具備
するものであって、前記第1の誘電体の前記信号配線層
の露出部の直下に空隙部を形成したことを特徴とするも
のである。
That is, the optical semiconductor element housing package of the present invention is attached to the bottom plate surface so as to surround the optical semiconductor element mounting part, the bottom plate having a mounting part on which the optical semiconductor element is mounted on the upper surface. A frame, and a through hole formed through the side wall of the frame or attached to a through hole provided in the side wall of the frame and for inserting an optical signal transmission line therein. A first dielectric having a cylindrical fixing member having a hole, a first dielectric formed through the frame, and having on its surface a signal wiring layer electrically connected to the optical semiconductor element; The first signal line is bonded to the first dielectric with the signal line layer interposed therebetween such that both ends of the signal line layer of the dielectric are exposed, and the second line is disposed between the first dielectric and the frame. An input / output terminal comprising: a second dielectric; and an optical semiconductor element attached to an upper surface of the frame. The be one which includes a lid for sealing hermetically, and is characterized in that the formation of the void portion just below the exposed portion of the signal wiring layer of the first dielectric.

【0010】ここで、前記空隙部を形成した直上の前記
信号配線層の実効誘電率が8以下であること、前記第1
の誘電体全体の厚み(t1)に対する前記空隙部の厚み
(t2)の比(t2/t1)が0.1以上であること、前
記第1の誘電体全体の厚み(t 1)が0.25〜1mm
であること、前記信号配線層の幅(w2)に対する前記
空隙部の幅(w1)の比(w1/w2)が2.5以上であ
ることが望ましい。
[0010] Here, the space just above the space is formed.
The signal wiring layer has an effective dielectric constant of 8 or less;
Thickness of the entire dielectric (t1Thickness of the void portion with respect to)
(TTwo) Ratio (tTwo/ T1) Is 0.1 or more, before
The thickness of the entire first dielectric (t) 1) Is 0.25 to 1 mm
And the width of the signal wiring layer (wTwoAbove)
The width of the gap (w1) Ratio (w1/ WTwo) Is 2.5 or more
Is desirable.

【0011】[0011]

【発明の実施の形態】本発明の光半導体素子収納用パッ
ケージ(以下、光パッケージと略す。)の一例につい
て、その概略断面図である図1および入出力端子の概略
斜視図である図2を基に説明する。
FIG. 1 is a schematic sectional view of an example of an optical semiconductor element housing package (hereinafter, abbreviated as an optical package) according to the present invention, and FIG. 2 is a schematic perspective view of an input / output terminal. I will explain based on.

【0012】図1の光パッケージ1によれば、底板2の
上面に、表面に光半導体素子3が搭載された絶縁基体4
からなる実装基板5を載置するための載置部2aを囲繞
するように金属製の枠体7が、溶接または半田等の接続
部材を介して底板2の表面に取着、固定されている。ま
た、枠体7の上面には光半導体素子(以下、光素子と略
す。)3を気密に封止するための蓋体9が配設され、底
板2、枠体7および蓋体9によって光素子3が気密に封
止されている。
According to the optical package 1 of FIG. 1, an insulating substrate 4 on which an optical semiconductor element 3 is mounted is provided on the upper surface of the bottom plate 2.
A metal frame 7 is attached to and fixed to the surface of the bottom plate 2 via a connection member such as welding or solder so as to surround the mounting portion 2a for mounting the mounting substrate 5 made of. . A lid 9 for hermetically sealing an optical semiconductor element (hereinafter, abbreviated as an optical element) 3 is provided on an upper surface of the frame 7, and the bottom plate 2, the frame 7, and the lid 9 provide light. The element 3 is hermetically sealed.

【0013】さらに、枠体7の側壁には貫通孔7aが設
けられ、該貫通孔7aを囲む枠体7の外壁面には、内部
に光ファイバ等の光信号の伝送線路(以下、光線路と略
す。)10を挿入するための貫通孔11aを有する固定
部材11が接着、固定されて、枠体7の貫通孔7aと固
定部材11の貫通孔11aが連結して配設されている。
Further, a through hole 7a is provided in a side wall of the frame 7, and a transmission line (hereinafter referred to as an optical line) of an optical signal such as an optical fiber is provided inside an outer wall surface of the frame 7 surrounding the through hole 7a. A fixing member 11 having a through-hole 11a for inserting the 10 is adhered and fixed, and the through-hole 7a of the frame 7 and the through-hole 11a of the fixing member 11 are connected to each other.

【0014】そして、固定部材11の貫通孔11a内に
挿入された光線路10の先端から出力された光信号を光
素子3にて受光するように配置されている。なお、光線
路10は固定部材11の貫通孔11a内に充填される半
田等の接着剤13によって固定部材11と接着される。
The optical element 3 is arranged to receive an optical signal output from the tip of the optical line 10 inserted into the through hole 11 a of the fixing member 11. The optical line 10 is bonded to the fixing member 11 by an adhesive 13 such as solder filled in the through hole 11a of the fixing member 11.

【0015】一方、光素子3は、実装基板5に形成され
た配線回路(図示せず)やワイヤボンディング15を介
して、枠体7の側壁を貫通して形成され、両端が第1の
誘電体16上面から露出するとともに、枠体7の側壁部
において第1の誘電体16と第2の誘電体17との2つ
の誘電体16、17間に挟持された信号配線層18の露
出部18aと接続されている。
On the other hand, the optical element 3 is formed through a side wall of the frame 7 via a wiring circuit (not shown) formed on the mounting substrate 5 and a wire bonding 15, and both ends are formed of a first dielectric. The exposed portion 18a of the signal wiring layer 18 exposed from the upper surface of the body 16 and sandwiched between the two dielectrics 16 and 17 of the first dielectric 16 and the second dielectric 17 on the side wall of the frame 7 Is connected to

【0016】また、信号配線層18は、第1の誘電体1
6上にて枠体7の外に形成されたリード端子20と銀ロ
ウ等のロウ材による接合によって接続されており、リー
ド端子20によって外部回路(図示せず)と光パッケー
ジ1とが接続されている。
The signal wiring layer 18 is formed of the first dielectric 1
The lead terminal 20 formed outside the frame 7 on the frame 6 is connected by joining with a brazing material such as silver brazing, and an external circuit (not shown) and the optical package 1 are connected by the lead terminal 20. ing.

【0017】さらに、第1の誘電体16上面に形成され
る信号配線層18は、特に、インダクタンスを小さくす
る等の理由から光線路10と同一線上に配置され、かつ
誘電体16、17との熱膨張差に起因する信号配線層1
8への応力の発生を抑制して信号配線層18を伝送する
信号の伝送特性が劣化することを防止するために、第1
の誘電体16上面の中央部に形成され、また、第1の誘
電体16の下面(信号配線層18を形成する面と反対の
底面)には、接地導体層(グランド層)22が形成され
て、信号配線層18とグランド層22とによってマイク
ロストリップ線路が形成されており、また、第1の誘電
体16、第2の誘電体17、信号配線層18およびグラ
ンド層22とによって、光パッケージ1の内部と外部を
接続する入出力端子24を形成している。
Further, the signal wiring layer 18 formed on the upper surface of the first dielectric 16 is arranged on the same line as the optical line 10 particularly for the purpose of reducing the inductance and the like. Signal wiring layer 1 caused by thermal expansion difference
In order to suppress the generation of stress on the transmission line 8 and prevent the transmission characteristics of the signal transmitted through the signal wiring layer 18 from deteriorating, the first
A ground conductor layer (ground layer) 22 is formed on the lower surface of the first dielectric 16 (the bottom opposite to the surface on which the signal wiring layer 18 is formed). Thus, a microstrip line is formed by the signal wiring layer 18 and the ground layer 22, and the optical package is formed by the first dielectric 16, the second dielectric 17, the signal wiring layer 18 and the ground layer 22. 1 form an input / output terminal 24 for connecting the inside and the outside.

【0018】(空隙部)本発明によれば、上記入出力端
子24において、第1の誘電体16の信号配線層18形
成部のうち、露出部18aの直下に位置する第1の誘電
体16に空隙部26を形成したことが大きな特徴であ
り、これによって、信号の伝送特性に関わる第1の誘電
体16の実効誘電率を小さくでき、信号配線層18にて
発生する容量成分を低減できることから、パッケージ全
体1としての容量成分を低減できる。その結果、 T=2.19CR (ただし、T:受光感度を示す立ち上がり値(光信号を
電気信号に変換する効率値)、C:パッケージ(配線全
体+光素子)の容量、R:(配線全体+光素子)の抵抗
値)で示される光−電気信号の変換速度を向上して、光
−電気信号を高速に、かつ円滑に授受することができ
る。
(Void) According to the present invention, in the input / output terminal 24, the first dielectric 16 located immediately below the exposed portion 18a in the portion where the signal wiring layer 18 of the first dielectric 16 is formed. The main feature is that the air gap 26 is formed in the first dielectric 16, whereby the effective dielectric constant of the first dielectric 16 relating to signal transmission characteristics can be reduced, and the capacitance component generated in the signal wiring layer 18 can be reduced. Therefore, the capacitance component of the entire package 1 can be reduced. As a result, T = 2.19CR (where, T: a rise value indicating light receiving sensitivity (an efficiency value for converting an optical signal into an electric signal), C: the capacity of the package (entire wiring + optical element), and R: (entire wiring) The conversion speed of the optical-electrical signal represented by the resistance value of the + optical element) can be improved, and the optical-electrical signal can be transmitted and received at high speed and smoothly.

【0019】ここで、空隙部26の形状は、矩形状、碗
状等いずれの形状でもよいが、製造の容易性の点および
空隙部の容積を増す上では矩形形状であることが望まし
い。また、その角部にはR部やテーパーが設けられてい
てもよい。なお、空隙部26は第1の誘電体16の内部
に設けられていてもよいが、製造の容易性の点で第1の
誘電体16の底面に切り欠きとして形成されることが望
ましい。
Here, the shape of the gap portion 26 may be any shape such as a rectangular shape and a bowl shape, but is desirably a rectangular shape from the viewpoint of ease of production and increasing the volume of the gap portion. Further, an R portion or a taper may be provided at the corner. The void 26 may be provided inside the first dielectric 16, but is preferably formed as a cutout on the bottom surface of the first dielectric 16 in terms of ease of manufacture.

【0020】また、空隙部26の厚さ(高さ)は、容量
成分の低減の点および第1の誘電体16の機械的強度を
維持する点で、第1の誘電体16全体の厚み(t1)に
対する空隙部26の厚み(t2)の比(t2/t1)が
0.1以上、特に0.3以上、さらに0.5以上である
ことが望ましい。なお、第1の誘電体16の厚み
(t1)は、容量成分の低減の点および機械的強度を維
持する点で、0.25〜2mm、特に0.36〜1mm
であることが望ましい。
The thickness (height) of the gap 26 is determined by the thickness (height) of the entire first dielectric 16 from the viewpoint of reducing the capacitance component and maintaining the mechanical strength of the first dielectric 16. t ratio of the thickness of the gap portion 26 with respect to 1) (t 2) (t 2 / t 1) of 0.1 or more, particularly 0.3 or more, it is desirable that more than 0.5. In addition, the thickness (t 1 ) of the first dielectric 16 is 0.25 to 2 mm, particularly 0.36 to 1 mm in terms of reducing the capacitance component and maintaining the mechanical strength.
It is desirable that

【0021】一方、空隙部26の幅(w1)は、特に、
容量成分の低減の点で信号配線層18の幅(w2)に対
する比(w1/w2)が2.5以上、特に第1の誘電体1
6の強度を維持するためには2.5〜3であることが望
ましい。
On the other hand, the width (w 1 ) of the gap 26 is
In terms of reducing the capacitance component, the ratio (w 1 / w 2 ) to the width (w 2 ) of the signal wiring layer 18 is 2.5 or more, especially the first dielectric 1
In order to maintain the strength of No. 6, it is desirable that it is 2.5 to 3.

【0022】さらには空隙部26の幅(w1)を第1の
誘電体16の幅(w3)と同じとする、すなわち、空隙
部26の両側端が開放されたものであってもよいが、強
度の観点および信号配線層18を伝送する信号の伝送特
性を向上させるためには、第1の誘電体16の幅方向の
断面が凹部をなし、該凹部内が空隙部18となるように
形成される、すなわち、空隙部26の幅(w1)が第1
の誘電体16の幅(w3)よりも小さく形成されている
ことが望ましい。
Further, the width (w 1 ) of the gap 26 may be the same as the width (w 3 ) of the first dielectric 16, that is, both ends of the gap 26 may be open. However, in order to improve the strength and the transmission characteristics of the signal transmitted through the signal wiring layer 18, the cross section of the first dielectric 16 in the width direction forms a concave portion, and the inside of the concave portion becomes the void portion 18. In other words, the width (w 1 ) of the gap 26 is the first
It is preferable that the width of the dielectric 16 is smaller than the width (w 3 ).

【0023】さらに、空隙部26の長さ(d)は第1の
誘電体16の信号配線層18形成面の露出部18aの長
さに依存し、特に、容量の低減、強度の点で空隙部26
の長さ(d)と第1の誘電体16の信号配線層18形成
面の露出部18aの長さと同じであることが望ましい。
なお、該露出部18aは信号配線層18と接続されるリ
ード端子20やワイヤボンディング15との接続信頼性
の点で、例えば、片方の長さが0.5〜2mm、特に
0.8〜1.5mmにて形成されるが、空隙部26の長
さ(d)は0.2〜2mm、特に0.5〜1.5mmで
あることが望ましい。なお、2つの露出部18aの長さ
は必ずしも同じである必要はなく、信号配線層18に接
続されるリード端子20やワイヤボンディング15との
接続状態によって変わりうる。
Further, the length (d) of the gap 26 depends on the length of the exposed portion 18a on the surface of the first dielectric 16 on which the signal wiring layer 18 is formed. Part 26
Is preferably the same as the length (d) of the first dielectric 16 and the length of the exposed portion 18a on the surface of the first dielectric 16 on which the signal wiring layer 18 is formed.
The exposed portion 18a has a length of, for example, 0.5 to 2 mm, particularly 0.8 to 1 in terms of connection reliability with the lead terminal 20 and the wire bonding 15 connected to the signal wiring layer 18. The gap 26 is formed to have a length (d) of 0.2 to 2 mm, preferably 0.5 to 1.5 mm. Note that the lengths of the two exposed portions 18a do not necessarily have to be the same, and may vary depending on the connection state with the lead terminals 20 connected to the signal wiring layer 18 and the wire bonding 15.

【0024】また、上記空隙部26を形成することによ
って、空隙部26の直上に位置する信号配線層18の実
効誘電率は8以下、特に6以下となり、立ち上がり時間
(T)は空隙部26を形成しない場合の時間を100と
した時の比率(Tr比)が50以下、特に30以下とな
る。
Further, by forming the gap 26, the effective dielectric constant of the signal wiring layer 18 located immediately above the gap 26 becomes 8 or less, particularly 6 or less, and the rise time (T) of the gap 26 is reduced. The ratio (Tr ratio) is 100 or less, especially 30 or less, when the time when the film is not formed is 100.

【0025】一方、底板2は、光素子3を搭載する実装
基板4を支持する支持部材として機能し、その材質は、
鉄(Fe)−ニッケル(Ni)−コバルト(Co)合
金、銅(Cu)−タングステン(W)合金、アルミニウ
ム、Cu−Mo、Cu等の金属材料、またはセラミック
スからなる。また、枠体7および蓋体9は、底板2の熱
膨張係数に近似する金属、例えば、鉄(Fe)−ニッケ
ル(Ni)−コバルト(Co)合金等の金属材料または
セラミックスからなり、光素子3を気密に封止するとと
もに、光素子3等にて発生した熱を外部へ放熱する。
On the other hand, the bottom plate 2 functions as a support member for supporting the mounting substrate 4 on which the optical element 3 is mounted.
It is made of a metal material such as iron (Fe) -nickel (Ni) -cobalt (Co) alloy, copper (Cu) -tungsten (W) alloy, aluminum, Cu-Mo, Cu, or ceramics. The frame 7 and the lid 9 are made of a metal having a thermal expansion coefficient close to that of the bottom plate 2, for example, a metal material such as an iron (Fe) -nickel (Ni) -cobalt (Co) alloy or a ceramic. 3 is hermetically sealed, and radiates heat generated in the optical element 3 and the like to the outside.

【0026】なお、底板2、枠体7、蓋体9およびリー
ド端子20は、例えば、金属のインゴット(塊)に圧延
加工法や打ち抜き加工法等、従来周知の金属加工法を施
して形成できる。なお、これらの外表面には耐食性を高
め、かつロウ材に対する濡れ性を改善するために、金属
メッキ膜、特に厚さ2〜6μmのニッケルメッキ膜と厚
さ0.5〜5μmの金メッキ膜を順次形成することが望
ましい。
The bottom plate 2, the frame 7, the lid 9 and the lead terminals 20 can be formed by applying a conventionally known metal working method such as a rolling method or a punching method to a metal ingot. . In order to enhance the corrosion resistance and improve the wettability with respect to the brazing material, a metal plating film, particularly a nickel plating film having a thickness of 2 to 6 μm and a gold plating film having a thickness of 0.5 to 5 μm are provided on these outer surfaces. It is desirable to form them sequentially.

【0027】そして、底板2と枠体7との間、および枠
体7と蓋体9との間は、Pb系、Pb−Sn系、金(A
u)―錫(Sn)合金、Ag−Cu系、Au−Ge系の
半田等の低融点ロウ材にて接合されるか、またはシーム
溶接法等の溶接により接合される。なお、底板2、枠体
7および蓋体9がセラミックスからなる場合には該セラ
ミックスの表面にメタライズを形成して接合される。
The space between the bottom plate 2 and the frame 7 and the space between the frame 7 and the lid 9 are Pb-based, Pb-Sn-based, gold (A
u) -tin (Sn) alloy, Ag-Cu-based, Au-Ge-based solder or other low melting point brazing material, or welding by seam welding or the like. When the bottom plate 2, the frame 7 and the lid 9 are made of ceramics, they are joined by forming a metallized surface on the ceramics.

【0028】また、固定部材11は、枠体7に熱膨張係
数が近似する、例えば鉄(Fe)−ニッケル(Ni)−
コバルト(Co)合金等の金属材料からなり、その内部
の貫通孔11aには光ファイバ等の光線路10が挿入さ
れて、樹脂や半田材等の接着剤により固定部材11と光
線路10とが固定される。なお、固定部材11と光線路
10とを半田により接続する場合には、光線路10の半
田濡れ性を高めるために、予め光線路10の先端部付近
の外周面に蒸着法等の薄膜形成法によってTa、Ti、
W、Mo、Cr、Ni、Pb、Sn、Au、Pdの群か
ら選ばれる少なくとも1種のメタライズを施してから光
線路10を固定部材11内に挿入することが望ましい。
The fixing member 11 has a thermal expansion coefficient close to that of the frame 7, for example, iron (Fe) -nickel (Ni)-
An optical line 10 such as an optical fiber is inserted into a through hole 11a inside the metal member such as a cobalt (Co) alloy, and the fixing member 11 and the optical line 10 are bonded by an adhesive such as a resin or a solder material. Fixed. When the fixing member 11 and the optical line 10 are connected by soldering, in order to enhance the solder wettability of the optical line 10, a thin film forming method such as a vapor deposition method is previously applied to the outer peripheral surface near the tip of the optical line 10. By Ta, Ti,
It is preferable to insert the optical line 10 into the fixing member 11 after performing at least one metallization selected from the group consisting of W, Mo, Cr, Ni, Pb, Sn, Au, and Pd.

【0029】さらに、入出力端子24を構成する第1の
誘電体16および第2の誘電体17は、アルミナ(Al
23)、窒化アルミニウム(AlN)、コージェライ
ト、ムライト、石英、ガラスセラミックス等のセラミッ
クスやテフロン等の樹脂が適応可能であるが、中でも、
金属製の枠体7との接合性、強度の点で、セラミックス
からなることが望ましく、また、熱膨張特性の観点で枠
体7との40〜400℃における熱膨張係数の差が10
×10-6/℃以下、特に5×10-6/℃以下のセラミッ
クスからなることが望ましい。
Further, the first dielectric 16 and the second dielectric 17 constituting the input / output terminal 24 are made of alumina (Al
Ceramics such as 2 O 3 ), aluminum nitride (AlN), cordierite, mullite, quartz, glass ceramics, and resins such as Teflon are applicable.
It is desirable to be made of ceramics from the viewpoint of bondability and strength with the metal frame 7, and the difference in thermal expansion coefficient between the frame 7 and the frame 7 at 40 to 400 ° C. is 10 in terms of thermal expansion characteristics.
× 10 -6 / ° C. or less, it is preferably made in particular 5 × 10 -6 / ℃ following ceramics.

【0030】また、第1の誘電体16と第2の誘電体1
7とは焼成したセラミックス同士を接合してもよいが、
寸法精度の向上および製造の容易性の点で焼成によって
同時に形成されたものであることが望ましい。
Further, the first dielectric 16 and the second dielectric 1
7 may be used to join the fired ceramics,
It is desirable that they are formed at the same time by firing from the viewpoint of improvement in dimensional accuracy and ease of manufacture.

【0031】さらに、第1の誘電体16の表面に形成さ
れる信号配線層18およびグランド層22は、モリブデ
ン(Mo)―マンガン(Mn)、タングステン(W)、
銅(Cu)、銀(Ag)、パラジウム(Pd)、白金
(Pt)および金(Au)の群から選ばれる少なくとも
1種の金属を含有する導体層にて形成され、ペーストを
塗布して焼成するか、または金属箔等の高純度金属にて
形成される。
Further, the signal wiring layer 18 and the ground layer 22 formed on the surface of the first dielectric 16 are made of molybdenum (Mo) -manganese (Mn), tungsten (W),
It is formed of a conductor layer containing at least one metal selected from the group consisting of copper (Cu), silver (Ag), palladium (Pd), platinum (Pt), and gold (Au). Or formed of a high-purity metal such as a metal foil.

【0032】また、信号配線層18およびグランド層2
2の表面には、耐湿性向上、耐酸化性向上およびリード
端子20、ワイヤボンディング15または枠体7と電気
的な接続を行うために、Ni、Cu、Au等のメッキ膜
(図示せず)が形成されることが望ましい。さらに、信
号配線層18は銀ロウ、半田等のロウ材を介してリード
端子20およびワイヤボンディング15と接続され、ま
た、グランド層22は枠体7とロウ材等によって接合さ
れる。
The signal wiring layer 18 and the ground layer 2
2 is a plated film (not shown) of Ni, Cu, Au or the like for improving moisture resistance and oxidation resistance and electrically connecting with the lead terminals 20, the wire bonding 15 or the frame 7. Is preferably formed. Further, the signal wiring layer 18 is connected to the lead terminal 20 and the wire bonding 15 via a brazing material such as silver brazing or solder, and the ground layer 22 is joined to the frame 7 by brazing material or the like.

【0033】さらに、絶縁基体4は、アルミナ(Al2
3)、窒化アルミニウム(AlN)、コージェライ
ト、ムライト、石英、ガラスセラミックス等のセラミッ
クスやテフロン等の樹脂が適応可能であるが、中でも、
金属製の底板2や枠体7との接合性、強度の点で、セラ
ミックスからなることが望ましく、また、熱膨張特性の
観点で枠体7との40〜400℃における熱膨張係数の
差が10×10-6/℃以下のセラミックスからなること
が望ましい。
Further, the insulating base 4 is made of alumina (Al 2
O 3 ), aluminum nitride (AlN), cordierite, mullite, quartz, ceramics such as glass ceramics, and resins such as Teflon are applicable.
It is desirable to be made of ceramics from the viewpoint of bondability and strength with the metal bottom plate 2 and the frame 7, and the difference in thermal expansion coefficient between the frame 7 and the frame 7 at 40 to 400 ° C. from the viewpoint of thermal expansion characteristics. It is desirable to use ceramics of 10 × 10 −6 / ° C. or less.

【0034】また、絶縁基体4の表面(図1によれば側
面)に搭載される光素子3は、光線路10から出射され
る光信号を効率よく受信する位置に配置される。また、
実装基板5はその下面に形成したメタライズ金属層等を
介して半田および/または有機樹脂により底板2の載置
部2aに接合される。
The optical element 3 mounted on the surface (the side according to FIG. 1) of the insulating base 4 is arranged at a position where the optical signal emitted from the optical line 10 is efficiently received. Also,
The mounting substrate 5 is joined to the mounting portion 2a of the bottom plate 2 by solder and / or organic resin via a metallized metal layer formed on the lower surface thereof.

【0035】(他の形態)なお、図1によれば、底板
2、枠体7および蓋体9は別体として形成したが、本発
明はこれに限定されるものではなく、底板と枠体、また
枠体と蓋体が一体物として形成されていてもよい。
(Other Embodiments) According to FIG. 1, the bottom plate 2, the frame 7 and the lid 9 are formed separately, but the present invention is not limited to this. Alternatively, the frame and the lid may be formed as one body.

【0036】また、図1によれば、光線路10を固定す
る固定部材11が枠体7の側面に接着された構造である
が、固定部材自体が枠体7の側壁に貫通して形成されて
いてもよい。
FIG. 1 shows a structure in which a fixing member 11 for fixing the optical line 10 is bonded to the side surface of the frame 7, but the fixing member itself is formed so as to penetrate the side wall of the frame 7. May be.

【0037】さらに、図1では、光線路10から出射さ
れた光信号を受光する受光素子である光素子3のみが搭
載されているが、光素子が複数個搭載されていてもよ
く、また、逆に光線路に信号を発する発光素子が搭載さ
れていてもよい。なお、本発明によれば、光信号を電気
信号に変換する場合に特に有効であるために、光素子と
して、光線路から出射される信号を受光する受光素子を
具備することが望ましい。
Further, in FIG. 1, only the optical element 3 which is a light receiving element for receiving the optical signal emitted from the optical line 10 is mounted, but a plurality of optical elements may be mounted. Conversely, a light emitting element that emits a signal may be mounted on the optical line. According to the present invention, since it is particularly effective when converting an optical signal into an electric signal, it is desirable to provide a light receiving element for receiving a signal emitted from the optical line as the optical element.

【0038】[0038]

【実施例】まず、鉄−ニッケル−コバルト合金からな
り、外表面にニッケルメッキ膜および金メッキ膜を形成
した底板、枠体、蓋体、固定部材を準備した。
First, a bottom plate, a frame, a lid, and a fixing member made of an iron-nickel-cobalt alloy and having a nickel plating film and a gold plating film formed on the outer surface were prepared.

【0039】一方、アルミナ原料粉末に焼結助剤を添加
し、かつ適当な有機バインダや溶剤等を添加混合してス
ラリーを作製し、このスラリーを用いてドクターブレー
ド法によってグリーンシートを形成し、該グリーンシー
トの所定位置にスクリーン印刷法によって、モリブデン
(Mo)−マンガン(Mn)およびタングステン(W)
を主成分とするメタライズペーストを用いて所定の配線
層を塗布し、これを複数枚積層した後、1600℃で焼
成して光素子を実装する絶縁基板を作製した。
On the other hand, a sintering aid is added to the alumina raw material powder, and an appropriate organic binder, a solvent and the like are added and mixed to form a slurry, and a green sheet is formed using this slurry by a doctor blade method. Molybdenum (Mo) -manganese (Mn) and tungsten (W) are formed at predetermined positions on the green sheet by screen printing.
A predetermined wiring layer was applied using a metallizing paste containing as a main component, a plurality of the layers were laminated, and then fired at 1600 ° C. to produce an insulating substrate on which an optical element was mounted.

【0040】他方、上記グリーンシートにスクリーン印
刷法により焼成後の幅が0.5mmとなる信号配線層を
なす導体層を形成して第1のグリーンシートを作製し、
また、他のグリーンシートの表面にグランド層をなす導
体層を形成した後、このグリーンシートに切り欠きを形
成してコの字状とした第2のグリーンシートを作製し
た。さらに、上記グリーンシートを所定形状にカットし
て第2の誘電体をなす第3のグリーンシートを作製し
た。そして、第2のグリーンシート−第1のグリーンシ
ート−第3のグリーンシートの順に積層して1600℃
で焼成することにより、図2の入出力端子を作製した。
On the other hand, a conductor layer constituting a signal wiring layer having a width of 0.5 mm after firing is formed on the green sheet by a screen printing method to produce a first green sheet.
After forming a conductor layer forming a ground layer on the surface of another green sheet, a notch was formed in this green sheet to produce a U-shaped second green sheet. Further, the green sheet was cut into a predetermined shape to prepare a third green sheet forming a second dielectric. Then, the second green sheet, the first green sheet, and the third green sheet are laminated in this order, and are stacked at 1600 ° C.
Then, the input / output terminal of FIG. 2 was produced.

【0041】なお、上記切り欠き(空洞部)の焼成後の
形状は、図2に示す形状とし、その具体的な寸法は、第
1の誘電体の幅(w3)3mm、長さ3.5mm、第2
の誘電体の長さ1.5mm、第2の誘電体の幅について
は第1の誘電体の幅(w3)と同じとして、第1の誘電
体の信号配線層の両端部の露出長さをそれぞれ1.0m
mとした。また、空隙部の形状は、幅(w1)1.5m
m、長さ1.0mmを一定として、第1の誘電体全体の
厚み(t1)および空隙部の厚み(t2)を表1に示すよ
うに変えた入出力端子を作製した。また、焼成後のアル
ミナセラミックスの誘電率は10であった。
The shape of the cutout (hollow portion) after firing is the shape shown in FIG. 2, and the specific dimensions are the width (w 3 ) of the first dielectric 3 mm and the length 3. 5mm, 2nd
Assuming that the length of the dielectric is 1.5 mm and the width of the second dielectric is the same as the width (w 3 ) of the first dielectric, the exposed length of both ends of the signal wiring layer of the first dielectric 1.0m each
m. The shape of the gap is 1.5 m in width (w 1 ).
The input / output terminal was manufactured by changing the thickness (t 1 ) of the entire first dielectric and the thickness (t 2 ) of the void portion as shown in Table 1 while keeping m and the length 1.0 mm constant. The dielectric constant of the alumina ceramic after firing was 10.

【0042】次に、上記底板の表面に銀ロウによって枠
体を接合し、該枠体の側壁の所定位置にドリルまたはパ
ンチングメタルによって2mmφの貫通孔を形成した。
そして、該貫通孔形成部の側面に固定部材を銀ロウによ
って接合するとともに、前記入出力端子を枠体の他の側
壁に形成した貫通孔内に配設して銀ロウにより接合し
た。また、前記底板の所定位置に上記絶縁基体を半田に
よって接合した。
Next, a frame was joined to the surface of the bottom plate by silver brazing, and a through hole of 2 mmφ was formed at a predetermined position on the side wall of the frame by a drill or punching metal.
The fixing member was joined to the side surface of the through-hole forming portion by silver brazing, and the input / output terminals were arranged in through-holes formed in the other side wall of the frame, and joined by silver brazing. Further, the insulating substrate was joined to a predetermined position of the bottom plate by soldering.

【0043】そして、前記絶縁基体と前記入出力端子の
信号配線層とを金からなるワイヤボンディングにて接続
するとともに、該信号配線層にAg−Cu半田を介して
鉄−ニッケル−コバルト合金からなり、外表面にニッケ
ルメッキ膜および金メッキ膜を形成したリード端子を接
合した。
The insulating base and the signal wiring layer of the input / output terminal are connected by wire bonding made of gold, and the signal wiring layer is made of an iron-nickel-cobalt alloy via Ag-Cu solder. Then, a lead terminal having a nickel plating film and a gold plating film formed on the outer surface thereof was joined.

【0044】さらに、前記絶縁基体側面の所定位置に受
光用の光半導体素子を実装した後、枠体の上面にシーム
接合により蓋体を接合した。また、前記固定部材の貫通
孔内に蒸着法によって先端付近の外周面にTaN膜−N
iメッキ膜−Auメッキ膜を順次被着形成した光ファイ
バを挿入し、半田によって光ファイバと固定部材とを接
合、固定することにより、光半導体素子収納用パッケー
ジを作製した。
Further, after mounting an optical semiconductor device for light reception at a predetermined position on the side surface of the insulating base, a lid was bonded to the upper surface of the frame by seam bonding. Further, a TaN film-N is formed on the outer peripheral surface near the tip by a vapor deposition method in the through hole of the fixing member.
An optical fiber on which an i-plated film and an Au-plated film were sequentially formed was inserted, and the optical fiber and a fixing member were joined and fixed by soldering, thereby producing an optical semiconductor element housing package.

【0045】得られた光パッケージについて、光ファイ
バから信号を入力し、光電変換パルスパターン測定機に
よって立ち上がり時間を測定し、空隙を形成しない試料
No.1の立ち上がり値を100として、各形状におけ
る立ち上がり値(Tr値)の比(Tr比)を算出した。
また、誘電体の誘電率(ε=10)、第1の誘電体の厚
み(t1)、空隙部の厚み(t2)、信号配線層の幅
(0.5mm)、空隙部の幅(w1=1.5mm)の形
状からシュミレーションによって空隙部の直上に位置す
る信号配線層の実効誘電率を算出した。結果は表1に示
した。
For the obtained optical package, a signal was input from an optical fiber, and the rise time was measured by a photoelectric conversion pulse pattern measuring instrument. With the rising value of 1 being 100, the ratio (Tr ratio) of the rising value (Tr value) in each shape was calculated.
The dielectric constant of the dielectric (ε = 10), the thickness of the first dielectric (t 1 ), the thickness of the gap (t 2 ), the width of the signal wiring layer (0.5 mm), and the width of the gap ( From the shape of w 1 = 1.5 mm), the effective dielectric constant of the signal wiring layer located immediately above the gap was calculated by simulation. The results are shown in Table 1.

【0046】[0046]

【表1】 [Table 1]

【0047】表1の結果から明らかなように、空隙部を
形成しない試料No.1、7に比較して空隙部を形成し
た試料No.2〜6ではいずれも実効誘電率が低下し、
Tr比が100よりも小さくなる、すなわち立ち上がり
時間が短縮できることを確認した。
As is clear from the results in Table 1, Sample No. having no voids was formed. Sample No. 1 in which a gap was formed as compared with Sample Nos. 1 and 7 In any of 2 to 6, the effective permittivity decreases,
It was confirmed that the Tr ratio was smaller than 100, that is, the rise time could be shortened.

【0048】[0048]

【発明の効果】本発明の光半導体収納用パッケージによ
れば、該入出力端子の信号配線層が露出した部分の直下
に位置する誘電体に空隙部を形成することによって、信
号配線層にて発生する容量成分を低減でき、パッケージ
全体としての容量成分を低減する結果、光−電気信号の
変換速度を向上して、光−電気信号を高速に、かつ円滑
に授受することができる。
According to the package for storing an optical semiconductor of the present invention, a void is formed in a dielectric located immediately below a portion where the signal wiring layer of the input / output terminal is exposed, so that the signal wiring layer can be formed. The generated capacitance component can be reduced, and as a result of reducing the capacitance component of the entire package, the conversion speed of the optical-electric signal can be improved, and the optical-electric signal can be transmitted and received at high speed and smoothly.

【0049】[0049]

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の光半導体素子収納用パッケージの一例
を示す概略断面図である。
FIG. 1 is a schematic sectional view showing an example of an optical semiconductor element housing package of the present invention.

【図2】図1の光半導体素子収納用パッケージの入出力
端子の構造を説明するための斜視図である。
FIG. 2 is a perspective view illustrating a structure of an input / output terminal of the package for housing an optical semiconductor element of FIG. 1;

【図3】従来の光半導体素子収納用パッケージの概略断
面図である。
FIG. 3 is a schematic sectional view of a conventional package for housing an optical semiconductor element.

【符号の説明】[Explanation of symbols]

1・・・光半導体素子収納用パッケージ(光パッケー
ジ) 2・・・底板 2a・・実装基板搭載部 3・・・光半導体素子(光素子) 4・・・絶縁基体 5・・・実装基板 7・・・枠体 7a、7b・・貫通孔 9・・・蓋体 10・・光信号の伝送線路(光線路) 11・・固定部材 11a・・貫通孔 13・・接合部材 15・・ワイヤボンディング 16・・第1の誘電体 17・・第2の誘電体 18・・信号配線層 18a・・露出部 20・・リード端子 22・・グランド層 24・・入出力端子 26・・空隙部
DESCRIPTION OF SYMBOLS 1 ... Optical semiconductor element accommodation package (optical package) 2 ... Bottom plate 2a ... Mounting board mounting part 3 ... Optical semiconductor element (optical element) 4 ... Insulating base 5 ... Mounting board 7 ··· Frame 7a, 7b ··· Through hole 9 ··· Lid 10 ··· Transmission line (optical line) for optical signal 11 ··· Fixing member 11a ··· Through hole 13 ··· Joining member 15 ··· Wire bonding 16 first dielectric 17 second dielectric 18 signal wiring layer 18a exposed portion 20 lead terminal 22 ground layer 24 input / output terminal 26 gap

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】上面に光半導体素子が搭載される搭載部を
有する底板と、 前記光半導体素子搭載部を囲むように前記底板表面に取
着される枠体と、 該枠体の側壁を貫通して形成されるか、または該枠体の
側壁に配設された貫通孔に取着され、かつ内部に光信号
の伝送線路を挿入するための貫通孔を有する筒状の固定
部材と、 前記枠体を貫通して形成され、かつ表面に前記光半導体
素子と電気的に接続される信号配線層を形成した第1の
誘電体と、該第1の誘電体の信号配線層の両端が露出す
るように前記信号配線層を挟んで前記第1の誘電体と接
合され、該第1の誘電体と前記枠体との間に配設される
第2の誘電体と、を備えた入出力端子と、 前記枠体の上面に取着され、前記光半導体素子を気密に
封止する蓋体と、を具備する光半導体素子収納用パッケ
ージであって、 前記第1の誘電体の前記信号配線層の露出部の直下に空
隙部を形成したことを特徴とする光半導体素子収納用パ
ッケージ。
1. A bottom plate having a mounting portion on which an optical semiconductor element is mounted on an upper surface, a frame attached to the surface of the bottom plate so as to surround the optical semiconductor device mounting portion, and penetrating a side wall of the frame. Or a cylindrical fixing member having a through hole for inserting a transmission line of an optical signal therein, and being attached to a through hole provided in a side wall of the frame body, A first dielectric formed through the frame and having on its surface a signal wiring layer electrically connected to the optical semiconductor element, and both ends of the first dielectric signal wiring layer being exposed; And a second dielectric disposed between the first dielectric and the frame body, the second dielectric being connected to the first dielectric with the signal wiring layer interposed therebetween. An optical semiconductor device comprising: a terminal; and a lid attached to an upper surface of the frame body and hermetically sealing the optical semiconductor device. An optical semiconductor element housing package, wherein a cavity is formed immediately below an exposed portion of the signal wiring layer of the first dielectric.
【請求項2】前記空隙部を形成した直上の前記信号配線
層の実効誘電率が8以下であることを特徴とする請求項
1記載の光半導体素子収納用パッケージ。
2. The optical semiconductor element housing package according to claim 1, wherein an effective dielectric constant of said signal wiring layer immediately above said void portion is 8 or less.
【請求項3】前記第1の誘電体全体の厚み(t1)に対
する前記空隙部の厚み(t2)の比(t2/t1)が0.
1以上であることを特徴とする請求項1または2記載の
光半導体素子収納用パッケージ。
3. The ratio (t 2 / t 1 ) of the thickness (t 2 ) of the void portion to the thickness (t 1 ) of the entire first dielectric is 0.
3. The package for housing an optical semiconductor element according to claim 1, wherein the number is one or more.
【請求項4】前記第1の誘電体全体の厚み(t1)が
0.25〜1mmであることを特徴とする請求項1乃至
3のいずれか記載の光半導体素子収納用パッケージ。
4. The package according to claim 1, wherein the thickness (t 1 ) of the entire first dielectric is 0.25 to 1 mm.
【請求項5】前記信号配線層の幅(w2)に対する前記
空隙部の幅(w1)の比(w1/w2)が2.5以上であ
ることを特徴とする請求項1乃至4のいずれか記載の光
半導体素子収納用パッケージ。
5. The ratio (w 1 / w 2 ) of the width (w 1 ) of the gap to the width (w 2 ) of the signal wiring layer is 2.5 or more. 5. The package for housing an optical semiconductor element according to any one of 4.
JP2000396304A 2000-12-26 2000-12-26 Optical semiconductor element storage package Expired - Fee Related JP4771588B2 (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000396304A JP4771588B2 (en) 2000-12-26 2000-12-26 Optical semiconductor element storage package

Publications (2)

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JP2002198543A true JP2002198543A (en) 2002-07-12
JP4771588B2 JP4771588B2 (en) 2011-09-14

Family

ID=18861618

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Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011044483A (en) * 2009-08-19 2011-03-03 Kyocera Corp Package for element storage, and mounting structure
CN102736194A (en) * 2011-03-31 2012-10-17 住友大阪水泥股份有限公司 Optical device sealing structure and optical deveice manufacturing method
KR20140027517A (en) * 2011-06-29 2014-03-06 피니사 코포레이숀 Multichannel rf feedthroughs
CN111712978A (en) * 2018-02-14 2020-09-25 古河电气工业株式会社 Cap and semiconductor laser module

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JP2000353846A (en) * 1999-06-11 2000-12-19 Toshiba Electronic Engineering Corp Stem-type semiconductor laser
JP2002141596A (en) * 2000-10-31 2002-05-17 Kyocera Corp Package for containing optical semiconductor element

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JPH077166A (en) * 1993-02-22 1995-01-10 Hughes Aircraft Co Method for using high power capacitance optical receiver and photodetector dispersedly arranged
JPH0794662A (en) * 1993-09-24 1995-04-07 Sumitomo Electric Ind Ltd Lead frame
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011044483A (en) * 2009-08-19 2011-03-03 Kyocera Corp Package for element storage, and mounting structure
CN102736194A (en) * 2011-03-31 2012-10-17 住友大阪水泥股份有限公司 Optical device sealing structure and optical deveice manufacturing method
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CN111712978A (en) * 2018-02-14 2020-09-25 古河电气工业株式会社 Cap and semiconductor laser module
CN111712978B (en) * 2018-02-14 2023-05-02 古河电气工业株式会社 Cover and semiconductor laser module

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