JP2002190986A - Sold state imaging device and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed electronic shutter while reducing power consumption. SOLUTION: The solid state imaging device comprises a first generating means 112 generating a signal for resetting the potential of a pixel 102, a second generating means 112 generating a signal for reading out photocharges stored in the pixel 102, and means 103 for selecting at least any one of signals generated from the first and second generating means 112 and resetting the potential of the pixel 102 or reading out photocharges thereof wherein the selecting means 103 varies the time after selecting a reset signal generated by the first generating means 112 before selecting a reset signal generated by the second generating means 112 depending on the number of inputted start signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device and system, and more particularly to a solid-state imaging device and system such as a digital camera, a video camera, a copying machine, and a facsimile.

[0002]

2. Description of the Related Art Conventionally, there is a solid-state imaging device such as a digital camera, a video camera, a copying machine, and a facsimile equipped with an image sensor in which a solid-state imaging device including a photoelectric conversion element is arranged in one or two dimensions.

[0003] Examples of the solid-state image sensor include a CCD image sensor and a MOS image sensor. There are MOS-type image sensors that amplify a signal based on incident light, and among them, a CMOS (complimentary) that can be manufactured using a process that has good compatibility with a process of manufacturing a MOS (Metal oxide semiconductor) transistor. MOS) type sensors.

[0004] One of the methods for controlling the light accumulation time of the solid-state imaging device is a so-called electronic shutter function. This function adjusts the charge accumulation time of the imaging unit by driving it, and electronically controls the exposure time instead of the physical aperture function. In order to realize a digital camera without a mechanical shutter and a diaphragm and to reduce the cost, a high-speed electronic shutter mechanism (up to 1 / 10,000 second) capable of shooting even under strong light is required.

More specifically, the electronic shutter function is realized by resetting the signal charges stored in each solid-state imaging device at a predetermined timing different from the pixel signal reading. That is, in order to realize the electronic shutter function in the solid-state imaging device, the peripheral circuit unit is configured so that the imaging unit can be accessed for reset at a different timing from the access for reading the pixel signal. There is a need to.

(Prior Art 1) For this reason, in a conventional solid-state imaging device, as described in, for example, JP-A-5-227489 or JP-A-9-93498, row selection for reading image signals is performed. A row selection shift register for the electronic shutter function is separately provided in addition to the shift register for the electronic shutter function, thereby performing an access for resetting the imaging unit, thereby realizing the electronic shutter function.

(Prior Art 2) A solid-state image pickup device using a shift register for realizing both an image signal readout and an electronic shutter function is disclosed in Japanese Patent Application Laid-Open No. H11-220663.
No., published in Japanese Patent Application Publication No. The method described in this publication includes a selection circuit for selecting between the time of resetting and the time of reading out of the imaging unit. The selection circuit supplies start pulses having different pulse widths to the shift register at the time of resetting and at the time of reading of the imaging unit, so that the shift register can access at different timings.

More specifically, the case where the start pulse is input for one column and the case where the start pulse is input for two columns are determined according to the outputs of the registers before and after the register of the shift register which is actually selected. It is extracted and determined by a logic circuit such as a three-input NOR circuit.

[0009]

However, the prior art 1
Since the shift registers for reading the image signal and for the electronic shutter function are provided in the solid-state imaging device, the chip area is increased, and it is difficult to reduce the power consumption because each shift register is driven. There is a problem.

Further, in the prior art 2, it is necessary to insert a LOW level signal between each input pulse to make a determination. Therefore, when the electronic shutter operation is to be performed in the shortest time, a row to which a start pulse for one column is not necessarily input is required between two pulses. Therefore, the possible electronic shutter speed requires a time longer than the two-horizontal scanning period, and there is a problem that it is difficult to realize a high-speed electronic shutter.

That is, the prior art 1 and the prior art 2 are:
There is a relationship in which mutual merits are disadvantages and disadvantages are advantages.

SUMMARY OF THE INVENTION It is an object of the present invention to realize a high-speed electronic shutter with low power consumption.

[0013]

In order to solve the above-mentioned problems, the present invention provides a first generating means for generating a reset signal for resetting a potential of a pixel, and reading out a photoelectric charge stored in the pixel. The second for generating the read signal
A solid comprising: a generation unit; and a selection unit that resets the potential of the pixel by selecting at least one of the signals generated by the first and second generation units or reads out the photoelectric charge accumulated in the pixel. In the imaging apparatus, the selection unit selects a reset signal generated by the first generation unit according to the number of input start signals,
It is characterized in that the time until the readout signal generated by the second generation means is selected is changed.

According to the present invention, there is provided a first generating means for generating a reset signal for resetting a potential of a pixel, and a second generating means for generating a read signal for reading out photoelectric charges accumulated in the pixel. , At least the first and second
Selecting means for selecting any of the signals generated by the generating means and resetting the potential of the pixel or reading out the photoelectric charge accumulated in the pixel, wherein the selecting means comprises: The reset signal generated by the first generation unit is selected in accordance with the time from when the start signal is input to when the second start signal is input, and then the read signal generated by the second generation unit is selected. It is characterized in that the time until selection is changed.

Furthermore, a solid-state imaging system according to the present invention includes the above-described solid-state imaging device, an optical system that forms light on the solid-state imaging device, and a signal processing circuit that processes an output signal from the solid-state imaging device. It is characterized by having.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 "Description of Configuration" FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 101 denotes a pixel 102 having a MOS solid-state imaging device.
Are two-dimensionally arranged, for example, in a three-row × three-column array, 103 is a vertical scanning circuit for selecting a pixel row in the imaging region 101, and 105 is a start pulse sequentially supplied to the vertical scanning circuit 103. The control unit 112 generates various signals to be supplied to the vertical scanning circuit 103.
The generating unit, which is the third generating unit, 111
3 is a supply line for transmitting a signal supplied to each pixel row, 108 is a horizontal scanning circuit for selecting a pixel column in the imaging area 101, and 109 is a read from the pixel column selected by the horizontal scanning circuit 108 A voltage conversion circuit 110 for sequentially converting the converted image signals into a voltage is an amplifier for amplifying the voltage-converted image signals.

The vertical scanning circuit 103 includes a shift register having a plurality of registers 104 and each of the registers 10.
4, a counter 106 that maintains binary “0” and “1” states in response to the output of “4”, and a selected row drive that performs a read operation or a reset operation on each pixel 102 based on the output of each counter 106. Unit 107. Incidentally, the vertical scanning circuit 103 and the horizontal scanning circuit 108 constitute a selecting means.

In FIG. 1 and FIGS. 2 and 3 described below, the numbers in parentheses attached to the respective wirings are as follows:
It identifies each signal in the timing diagrams of FIGS. 4 and 5 which will be used later.

FIG. 2 is a schematic circuit diagram of the selected row driving section 107 of FIG. 1 and its periphery. Selected row driver 10
Reference numeral 7 denotes an exclusive NOR (Exclusive NOR) for logically synthesizing an output signal of the counter 106 and a pulse signal Prt for identifying a reset pulse and a transfer pulse.
: Hereinafter, referred to as “EXNOR”. ) Circuit 301;
A logical product (hereinafter, referred to as “AND”) circuit 302 as a first logical product circuit for calculating a logical product of the output signal of the register 104 and the output signal of the EXNOR circuit 104;
AND circuit 303, which is a second AND circuit for calculating the logical product of the output signal of D circuit 302 and the reset pulse generated by generation unit 112, and the output signal of AND circuit 302 and the transfer generated by generation unit 112 An AND circuit 304 which is a fourth AND circuit for calculating a logical AND with the pulse;
AN, which is a third AND circuit that calculates the logical product of the output signal of the circuit 302 and the selection pulse generated by the generation unit 112
And a D circuit 305.

The output lines 206 to 208 for the respective output signals from the AND circuits 303 to 305 are connected to the supply line 11 in FIG.
Equivalent to 1.

FIG. 3 is a schematic circuit configuration diagram of the pixel 102 of FIG. In FIG. 2, reference numeral 201 denotes a photodiode unit which is a photoelectric conversion element for generating a photoelectric charge; and 202, a transfer of the photoelectric charge generated by the photodiode unit 201 in accordance with a transfer pulse transmitted through an output line 207. MOS transistor for photo charge transfer,
Reference numeral 210 denotes a transfer area to which a photocharge is transferred under the control of the transfer MOS transistor 202; 203, an amplification MOS transistor for generating an image signal amplified according to the transferred photocharge; 204, an output line 206; A reset MOS transistor for resetting each potential of the photodiode unit 201 and the transfer region 210 in accordance with a reset pulse transmitted through the output line 205; a selection MOS transistor 205 for controlling reading of an image signal in accordance with a selection pulse transmitted through the output line 208 , 209 are signal lines from which image signals are read.

"Explanation of Operation" FIGS. 4 and 5 show FIGS.
FIG. 5 is a timing chart for explaining the operation of FIG. 5, both of which reset the potential of the pixel 102 arranged in an arbitrary pixel row, and thereafter, show signals transmitted through each signal line when performing an operation of reading out photoelectric charges. However, FIG. 4 is a timing chart when the accumulation time of the photocharge is shortened, and FIG. 5 is a timing chart when the accumulation time of the photocharge is increased.

First, the operation in FIG. 4 will be described. First, one start pulse VST and one drive pulse PV having a wide pulse width are supplied from the control unit 105 to the vertical scanning circuit 1.
03 (FIG. 4 (1), (2)). On the side of the vertical scanning circuit 103, these pulses are sequentially stored in the register 1
04 is input. Then, the register 104 outputs a signal synchronized with the drive pulse PV while the start pulse VST is at the high level ((3) in FIG. 4).

During the above series of operations, the counter 106 outputs "0" (FIG. 4 (4)), and the generator 112 outputs the pulse signal Prt, which has been switched between high level and low level. The reset pulse RES, the transfer pulse TX, and the selection pulse SEL are output to the vertical scanning circuit 103 side (FIGS. 4 (8) to (10)).

As shown in FIGS. 4 (5) and (8), the pulse signal Prt is a signal synchronized with the rise of the reset pulse RES, and is a signal for distinguishing the reset pulse from the transfer pulse. .

Next, the counter 106 has the register 10
4 is input, and a signal in which “0/1” is switched in accordance with the rise of the signal is selected as the selected row driver 10.
7 (FIG. 4 (4)). Here, the counter 106 switches “0” to “1”. On the selected row driving unit 107 side, this signal is output to the EXNOR circuit 301.
Is input to The EXNOR circuit 301 has a pulse signal Prt in addition to the output signal from the counter 106.
(FIG. 4 (5)) is input, and a signal calculated based on these signals is output to the AND circuit 302 (FIG. 4 (6)).

The AND circuit 302 is connected to the EXNOR circuit 30
1 (FIG. 4 (6)) and an output signal (FIG. 4 (3)) from the register 104, and outputs a logical product calculated based on these signals to the AND circuits 303 to 305. Output. The AND circuits 303 to 305 include the reset pulse RES, the transfer pulse TX, and the selection pulse SEL (FIGS. 4 (8) to (10)) generated by the generation unit 112 and A
An output signal from the ND circuit 302 is input, and a logical product calculated based on these signals is output to the pixel region 101 through output lines 206 to 208 (FIG. 4 (11) to
(13)).

That is, when the control unit 105 supplies a start pulse VST as shown in FIG. 4A to the vertical scanning circuit 103 configured as shown in FIG.
In FIG. 4, first, the reset pulse and the transfer pulse are output at a high level in synchronization with each other, and subsequently, the transfer pulse and the selection pulse are output at a high level in synchronization with each other (see FIG.
1) to (13)).

At this time, in the pixel 102 shown in FIG. 3, the photodiode section 201 and the transfer region 210 are first reset to the reset potential V _DD, and after the accumulation of the photocharge for approximately one clock, the photodiode section 201 is reset. Is read out to the readout line 209 based on the photocharges generated in step (1).

Next, the operation in FIG. 5 will be described. Since the configuration of the solid-state imaging device shown in FIGS. 1 to 3 does not change, the operation in FIG. 5 is basically the same as that in FIG. It is. However, as described below, the control unit 1
05, two start pulses VS having a narrow pulse width
T is output, and the accumulation time of the photocharge changes accordingly.

Specifically, first, a signal synchronized with the drive pulse PV is output while the start pulse VST is at the high level, so that the waveform of the output signal of the register 104 is different (FIG. 4 (3), FIG. 5 ( 3)). If the waveform of the output signal of the register 104 is different, the waveform of the signal output from the EXNOR circuit 301 that calculates the signal based on the signal and the pulse signal Prt is different (FIGS. 4 (6) and 5 (6)).
Therefore, the waveform of the output signal of the AND circuit 302 whose output waveform depends on the waveform of the signal output from the EXNOR circuit 301 is different (FIGS. 4 (7) and 5 (7)).

If the waveform of the output signal of the AND circuit 302 is different, the AND circuits 206 to 20 depending on the signal waveform
8 are different (FIGS. 4 (11) to (13), FIG. 5).
(11) to (13)) Eventually, the length of the photocharge accumulation time changes. In FIG. 5, the time that is twice as long as the horizontal scanning period is set as the photocharge accumulation time. For example, the third drive pulse PV in FIGS. 5A and 5B is used. If the start pulse VST is set to the high level at the fourth high level of the drive pulse PV instead of setting the start pulse VST to the high level at the high level, the accumulation of the photocharges is three times as long as the horizontal scanning period. Time, so the accumulation time of the photocharge is
The control may be performed by changing the rising timing of the start pulse VST to the high level as needed.

(Embodiment 2) FIG. 6 is a timing chart for explaining the operation of the solid-state image pickup device according to Embodiment 2 of the present invention. The timing of various signals when realizing the same photocharge accumulation time as in FIG. Is shown. Also, comparing FIG. 6 with FIG. 5, the low level time of the two high level periods differs for the start pulse VST.

That is, in FIG. 6, the start pulse VST is continuously set to the high level continuously, whereas in FIG. 4, the start pulse VST is set to the high level once, and after a short interval, the start is started. Pulse VST
Is at a high level again. In this embodiment, 1
By changing the time between the first start pulse VST and the second start pulse VST, the accumulation time of the photocharge is changed.

(Embodiment 3) FIG. 7 is a configuration diagram of a solid-state imaging system using the solid-state imaging device described in Embodiments 1 and 2. In FIG. 7, reference numeral 1 denotes a barrier that functions both as protection of the lens and as a main switch, 2 as a lens for forming an optical image of a subject on the solid-state imaging device 4, 3 as an aperture for changing the amount of light passing through the lens, and 4 as a lens. 2 is a solid-state imaging device for capturing the object formed in 2 as an image signal (corresponding to the solid-state imaging device described in each of the above-described embodiments), and 5 is various corrections to the image signal output from the solid-state imaging device 4 , An image signal processing circuit for performing processing such as clamping, 6 an A / D converter for performing analog-digital conversion of an image signal output from the solid-state image sensor 4, and 7 an A / D
A signal processing unit that performs various corrections on the image data output from the converter 6 and compresses the data. A solid-state imaging device 4, an imaging signal processing circuit 5, an A / D converter 6, and a signal processing unit 7 A timing generator that outputs a timing signal,
9 is an overall control / arithmetic unit for controlling various operations and the entire still video camera, 10 is a memory unit for temporarily storing image data, and 11 is a recording medium control interface unit for recording or reading on a recording medium. , 12 is a removable recording medium such as a semiconductor memory for recording or reading image data, and 13 is an external interface (I / F) unit for communicating with an external computer or the like.

Next, the operation of FIG. 7 will be described. When the barrier 1 is opened, the main power is turned on, then the power of the control system is turned on, and the A / D converter 6 is turned on.
The power of the imaging system circuit is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the aperture 3 and the signal output from the solid-state imaging device 4 passes through the imaging signal processing circuit 5 to the A / D converter 6. Is output. The A / D converter 6 A / D converts the signal and outputs the signal to the signal processing unit 7. The signal processing unit 7 performs an exposure calculation based on the data in the overall control / calculation unit 9.

The brightness is determined based on the result of the photometry, and the overall control / arithmetic unit 9 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 4, high-frequency components are extracted, and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not the lens is focused, and when it is determined that the lens is not focused,
The lens is driven again to measure the distance.

Then, after the focus is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 4 is corrected in an imaging signal processing circuit 5, further A / D-converted by an A / D converter 6, and passed through a signal processing unit 7 to perform overall control. The data is stored in the memory unit 10 by the operation 9. Thereafter, the data stored in the memory unit 10 is
Under the control of the overall control / arithmetic unit 9, the data is recorded on a removable recording medium 12 such as a semiconductor memory through a recording medium control I / F unit. Further, the image may be processed by inputting it directly to a computer or the like through the external I / F unit 13.

[0040]

As described above, according to the present invention,
By changing the number of input start signals or the time between input of two start signals, for example, the time from resetting of pixels to reading out can be changed.
A low power consumption and a high-speed electronic shutter can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a schematic circuit configuration diagram of a selected row driving unit and its periphery in FIG. 1;

FIG. 3 is a schematic circuit configuration diagram of the pixel of FIG. 1;

FIG. 4 is a timing chart for explaining the operation of FIGS. 1 to 3;

FIG. 5 is a timing chart for explaining the operation of FIGS. 1 to 3;

FIG. 6 is a timing chart for explaining the operation of FIGS. 1 to 3;

FIG. 7 is a configuration diagram of a solid-state imaging system using the solid-state imaging device described in the first and second embodiments.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Barrier 2 Lens 3 Aperture 4 Solid-state image sensor 5 Image signal processing circuit 6 A / D converter 7 Signal processor 8 Timing generator 9 Overall control / arithmetic unit 10 Memory unit 11 Recording medium control interface (I / F) unit 12 Recording medium 13 External interface (I / F) unit 101 Imaging area 102 Pixel 103 Vertical scanning circuit 104 Register 105 Control unit 106 Counter 107 Selected row driving unit 108 Horizontal scanning circuit 109 Voltage conversion circuit 110 Amplifier 111 Common line 112 Generation unit 201 Photo Diode section 202 Transfer MOS transistor 203 Amplification MOS transistor 204 Reset MOS transistor 205 Selection MOS transistor 206 to 208 Output line 209 Read line 301 EXNOR circuit 302 to 305 AND circuit

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 4M118 AA04 AA10 AB01 BA14 CA02 DB09 FA06 FA34 FA42 5B047 AA01 BB02 BC05 BC06 BC23 CA06 EB03 5C024 CX51 CX61 CY42 GY31 GY32 GY37 GY38 HX17 HX32 HX50 HX52 JX21

Claims (8)

[Claims] A first generation unit for generating a reset signal for resetting a potential of a pixel; and a second generation unit for generating a readout signal for reading out photoelectric charges accumulated in the pixel.
A solid comprising: a generation unit; and a selection unit that resets the potential of the pixel by selecting at least one of the signals generated by the first and second generation units or reads out the photoelectric charge accumulated in the pixel. In the imaging apparatus, the selection unit may be configured to select a reset signal generated by the first generation unit according to the number of input start signals, and then select a readout signal generated by the second generation unit. A solid-state imaging device characterized by changing time. 2. A first generating means for generating a reset signal for resetting a potential of a pixel, and a second generating means for generating a read signal for reading out photoelectric charges accumulated in the pixel.
A solid comprising: a generation unit; and a selection unit that resets the potential of the pixel by selecting at least one of the signals generated by the first and second generation units or reads out the photoelectric charge accumulated in the pixel. In the imaging apparatus, the selection unit selects a reset signal generated by the first generation unit in accordance with a time from when a first start signal is input to when a second start signal is input, A solid-state imaging device, wherein the time until the readout signal generated by the second generation unit is selected is changed. 3. The solid-state imaging device according to claim 2, wherein the selection unit includes a counter that outputs a binary signal according to the number of inputs of the start signal or a time between the first and second start signals. apparatus. 4. A first AND circuit for calculating an AND of a signal based on a binary signal output from the counter and the start signal, and an output signal of the first AND circuit and first and second 4. The solid-state imaging device according to claim 3, further comprising a second and a third AND circuit that calculates a logical product of each of the signals generated by the generating unit. 5. The image processing apparatus according to claim 1, further comprising: a third generation unit configured to generate a transfer signal for transferring a photocharge generated by a photoelectric conversion element in the pixel to a transfer region; The solid-state imaging device according to any one of claims 1 to 4, wherein one of the signals generated by the second generation unit is selected. 6. The solid-state circuit according to claim 5, further comprising: a fourth AND circuit that calculates an AND of the output signal of the first AND circuit and the signal generated by the third generating unit. Imaging device. 7. The solid-state imaging device according to claim 1, wherein the pixel includes a MOS imaging device. 8. A solid-state imaging device according to claim 1, an optical system that forms an image on the solid-state imaging device, and a signal processing circuit that processes an output signal from the solid-state imaging device. And a solid-state imaging system.