JP4401566B2 - Solid-state imaging device and system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and system, and more particularly, to a solid-state imaging device and system such as a digital camera, a video camera, a copying machine, and a facsimile.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there are solid-state imaging devices such as digital cameras, video cameras, copying machines, and facsimiles equipped with an image sensor in which solid-state imaging elements including photoelectric conversion elements are arranged one-dimensionally or two-dimensionally.
[0003]
Solid-state image sensors include, for example, CCD image sensors and MOS image sensors. MOS type image pickup devices are of a type that amplifies signals based on incident light, and among them, a CMOS (complimentary) that can be manufactured using a process having good consistency with a step of forming a metal oxide semiconductor (MOS) transistor. MOS) type sensors.
[0004]
One of the methods for controlling the light accumulation time of the solid-state imaging device is a so-called electronic shutter function. This function adjusts the charge accumulation time of the image pickup unit by driving it, and controls the exposure time electronically instead of the physical aperture function. In order to realize a digital camera that does not have a mechanical shutter and an aperture and to reduce the cost, a high-speed electronic shutter mechanism (up to 1 / 10,000 second) that can shoot even under strong light is required.
[0005]
Specifically, the electronic shutter function is realized by resetting the signal charge accumulated in each solid-state imaging device at a predetermined timing different from pixel signal readout. In other words, in order to realize the electronic shutter function in the solid-state imaging device, the peripheral circuit unit is configured so that the imaging unit can be accessed for reset at a timing different from the access for reading the pixel signal. There is a need to.
[0006]
(Prior art 1)
For this reason, in the conventional solid-state imaging device, as described in, for example, Japanese Patent Application Laid-Open No. H5-227489 or Japanese Patent Application Laid-Open No. H9-93498, an electronic device is provided separately from the row selection shift register for reading image signals. An electronic shutter function has been realized by separately providing a row selection shift register for the shutter function and thereby performing access for resetting the imaging unit.
[0007]
(Prior art 2)
Japanese Patent Application Laid-Open No. 11-220663 discloses a solid-state imaging device using a shift register that realizes both an image signal readout and an electronic shutter function. The method described in this publication includes a selection circuit that selects when the imaging unit is reset and when it is read out. The selection circuit can be accessed from the shift register at different timings by supplying a start pulse having a different pulse width to the shift register when the imaging unit is reset and when reading.
[0008]
Specifically, the output of the register before and after the register corresponding to the actually selected row in the shift register is extracted when the start pulse is input for one column and when the start pulse is input for two columns. This is determined by a logic circuit such as a 3-input NOR circuit.
[0009]
[Problems to be solved by the invention]
However, since the prior art 1 is provided with shift registers for reading image signals and for electronic shutter functions in the solid-state imaging device, the chip area is increased and the power consumption is low for driving each shift register. There is a problem that it is difficult to use electric power.
[0010]
Further, in the related art 2, it is necessary to insert a LOW level signal between the respective input pulses for discrimination. Therefore, when the electronic shutter operation is performed in the shortest time, a row in which the start pulse for one column is not necessarily input is required between the two pulses. For this reason, the electronic shutter speed that can be achieved requires a time of two or more horizontal scanning periods, which makes it difficult to realize a high-speed electronic shutter.
[0011]
That is, the prior art 1 and the prior art 2 are in a relationship in which the mutual merits are demerits and the demerits are merits.
[0012]
Accordingly, an object of the present invention is to realize a high-speed electronic shutter with low power consumption.
[0013]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides pixels including photoelectric conversion elements arranged in a matrix, signal lines from which signals from a plurality of the pixels are read, and the photoelectric conversion elements for each pixel row. A scanning circuit that selectively performs a reset operation for resetting the signal of the signal and a read operation for reading the signal of the photoelectric conversion element to the output line, and a first generation unit that generates a reset pulse for the reset operation, , and a second generating unit that generates a read pulse for the read operation, the scanning circuit comprises a shift register, one of the first, each of the signals generated by the second generating means in the solid-state imaging device including a selection means for selecting and outputting, and a control unit for supplying a start pulse to said shift register, said selection means, said from the control unit Shifutore Depending on the number of inputs of the start pulse input to the static, in the same pixel row, from the output of the reset pulse generated by said first generating means, to the output of the read pulses generated by the second generating means characterized Rukoto changing the time.
[0014]
In addition, the present invention provides a pixel including photoelectric conversion elements arranged in a matrix, a signal line from which signals from the plurality of pixels are read, and a reset for resetting the signal of the photoelectric conversion element for each pixel row A scanning circuit that selectively performs an operation and a read operation for reading a signal of the photoelectric conversion element to the output line, first generation means for generating a reset pulse for the reset operation, and for the read operation and a second generating unit that generates a read pulse, and said scanning circuit includes a shift register, said first, selecting which selects and outputs one of the signals generated by the second generating means in the solid-state imaging device including a unit, and a control unit for supplying a start pulse to said shift register, said selection means, second start from the first start pulse is input No. In response to the time until the input, in the same pixel row, from the output of the reset pulse generated by said first generating means, to the output of the read pulses generated by the second generating means time changing the characterized Rukoto.
[0015]
Furthermore, a solid-state imaging system of the present invention includes the above-described solid-state imaging device, an optical system that focuses light on the solid-state imaging device, and a signal processing circuit that processes an output signal from the solid-state imaging device. Features.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
(Embodiment 1)
"Configuration Description"
FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 101 denotes an imaging region in which pixels 102 having MOS type solid-state imaging devices are arranged in two dimensions, for example, 3 rows × 3 columns, and 103 denotes vertical scanning for selecting pixel rows in the imaging region 101. Circuit 105, a control unit that sequentially supplies a start pulse to the vertical scanning circuit 103, 112 a generation unit that is first to third generation units that generate various signals to be supplied to the vertical scanning circuit 103, 111 A supply line for transmitting a signal supplied from the vertical scanning circuit 103 to each pixel row, 108 is a horizontal scanning circuit for selecting a pixel column in the imaging region 101, and 109 is a pixel column selected by the horizontal scanning circuit 108. A voltage conversion circuit 110 sequentially converts the image signals read out from, and an amplifier 110 amplifies the voltage-converted image signal.
[0018]
The vertical scanning circuit 103 includes a shift register having a plurality of registers 104, a counter 106 that maintains binary “0” and “1” states according to the outputs of the registers 104, And a selected row driver 107 that performs a read operation or a reset operation on each pixel 102 based on the output. Incidentally, the vertical scanning circuit 103 and the horizontal scanning circuit 108 constitute selection means.
[0019]
In FIG. 1 and FIGS. 2 and 3 to be described below, numbers in parentheses attached to each wiring identify each signal in the timing diagrams of FIGS. 4 and 5 to be used later.
[0020]
FIG. 2 is a schematic circuit configuration diagram of the selected row driving unit 107 in FIG. 1 and its surroundings. The selected row driving unit 107 is referred to as an exclusive NOR (hereinafter, “EXNOR”) that logically synthesizes the output signal of the counter 106 and the pulse signal Prt for identifying the reset pulse and the transfer pulse. ) Circuit 301, a logical product (hereinafter referred to as “AND”) circuit 302 which is a first logical product circuit for calculating a logical product of the output signal of register 104 and the output signal of EXNOR circuit 104, and AND circuit 302. AND circuit 303 that is a second AND circuit that calculates a logical product of the output signal of the AND circuit 302 and the reset pulse generated by the generation unit 112, and the output signal of the AND circuit 302 and the transfer pulse generated by the generation unit 112 An AND circuit 304 that is a fourth AND circuit that calculates a logical product, an output signal of the AND circuit 302, and a selection pulse generated by the generation unit 112 And an AND circuit 305 which is a third AND circuit for calculating a logical product.
[0021]
The output lines 206 to 208 for the output signals from the AND circuits 303 to 305 correspond to the supply line 111 in FIG.
[0022]
FIG. 3 is a schematic circuit configuration diagram of the pixel 102 of FIG. In FIG. 2, reference numeral 201 denotes a photodiode portion which is a photoelectric conversion element for generating photoelectric charges, and 202 denotes transfer control of photoelectric charges generated by the photodiode portion 201 in accordance with a transfer pulse transmitted through an output line 207. A photocharge transfer MOS transistor; 210, a transfer region to which photocharge is transferred in accordance with the control of the transfer MOS transistor 202; 203, an amplification for generating an image signal amplified in accordance with the transferred photocharge A MOS transistor 204 is a reset MOS transistor that resets the potentials of the photodiode unit 201 and the transfer region 210 in accordance with a reset pulse transmitted through the output line 206, and 205 is an image signal read-out in accordance with a selection pulse transmitted through the output line 208. MOS transistor for selection that is controlled Register, 209 is a signal line for an image signal is read.
[0023]
"Description of operation"
FIGS. 4 and 5 are timing charts for explaining the operations of FIGS. 1 to 3, both of which reset the potential of the pixel 102 arranged in an arbitrary pixel row, and then perform an operation of reading out the photocharge. FIG. 4 is a timing diagram for shortening the photocharge accumulation time, and FIG. 5 is a timing diagram for increasing the photocharge accumulation time. It is.
[0024]
First, the operation in FIG. 4 will be described. First, one wide start pulse VST and drive pulse PV are output from the control unit 105 to the vertical scanning circuit 103 side (FIGS. 4 (1) and (2)). On the vertical scanning circuit 103 side, these pulses are sequentially input to the register 104. Then, the register 104 outputs a signal synchronized with the drive pulse PV while the start pulse VST is at a high level ((3) in FIG. 4).
[0025]
Note that, during the series of operations described above, the counter 106 outputs “0” (FIG. 4 (4)), and the generation unit 112 switches the pulse signal Prt that is switched between the high level and the low level, and the reset pulse RES. The transfer pulse TX and the selection pulse SEL are respectively output to the vertical scanning circuit 103 side (FIGS. 4 (8) to (10)).
[0026]
Incidentally, as shown in FIGS. 4 (5) and 4 (8), the pulse signal Prt is a signal synchronized with the rising edge of the reset pulse RES, and is a signal for identifying the reset pulse and the transfer pulse.
[0027]
Next, the counter 106 receives the output signal from the register 104, and outputs a signal in which “0/1” is switched to the selected row driver 107 side in accordance with the rising edge of the signal (FIG. 4 (4)). ). Here, the counter 106 switches “0” to “1”. This signal is input to the EXNOR circuit 301 on the selected row driving unit 107 side. In addition to the output signal from the counter 106, the EXNOR circuit 301 receives a pulse signal Prt (FIG. 4 (5)), and a signal calculated based on these signals is output to the AND circuit 302. (FIG. 4 (6)).
[0028]
The AND circuit 302 inputs the output signal (FIG. 4 (6)) from the EXNOR circuit 301 and the output signal (FIG. 4 (3)) from the register 104, and ANDs the logical product calculated based on these signals. Output to circuits 303-305. The AND circuits 303 to 305 receive the reset pulse RES, the transfer pulse TX, the selection pulse SEL (FIGS. 4 (8) to (10)) generated by the generation unit 112 and the output signal from the AND circuit 302, and these The logical product calculated based on this signal is output to the pixel region 101 side through the output lines 206 to 208 (FIGS. 4 (11) to (13)).
[0029]
That is, when the start pulse VST as shown in FIG. 4A is supplied from the control unit 105 to the vertical scanning circuit 103 configured as shown in FIG. 2, first, the reset pulse and the transfer pulse are supplied to the pixel region 101. Are synchronously output at a high level, and then the transfer pulse and the selection pulse are synchronously output at a high level (FIGS. 4 (11) to (13)).
[0030]
At this time, in the pixel 102 shown in FIG. 3, the photodiode unit 201 and the transfer region 210 are first reset to the reset potential V _DD, and subsequently generated by the photodiode unit 201 after accumulating photoelectric charge for approximately one clock. The image signal based on the photocharge is read out to the readout line 209.
[0031]
Next, the operation in FIG. 5 will be described. Since the configuration of the solid-state imaging device shown in FIGS. 1 to 3 is not changed, the operation in FIG. 5 is basically the same as that in FIG. However, as will be described below, the control unit 105 outputs two start pulses VST having a narrow pulse width, and as a result, the photocharge accumulation time changes accordingly.
[0032]
Specifically, first, since the signal synchronized with the drive pulse PV is output while the start pulse VST is at the high level, the waveform of the output signal of the register 104 is different (FIG. 4 (3), FIG. 5 (3)). . If the waveform of the output signal of the register 104 is different, the waveform of the signal output from the EXNOR circuit 301 that calculates a signal based on the signal and the pulse signal Prt is different (FIG. 4 (6), FIG. 5 (6)). Therefore, the waveform of the output signal of the AND circuit 302 whose output waveform depends on the waveform of the signal output from the EXNOR circuit 301 is different (FIG. 4 (7), FIG. 5 (7)).
[0033]
When the waveform of the output signal of the AND circuit 302 is different, the output waveforms of the AND circuits 206 to 208 depending on the signal waveform are different (FIGS. 4 (11) to (13) and FIGS. 5 (11) to (13)). Eventually, the length of photocharge accumulation changes. In FIG. 5, the time twice as long as the horizontal scanning period is the photocharge accumulation time. For example, the third drive pulse PV in FIGS. 5 (1) and (2) is used. If the start pulse VST is set to the high level at the fourth high level of the drive pulse PV instead of the start pulse VST to be set to the high level at the high level, the photocharge accumulation is performed for three times the horizontal scanning period. Since the time can be set, the photocharge accumulation time may be controlled by changing the rising timing of the start pulse VST to a high level as necessary.
[0034]
(Embodiment 2)
FIG. 6 is a timing diagram for explaining the operation of the solid-state imaging device according to the second embodiment of the present invention, and shows the timing of various signals when realizing the same photocharge accumulation time as in FIG. Further, comparing FIG. 6 with FIG. 5, regarding the start pulse VST, the low level times of the two high level periods are different.
[0035]
That is, in FIG. 6, the start pulse VST is continuously set to the high level, whereas in FIG. 4, after the start pulse VST is once set to the high level, the start pulse VST is set after a short interval. High level again. In the present embodiment, the photocharge accumulation time is changed by changing the time between the first start pulse VST and the second start pulse VST.
[0036]
(Embodiment 3)
FIG. 7 is a configuration diagram of a solid-state imaging system using the solid-state imaging device described in the first and second embodiments. In FIG. 7, 1 is a barrier that serves as a lens switch and a main switch, 2 is a lens that forms an optical image of a subject on the solid-state imaging device 4, 3 is a diaphragm for changing the amount of light passing through the lens, and 4 is a lens. 2 is a solid-state imaging device for capturing the subject imaged as an image signal (corresponding to the solid-state imaging device described in the above embodiments), and 5 is various corrections to the image signal output from the solid-state imaging device 4. , An imaging signal processing circuit that performs processing such as clamping, 6 is an A / D converter that performs analog-digital conversion of an image signal output from the solid-state imaging device 4, and 7 is an image output from the A / D converter 6. A signal processing unit 8 performs various corrections on the data and compresses the data. 8 is a timing for outputting various timing signals to the solid-state imaging device 4, the imaging signal processing circuit 5, the A / D converter 6, and the signal processing unit 7. 9 is a general control / arithmetic unit for controlling various operations and the entire still video camera, 10 is a memory unit for temporarily storing image data, and 11 is a recording unit for recording or reading on a recording medium. A medium control interface unit 12 is a detachable recording medium such as a semiconductor memory for recording or reading image data, and 13 is an external interface (I / F) unit for communicating with an external computer or the like.
[0037]
Next, the operation of FIG. 7 will be described. When the barrier 1 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 6 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the aperture 3, and the signal output from the solid-state imaging device 4 passes through the imaging signal processing circuit 5 to the A / D converter 6. Is output. The A / D converter 6 performs A / D conversion on the signal and outputs it to the signal processing unit 7. The signal processing unit 7 performs an exposure calculation by the overall control / calculation unit 9 based on the data.
[0038]
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 9 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 4, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not it is in focus. If it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
[0039]
Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 4 is corrected in the imaging signal processing circuit 5, further A / D converted by the A / D converter 6, and totally controlled through the signal processing unit 7. Accumulated in the memory unit 10 by calculation 9 Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 9. Further, the image may be processed by directly entering the computer or the like through the external I / F unit 13.
[0040]
【The invention's effect】
As described above, according to the present invention, it is possible to change the time from pixel reset to readout by changing the number of input start signals and, for example, the time between the input of two start signals. Power can be achieved and a high-speed electronic shutter can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging apparatus according to a first embodiment of the present invention.
2 is a schematic circuit configuration diagram of a selected row driving unit in FIG. 1 and its periphery. FIG.
3 is a schematic circuit configuration diagram of the pixel in FIG. 1. FIG.
FIG. 4 is a timing chart for explaining the operation of FIGS. 1 to 3;
FIG. 5 is a timing chart for explaining the operation of FIGS. 1 to 3;
FIG. 6 is a timing chart for explaining the operation of FIGS. 1 to 3;
FIG. 7 is a configuration diagram of a solid-state imaging system using the solid-state imaging device described in the first and second embodiments.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Barrier 2 Lens 3 Diaphragm 4 Solid-state image sensor 5 Imaging signal processing circuit 6 A / D converter 7 Signal processing part 8 Timing generation part 9 Overall control and calculation part 10 Memory part 11 Recording medium control interface (I / F) part 12 Recording medium 13 External interface (I / F) unit 101 Imaging area 102 Pixel 103 Vertical scanning circuit 104 Register 105 Control unit 106 Counter 107 Selected row driving unit 108 Horizontal scanning circuit 109 Voltage conversion circuit 110 Amplifier 111 Common line 112 Generation unit 201 Photo Diode section 202 Transfer MOS transistor 203 Amplification MOS transistor 204 Reset MOS transistor 205 Selection MOS transistors 206 to 208 Output line 209 Read line 301 EXNOR circuit 302 to 305 AND circuit

Claims (12)

Pixels including photoelectric conversion elements arranged in a matrix;
A signal line from which signals from a plurality of the pixels are read out;
A scanning circuit that selectively performs a reset operation for resetting the signal of the photoelectric conversion element and a read operation for reading out the signal of the photoelectric conversion element to the output line for each pixel row;
First generation means for generating a reset pulse for the reset operation ;
And a second generating unit that generates a read pulse for the read operation,
The scanning circuit includes:
A shift register;
In the solid-state imaging device provided with a selection means for selecting and outputting one of the signals generated by said first, second generation means,
A control unit for supplying a start pulse to the shift register;
The selection unit outputs a reset pulse generated by the first generation unit in the same pixel row in accordance with the number of start pulses input from the control unit to the shift register, and then generates a second generation. a solid-state imaging device according to claim Rukoto changing the time until outputting the read pulses generated by the means. Said selection means, the solid-state imaging device according to claim 1, characterized in that it comprises a counter for outputting a binary signal according to the input number of the start pulse. A first AND circuit for calculating a logical product of a signal based on the binary signal output from the counter and the start pulse ; an output signal of the first AND circuit; and first and second generation means. logical second to calculate the solid-state imaging device according to claim 2, further comprising a third logic aND circuit for each signal. Further, the pixel comprises a third generation means that generates a transfer pulse light charge generated by the photoelectric conversion element has a transfer area to be transferred, and transfers the charges of the photoelectric conversion element to the transfer region ,
It said selection means, said first, second, third solid-state imaging according to any one of claims 1 to 3, by selecting one of the generated by the generating means pulse and outputs apparatus. 5. The solid-state imaging device according to claim 4, further comprising a fourth AND circuit that calculates a logical product of the output signal of the first AND circuit and the pulse generated by the third generating unit. Pixels including photoelectric conversion elements arranged in a matrix;
A signal line from which signals from a plurality of the pixels are read out;
A scanning circuit that selectively performs a reset operation for resetting the signal of the photoelectric conversion element and a read operation for reading out the signal of the photoelectric conversion element to the output line for each pixel row;
First generation means for generating a reset pulse for the reset operation;
Second generation means for generating a read pulse for the read operation,
The scanning circuit includes:
A shift register;
A solid-state imaging device comprising: selection means for selecting and outputting any of the signals generated by the first and second generation means;
A control unit for supplying a start pulse to the shift register;
The selection unit outputs a reset pulse generated by the first generation unit in the same pixel row according to a time from when the first start pulse is input to when the second start pulse is input. A solid-state imaging device characterized in that the time until the readout pulse generated by the second generation means is output is changed. The solid-state imaging device according to claim 6, wherein the selection unit includes a counter that outputs a binary signal in response to the start pulse. A first AND circuit for calculating a logical product of a signal based on the binary signal output from the counter and the start pulse; an output signal of the first AND circuit; and first and second generation means. The solid-state imaging device according to claim 7, further comprising second and third logical product circuits for calculating a logical product with each signal. Further, the pixel includes a transfer region to which the photoelectric charge generated by the photoelectric conversion element is transferred, and includes third generation means for generating a transfer pulse for transferring the charge of the photoelectric conversion element to the transfer region,
9. The solid-state imaging according to claim 6, wherein the selection unit selects and outputs one of the pulses generated by the first, second, and third generation units. apparatus. 10. The solid-state imaging device according to claim 9, further comprising a fourth AND circuit that calculates a logical product of the output signal of the first AND circuit and the pulse generated by the third generator. The pixel is a solid-state imaging device of any one of claims 1 to 10, characterized in that it comprises a MOS type imaging device. A solid-state imaging device according to any one of claims 1 to 11 ,
An optical system for imaging light onto the solid-state imaging device;
And a signal processing circuit for processing an output signal from the solid-state imaging device.

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