JP2002185855A - Image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image sensor that can continuously output an image signal without the need for provision of a pause period for stabilizing the image signal and causing a response delay for output of the image signal in the case of outputting the image signal immediately after a pixel array by one line is selected. SOLUTION: In the image sensor using photo sensor circuits for the unit of pixels, where a MOS transistor(TR) converts a sensor current flowing through a photoelectric conversion element in response to an incident luminous quantity into a voltage signal in a weakly inverted state with a logarithmic output characteristic, when the pixel array by one line is selected and each pixel in the selected pixel array is sequentially read, the reading method is configured such that the pixel array by each one line is divided into at least two and each of the pixel division arrays for one line is deviated by a prescribed time and sequentially selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor using an optical sensor circuit for charging and discharging a parasitic capacitance of a photoelectric conversion element to obtain a sensor signal for each pixel.

[0002]

2. Description of the Related Art Conventionally, in a MOS type image sensor, an optical sensor circuit for one pixel serves as a photoelectric conversion element for generating a sensor current corresponding to the amount of incident light Ls as shown in FIG. , A transistor Q1 for charging / discharging the parasitic capacitance C, a transistor Q2 for amplifying the terminal voltage Vpd of the photodiode PD, and an image signal Vo with the pulse timing of the image signal read signal VS. Output MOS transistor Q
It consists of three. Then, the gate voltage VG of the transistor Q1 is fixed to a level for functioning as an overflow drain, and the sensor current flowing through the photodiode PD is converted into a voltage signal with a logarithmic output characteristic in a weak inversion state, thereby increasing the dynamic range. The optical signal is enlarged so that it can be detected with high sensitivity.

[0003]

The problem to be solved is that the sensor current flowing through the photoelectric conversion element according to the amount of incident light is converted into a voltage signal with logarithmic output characteristics in a weak inversion state using a MOS transistor. In an image sensor using such an optical sensor circuit, an afterimage occurs when the amount of incident light on the photoelectric conversion element decreases.

In the above-described optical sensor circuit, when the incident light Ls is incident on the photodiode PD with a sufficient amount of light, a sufficient sensor current flows through the transistor Q1, and the resistance value of the transistor Q1 is very large. Since there is no image signal, the optical signal can be detected with a sufficient response speed such that an afterimage does not occur as an image sensor.

However, the incident light L of the photodiode PD
Since the transistor Q1 is set to operate such that when the amount of light of s decreases and the current flowing through the transistor Q1 decreases, the resistance value of the transistor Q1 increases by one digit when the current flowing through the transistor Q1 decreases by one digit. , The time constant with the parasitic capacitance C of the photodiode PD increases, and it takes time to discharge the charge accumulated in the parasitic capacitance C. Therefore, as the amount of incident light Ls decreases, an afterimage is observed over a long period of time.

FIG. 5 shows a change characteristic of the voltage signal Vpd when the sensor current of the photodiode PD rapidly changes from 1E-10A to 1E-15A.

From this characteristic, if the image signal Vo is output every 1/30 sec with a sensor current of about 1E-12A where the amount of light Ls incident on the photodiode PD is small, the voltage signal is output within that time. It can be seen that Vpd is not saturated.

Therefore, when the light amount of the incident light Ls of the photodiode PD is small, the saturation time of the voltage signal Vpd corresponding to the sensor and the current becomes long, so that the pulse timing of the image signal read signal VS as shown in FIG. When the image signal Vo is read, an output having a higher level than before appears as an afterimage. In FIG. 19, Vpd '
Indicates a voltage signal inverted and amplified by the amplification transistor Q2.

[0009]

According to the present invention, there is provided a MOS transistor for charging and discharging a parasitic capacitance of a photoelectric conversion element for detecting an optical signal and converting the signal into an electric signal. An optical sensor circuit which is fixed to a level and converts the sensor current of the photoelectric conversion element into a voltage signal with a logarithmic output characteristic in a weak inversion state is used for each pixel of the image sensor. In that case, when detecting an optical signal in each of the optical sensor circuits, the drain voltage of the MOS transistor is set lower than a steady value for a predetermined time to discharge the electric charge accumulated in the parasitic capacitance of the photoelectric conversion element. By performing initialization, even if a sudden change occurs in the sensor current, a voltage signal corresponding to the amount of incident light at that time is immediately obtained, and an afterimage occurs even when the amount of incident light is small. We try to take steps that will not happen.

More specifically, a plurality of pixels each composed of a photosensor circuit are arranged in a matrix, and a pixel column selecting circuit for sequentially selecting a pixel column for one line, and each pixel in the selected pixel column is used as a pixel column selecting circuit. In an image sensor in which each pixel signal is read out in time series by a pixel selection circuit that is sequentially selected, each pixel is initialized at an appropriate timing according to each pixel signal's readout scanning. Therefore, prior to the selection of the pixel column for each one line, the MO of each pixel in the pixel column to be selected at that time is selected.
A voltage switching circuit is provided for switching the drain voltage of the S-type transistor to a value lower than the steady state for a predetermined time and discharging the electric charge accumulated in the parasitic capacitance of the photoelectric conversion element.

At this time, in the present invention, in particular, immediately after a pixel row for one line is selected, each image signal V of the pixel row is selected.
In consideration of the response delay in each pixel when reading o, in order to provide a stable period, the pixel line for each line is divided into at least two, and the divided pixel lines in one line are shifted by a predetermined time. After the selection, the drain voltage of the MOS transistor of each pixel in the divided pixel column to be selected at that time is selected from the steady state for a predetermined time for each selection of the divided pixel column. Is also switched to a lower value.

[0012]

FIG. 1 shows an optical sensor circuit for one pixel used in an image sensor according to the present invention.

The optical sensor circuit includes a photodiode PD for generating a sensor current corresponding to the amount of incident light Ls, and a transistor Q for charging and discharging the parasitic capacitance C.
1, a transistor Q2 that amplifies the terminal voltage Vpd of the photodiode PD, and a MOS transistor Q3 that outputs an image signal Vo at the pulse timing of the image signal read signal VS. And the transistor Q
1 is fixed to a level for functioning as an overflow drain, and the photodiode PD
Is converted into a voltage signal with a logarithmic output characteristic in a weak inversion state.

In such an optical sensor circuit, in particular, in the present invention, when detecting an optical signal, the drain voltage VD of the MOS transistor Q1 is set lower than a steady value for a predetermined time, and By discharging and initializing the electric charge accumulated in the parasitic capacitance C, even if a sudden change occurs in the sensor current, a voltage signal corresponding to the incident light amount at that time can be immediately obtained, and the incident light Ls Even after a small amount of light, no afterimage is generated.

FIG. 2 shows a time chart of signals of various parts in the optical sensor circuit at that time. Here, t1
Indicates the timing of initialization, and t2 indicates the timing of optical signal detection. Drain voltage VD of transistor Q1
Is switched from a steady value (high level H) to a low voltage (low level L), for example, 5 μsec when the reading speed for one pixel is about 100 nsec.
It is set to about c. In the figure, T is a photodiode PD
Shows the accumulation period of the parasitic capacitance C, and the accumulation period T
Is 1/30 sec (or 1/60 sec.) For NTSC signals.
sec).

In such a device, the MO
The drain voltage VD of the S transistor Q1 is low level L
When the potential difference between the gate voltage VG and the drain voltage VD at that time is larger than the threshold value of the transistor Q1, the transistor Q1 enters a low resistance state. Thereby, the potential on the source side at that time becomes equal to the drain voltage VD (actually, a potential difference corresponding to the threshold remains), and the junction capacitance C of the photodiode PD is discharged.

FIG. 3 shows a transistor Q at the time of initialization.
1 schematically shows an operation state due to the flow of one electric charge q.

Then, when the drain voltage VD is switched to the steady high level H after the elapse of the time tm and the optical signal is detected, the potential on the source side becomes the drain voltage V
If the potential difference between the gate voltage VG and the drain voltage VD at that time is larger than the threshold value, the MOS transistor Q1 enters a low resistance state, and the junction capacitance C of the photodiode PD is charged. become.

FIG. 4 schematically shows an operation state due to the flow of the electric charge q of the transistor Q1 when detecting the optical signal.

As described above, if the junction capacitance C of the photodiode PD is discharged and initialized before the detection of the optical signal, the junction capacitance C is charged, and a certain time elapses from the initialization timing. At this point, the output voltage (terminal voltage of the photodiode PD) Vpd becomes a value corresponding to the amount of incident light Ls. That is, after the initialization, a discharge characteristic with a constant time constant following the change in the amount of incident light Ls can be obtained.

At this time, if left for a long time, the drain voltage V
The current supplied from D through the transistor Q1 and the current flowing through the photodiode PD are the same, but if there is no charge left before, the same discharge characteristics are always obtained, so that the afterimage does not occur.

Therefore, if the optical signal is detected for a predetermined time after the initialization, an image signal Vo having no afterimage corresponding to the amount of the incident light Ls can be obtained.

FIG. 5 shows a change characteristic of the voltage signal Vpd when the sensor current of the photodiode PD rapidly changes from 1E-10A to 1E-15A. This shows a case where the timing of signal detection is set.

FIG. 6 shows the voltage signal Vp when the optical signal is repeatedly read out at the timing of 1/30 sec.
The characteristic of the amplified signal of d is shown. According to this, 1 /
The signal characteristics obtained every 30 seconds correspond to the sensor current corresponding to the amount of light Ls incident on the photodiode PD, and it can be seen that there is no effect of the afterimage.

FIG. 7 shows the output characteristics of the pixel signal Vo when the amount of light Ls incident on the photodiode PD is changed. According to this, it is understood that the logarithmic output characteristic is completely obtained when the sensor current of the photodiode PD is 1E-13A or more. Also, when the sensor current is 1E-
It can be seen that, although the logarithmic characteristic is deviated in the area of 13A or less, an output without afterimage is obtained.

The drain voltage V of the transistor Q1 is
By adjusting the value of the low level L when decreasing D,
If the voltage is reduced until the transistor Q1 can be completely brought into the low resistance state, the output characteristics shown in FIG. 7A can be obtained. However, when the control voltage VD is set to be equal to the gate voltage VG, a normal logarithmic output characteristic as shown in FIG. 7B is obtained.

Accordingly, in the case of the output characteristic shown in FIG. 7A, there is no afterimage, but the sensitivity is low when the light amount is small. In the case of the logarithmic output characteristic shown in FIG. 7B, the sensitivity is high even when the light amount is small, but the afterimage becomes remarkable. That is, a trade-off relationship is established between the sensitivity and the afterimage.

Therefore, the drain voltage V of the transistor Q1 is set so that the output characteristic comes to an intermediate region between the output characteristic shown in FIG. 7A and the logarithmic output characteristic shown in FIG.
By adjusting D, it is possible to set such that the priority is given to the sensitivity in applications where the afterimage is not a problem, and to the setting where the priority is given to eliminating the afterimage in applications where the afterimage is a problem. In practice, it is conceivable to adjust the drain voltage VD according to the extent of the afterimage that does not cause a problem depending on the application so as to set the sensitivity as large as possible.

The present invention is directed to an image sensor in which a plurality of pixels are arranged in a matrix in such a manner that the photosensor circuit is used as a pixel unit so that each image signal is read out in time series. , So that each pixel can be initialized at an appropriate timing according to the reading scan of each image signal.

FIG. 8 shows a basic configuration example of an image sensor according to the present invention.

As the image sensor, here, D
4 × 4 pixels 11 to D44 are arranged in a matrix, and a pixel column of one line is selected by selection signals LS1 to LS4 sequentially output from the pixel column selection circuit 1, and the selected pixel column is selected. Each of the pixels in the pixel column is connected to a corresponding one of the switches SW1 to SW4 in the switch group 3 by selection signals DS1 to DS4 sequentially output from the pixel selection circuit 2.
By sequentially turning on the SW4, each image signal V
o is read out in time series. In the figure,
4 is a power supply for the gate voltage VG of the transistor Q1 in each pixel, and 6 is a power supply for the drain voltage VD.

In the image sensor, when selecting a pixel column for each one line, the drain voltage VD of the transistor Q1 of each pixel in the selected pixel column is set to a high level in a steady state at a predetermined timing. A voltage switching circuit 5 for switching to H and low level L at initialization is provided.

The operation of the thus constructed image sensor according to the present invention will be described below with reference to a time chart of signals of respective parts shown in FIG.

First, when the pixel column selection signal LS1 becomes high level H, the corresponding D11, D12, D13,
The first pixel row composed of D14 is selected. And L
During a certain period T1 in which S1 is at the high level, the pixel selection signals DS1 to DS4 sequentially go to the high level H, and the image signals V of the pixels D11, D12, D13, and D14 are output.
o are sequentially read.

Next, when the next row LS2 goes high when the pixel row selection signal LS1 goes low, a second pixel row consisting of D21, D22, D23 and D24 is selected. . Then, during a certain period T1 in which LS2 is at the high level H, the pixel selection signals DS1 to DS4 sequentially become the high level H, and the image signals Vo of the pixels D21, D22, D23, and D24 are sequentially read.

Similarly, the pixel column selection signals LS3 and LS4 continuously go to the high level H, and the corresponding third
And the fourth pixel column are sequentially selected, and LS3 and LS
4 during a certain period T1 in which the pixel selection signals DS1 to DS4 are at the high level H, respectively.
, The image signals Vo of the pixels D31, D32, D33, D34 and D41, D42, D43, D44 are sequentially read.

When the pixel column selection signal LS1 falls to the low level L after the period T1, at the time when each of the pixels D11, D12,
Each pixel is initialized by switching the drain voltage VD1 of D13 and D14 from the high level H to the low level L for a predetermined time T2, and the image in the next cycle performed after the one-cycle period T3 passes. Prepare for signal reading.

Next, when the pixel column selection signal LS2 falls to the low level L after the period T1, each of the pixels D21, D2 in the second pixel column selected at that time.
2, each pixel is initialized by switching the drain voltage VD1 of D23, D24 from the previous high level H to the low level L for a predetermined time T2, and the next cycle performed after the diameter of one cycle period T3. To read the image signal at

Similarly, when the pixel column selection signals LS3 and LS4 fall to the low level L after the period T1, respectively, the drain voltages VD3 corresponding to the third and fourth pixel columns selected at that time, respectively. Is switched to the low level L to initialize each pixel, to prepare for the readout of the image signal in the next cycle, which is performed after the passage of one cycle period T3.

Here, the pixel column selection signal LSX (X
= 1 to 4) falls to the low level L after the T1 period, the drain voltage VDX is switched to the low level L to perform initialization. The initialization timing is the pixel column selection signal LSX. During the idle period T4 of the pixel column selection in the low level L state.

The timing of the generation of the signals of the respective parts as described above is determined by driving the pixel column selection circuit 1, the pixel selection circuit 2, and the voltage switching circuit 5 under the control of an ECU (not shown). ing.

As described above, by initializing each pixel at an appropriate timing according to the reading scan of each image signal, it is possible to reduce excess / shortage of the accumulation time of the entire image sensor, and to reduce the afterimage. Instead, an image sensor having a logarithmic output characteristic with a wide dynamic range can be realized.

However, in the image sensor having the structure shown in FIG. 8, the response delay when the image signal Vo of each pixel in the pixel row is read out immediately after the pixel row of one line is selected. It becomes a problem.

FIG. 10 is a time chart of signals in each part in consideration of a response delay when an image signal Vo of each pixel in the pixel row is read out immediately after a pixel row for one line is selected.

Therefore, in practice, as shown in FIG. 11, when a pixel column for one line is selected (the pixel column selection signal LSX goes high during the period T1 and falls to low level). It is necessary to start reading the image signal Vo after the time t required for the image signal Vo in the pixel column selected at that time to stabilize from (time point).

However, since the pause period t is provided every time the image signal Vo of each pixel for one line is read, the image signal Vo of each pixel D11 to D44 in the image sensor is continuously read. It is not possible to do so and wastes time.

Therefore, in the present invention, in particular, as shown in FIG. 12, in the configuration of the image sensor, the pixel column for each one line is divided at least into two, and one of the divided pixel columns is The pixel column selection circuit 11 and the voltage switching circuit 51 are provided, and the pixel column selection circuit 12 and the voltage switching circuit 52 are provided for each of the other divided pixel columns.

As shown in FIG. 13, under the control of an ECU (not shown), one divided pixel column selection signal LSX1 output from the pixel column selection circuit 11 and the other divided pixel column selection signal LSX1 output from the pixel column selection circuit 12 When selecting a pixel column for one line according to the pixel column selection signal LSX2 obtained, the output timing of the pixel column selection signal LSX2 is delayed later than the pixel column selection signal LSX1, so that each divided pixel column in the one line is Are sequentially shifted by a predetermined time t (corresponding to the image signal stabilization period t).

At this time, the pixel column selection signal LSX1
When the pixel column selection signal LSX2 rises to the high level H later than the predetermined time t, the pixel selection circuit 2 starts reading the image signal Vo for one line.

At this time, each pixel column selection signal LSX
1 and LSX2, each time a divided pixel column is selected, the drain voltages VDX1 and VDX2 of the corresponding pixels are respectively set to low level L when the pixel column selection signals LSX1 and LSX2 fall to low level. Switch.

By reading out the image signal Vo of each of the pixels D11 to D44 in such an image sensor, it is possible to stabilize the output of the image signal every time a pixel row for each line is selected. Reading of the image signal Vo from each of the pixels D11 to D44 can be performed continuously without providing a rest period.

It is to be noted that each of the divided pixel columns is not provided with the pixel column selection circuits 11 and 12 and the voltage switching circuits 51 and 52, respectively.
Selection signals LSX1 and LSX for the pixel columns obtained by dividing the line
2 may be sent, and one voltage switching circuit may supply drain voltages VDX1 and VDX2 of the corresponding pixels in the divided pixel column of each line.

When the drain voltages VDX1 and VDX2 are switched to low level L to initialize each pixel, as shown in FIG. 14, the selection signal LSX1 (or LSX2) of the divided pixel column is set to low level. Immediately after falling to L, the drain voltage VDX1 (or VDX
If 2) is switched to the low level L, the accumulation time tc of each pixel can be taken over one cycle T. In addition, as shown in FIG. 15, if the initialization timing is delayed, the accumulation time tc of each pixel is reduced.
Can be shortened. Therefore, by shifting the initialization timing, the accumulation time tc of each pixel can be controlled, and a pseudo shutter function can be exhibited.

FIG. 16 shows another configuration example of the image sensor according to the present invention.

In this case, sample-and-hold circuits SH1 to SH4 are provided on the output side of each pixel in the pixel column for one line.

As shown in FIG. 17, under the control of an ECU (not shown), one of the sample-and-hold circuits SH1 and SH corresponding to the timing at which the selection signal LSX1 of one of the divided pixel columns becomes high level H.
The sample and hold signal SHS1 is supplied to H2. Also, the selection signal LSX2 of the other divided pixel column
Becomes high level H, the corresponding sample and hold circuits SH3 and SH4 are supplied with a sample and hold signal SHS2. Thus, the image signal Vo of each pixel in the selected pixel line of one line is sequentially held.

According to such a configuration, the image signal V of each pixel in each selected one-line pixel column is obtained.
The output of o can be performed stably.

FIG. 18 shows an example of a configuration in which an image sensor having a 3 × 6 pixel configuration is divided into three parts.

Here, the pixel column selecting circuit 11 and the voltage switching circuit 51 are applied to the divided first pixel columns in each line, and the pixel column selecting circuit 12 is applied to the divided second pixel columns. And the voltage switching circuit 52 is provided with the pixel column selection circuit 13 and the voltage switching circuit 53 for each of the divided third pixel columns.

Under the control of the ECU (not shown), when the selection signals of the divided pixel columns are output from the respective pixel column selection circuits 11, 12, and 13, a relatively predetermined period of time is set as in the case described above. By sequentially shifting the output by t, a time for stabilizing the image signal in another divided pixel column while selecting one divided pixel column is ensured.

FIG. 19 shows another example of a configuration in which an image sensor having a 3.times.6 pixel configuration is divided into three parts. In this case, a sample and output is provided on the output side of each pixel in a pixel column for one line. Hold circuits SH1 to SH
6 are provided.

Under the control of an ECU (not shown), the sample-and-hold signals are applied to the corresponding sample-and-hold circuits SH1 and SH2 at the timing when the selection signal LSX1 of the first divided pixel row rises to a high level. Thus, each image signal Vo is held.
Similarly, at the timing when the selection signal LSX2 of the divided second pixel row rises to the high level, the corresponding sample-and-hold circuits SH3 and SH4 are supplied with the sample-and-hold signals, and each image signal Vo is held. Further, the selection signal LSX2 of the divided third pixel column
Rises to a high level, the corresponding sample-and-hold circuits SH5 and SH6 are supplied with a sample-and-hold signal to hold each image signal Vo. As a result, the image signal Vo for one line divided into three is stably read.

[0063]

As described above, the present invention provides an optical sensor circuit which converts a sensor current flowing through a photoelectric conversion element in accordance with the amount of incident light into a voltage signal with a logarithmic output characteristic in a weak inversion state using a MOS transistor. A plurality of pixels are arranged in a matrix, and each pixel signal is sequentially selected by a pixel column selection circuit for sequentially selecting one line of pixel columns and a pixel selection circuit for sequentially selecting each pixel in the selected pixel column. In the image sensor configured to perform the time-series read-out scan, the pixel row for each one line is divided into at least two, and the divided pixel rows in one line are sequentially shifted by a predetermined time. When one pixel line for one line is selected and each image signal Vo is read out immediately after the selection, a pause for stabilizing the image signal output is not performed. Without providing between, can be continuously performed without causing a response delay the reading of the image signal, there is an advantage that can be achieved to enable to improve the reading speed of the image signal.

Further, according to the present invention, each time a divided pixel column is selected, the drain voltage of the MOS transistor of each pixel in the divided pixel column to be selected at that time is changed from a steady state for a predetermined time. Also switch to a lower value,
The electric charge accumulated in the parasitic capacitance of the photoelectric conversion element is discharged, so that each pixel can be initialized at an appropriate timing according to the reading scan of each image signal, and a sudden change in the sensor current occurs. Even if a change occurs, a voltage signal corresponding to the amount of incident light at that time is immediately obtained, and there is an advantage that an afterimage does not occur even when the amount of incident light is small.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an optical sensor circuit for one pixel used in an image sensor according to the present invention.

FIG. 2 is a time chart of signals of each part in the optical sensor circuit.

FIG. 3 is a diagram schematically illustrating an operation state due to a flow of a charge q of a transistor Q1 at the time of initialization of a photosensor circuit.

FIG. 4 is a diagram schematically illustrating an operation state due to a flow of a charge q of a transistor Q1 when an optical signal is detected by an optical sensor circuit.

FIG. 5 is a diagram illustrating a change characteristic of each voltage signal Vpd when a sensor current of the photodiode PD in the optical sensor circuit changes.

FIG. 6 shows a voltage signal Vpd obtained when an optical signal is repeatedly read at a predetermined timing in the optical sensor circuit.
FIG. 4 is a diagram showing characteristics of an amplified signal of FIG.

FIG. 7 is a diagram illustrating output characteristics of a pixel signal Vo when the amount of incident light Ls to a photodiode PD is changed in the optical sensor circuit.

FIG. 8 is a block diagram showing a basic configuration example of an image sensor according to the present invention.

FIG. 9 is a time chart of signals of each part of the image sensor in the basic configuration example.

FIG. 10 is a time chart of signals of respective parts in consideration of a response delay when reading an image signal in the image sensor according to the basic configuration example.

FIG. 11 is a time chart of signals of respective parts when an image signal in the image sensor according to the basic configuration example is read out during a pause period.

FIG. 12 is a block diagram showing an embodiment of an image sensor according to the present invention.

FIG. 13 is a time chart of signals of various parts of the image sensor in the embodiment.

FIG. 14 is a time chart illustrating an example of an initialization timing of each pixel in the image sensor according to the present invention.

FIG. 15 is a time chart showing another example of the initialization timing of each pixel in the image sensor according to the present invention.

FIG. 16 is a block diagram showing another embodiment of the image sensor according to the present invention.

FIG. 17 is a time chart of signals of various parts of an image sensor according to another embodiment.

FIG. 18 is a block diagram showing still another embodiment of the image sensor according to the present invention.

FIG. 19 is a block diagram showing still another embodiment of the image sensor according to the present invention.

FIG. 20 is a diagram illustrating output characteristics of an image signal read at a predetermined timing when the amount of incident light in the optical sensor circuit is small when initialization is not performed.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 pixel column selection circuit 11 to 13 divided pixel column selection circuit 2 pixel selection circuit 3 image signal output switch group 4 gate voltage power supply 5 voltage switching circuit 51 to 53 voltage switching circuit SH1 to SH4 for divided pixel column Sample and hold circuit

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Jiro Kurita 1-10-1 Shinsayama, Sayama City, Saitama Prefecture Honda Engineering Co., Ltd. (72) Inventor Katsuhiko Takebe 1-10-1 Shinsayama, Sayama City, Saitama Prefecture Hong F-term (reference) in Da Engineering Co., Ltd. 4M118 AA02 AA10 AB01 BA14 CA02 DD09 DD12 FA06 FA14 5B047 BB04 CA06 CB05 CB17 5C024 AX01 CX03 CX11 CX51 GX03 GX15 GY31 GY32 GY41 GZ42 HX12 HX17 HX35

Claims (5)

[Claims] 1. A plurality of photosensor circuits, each configured to convert a sensor current flowing through a photoelectric conversion element according to an incident light amount into a voltage signal with a logarithmic output characteristic in a weak inversion state by using a MOS transistor, are used as a pixel unit. Pixels are arranged in a matrix, and a pixel column selection circuit for sequentially selecting a pixel column for each one line and a pixel selection circuit for sequentially selecting each pixel in the selected pixel column are used in time series of each image signal. In an image sensor for performing a read-out scan, a pixel line for each one line is divided into at least two parts, and each divided pixel line in one line is sequentially shifted by a predetermined time. Characteristic image sensor. 2. Each time a divided pixel column is selected, the drain voltage of the MOS transistor of each pixel in the divided pixel column to be selected at that time is set to a value lower than a steady value for a predetermined time. 2. The image sensor according to claim 1, further comprising a voltage switching circuit for switching and discharging a charge accumulated in a parasitic capacitance of the photoelectric conversion element. 3. The drain voltage of the MOS transistor of each pixel in the divided pixel column is switched to a value lower than the steady state for a predetermined time immediately after the selection of the divided pixel column. An image sensor according to claim 2, wherein 4. After a lapse of a predetermined time from the selection of a divided pixel column, the drain voltage of the MOS transistor of each pixel in the divided pixel column is switched to a value lower than a steady state for a predetermined time. The image sensor according to claim 2, wherein: 5. The image sensor according to claim 1, wherein a sample-and-hold circuit is provided on an output side of each pixel in a pixel line for one line.