JP2002185290A - Ring oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ring oscillator which can be controlled its oscillating frequency from the outside and can reduce generation of a noise caused by an over current produced during operation. SOLUTION: Odd-numbered ranks of CSL-type inverters 11 are connected in series and the output of the last rank of CSL-type inverters 11 is feedback to the input side of he first rank of CSL-type inverters 11, thereby having the oscillator oscillate by itself. Also, the oscillator comprises bias applied terminals 12 and 13 to which bias voltages BIAS1, BIAS2 are applied. Furthermore when the oscillation gets into operation, a fixed voltage as the BIAS1 is supplied from the outside to the bias applied terminal 12 and a voltage whose voltage value is variable as the BIAS2 is supplied from the outside to the bias applied terminal 13, thereby controlling the oscillating frequency from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ring oscillator using an inverter such as a CMOS inverter.

[0002]

2. Description of the Related Art As a conventional ring oscillator, FIG.
0, the inverters 1 are connected in odd-numbered stages in series,
It is known that the output of the last-stage inverter 1 is fed back to the input side of the first-stage inverter 1. As the inverter 1, for example, as shown in FIG.
A CMOS inverter or the like combining the S transistor Q1 and the NMOS transistor Q2 is used.

[0003] The features of the CMOS inverter are as follows.
When the logic is in a steady state, that is, when the output is one of a high level (H level) and a low level (L level), no current consumption flows.
Then, as shown in FIG.
When used as a component of an oscillator, the output thereof always transitions between H level and L level during the oscillation operation.

When the input of the CMOS inverter transitions, the output is inverted, so that charge and discharge are performed. further,
In some cases, a through current may occur between the power supply and the ground. In either case, a transient current will flow. This transient current is converted to a voltage by the parasitic resistance in the current path,
The current passing through the channel of the MOS transistor is
The noise propagates to the substrate of the MOS transistor as noise.

Therefore, in a conventional ring oscillator using a CMOS inverter, when operating at a high speed, noise generated during the operation cannot be reduced. In particular, in a digital / analog hybrid circuit in which a digital section and an analog section are mixed, the noise generated as described above has a large effect on the analog section, particularly by the CMOS circuit on the digital section side. In order to electrically separate these from each other on a substrate, measures such as providing a gart ring are taken.

On the other hand, when attention is paid to the oscillation frequency of a ring oscillator using a CMOS inverter, the oscillation frequency is proportional to the number of connection stages of the CMOS inverter. Therefore,
Assuming that the delay time of each CMOS inverter is tpd and the number of stages of the CMOS inverter (ring oscillator) is N, the oscillation cycle of the ring oscillator is expressed by the following equation (1).

T = (tpd × N) + δ (1) Here, δ is a time constant due to a parasitic resistance and a parasitic capacitance of a wiring between CMOS inverters constituting the ring oscillator.

[0008]

However, when the oscillation period is shortened by reducing the number of stages of the CMOS inverter, the input signal may change before the output of each stage of the ring oscillator is inverted. In such a case, the output of each stage may be fixed at an intermediate potential between the power supply voltage and the ground, and the oscillation may be stopped.

Therefore, when a ring oscillator is constituted by a CMOS inverter, the number of connection stages of the inverter is set to a certain number or more, the gate length of the MOS transistor is increased to increase the delay time tpd, or the delay between the inverters is increased. The method of inserting a buffer is adopted. However, according to these methods, the layout area of the entire circuit is increased, and the time required for transition is increased, so that the through current may be increased.

Further, it has been difficult to vary the oscillation frequency in a conventional ring oscillator composed only of inverters. SUMMARY OF THE INVENTION An object of the present invention is to provide a ring oscillator that reduces the generation of noise due to a transient current generated during operation. It is another object of the present invention to provide a ring oscillator which can reduce the number of inverters connected in series as compared with a conventional ring oscillator at the same oscillation frequency.

Still another object of the present invention is to provide a ring oscillator whose oscillation frequency can be varied.

[0012]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, each of the inventions according to claims 1 to 6 is configured as follows. That is, the invention according to claim 1 is a ring oscillator in which inverters are connected in series in an odd number of stages and the output of the last-stage inverter is fed back to the input side of the first-stage inverter to perform self-oscillation. , And CSL type inverters.

According to a second aspect of the present invention, in the ring oscillator according to the first aspect, each of the CSL type inverters has a bias application terminal, and a bias application terminal of at least one of the CSL type inverters. The oscillation frequency can be made variable by changing the bias applied to the power supply. The invention according to claim 3 is a ring oscillator in which inverters are connected in series in an odd-numbered stage, and the output of the last-stage inverter is fed back to the input side of the first-stage inverter to perform self-oscillation. Is formed by a CSL type inverter, and at least one of the CSL type inverters includes:
A driving capability is lower than that of the CSL type inverter, and a feedback CSL type inverter reversely connected between the input and the output is included.

According to a fourth aspect of the present invention, in the ring oscillator according to the third aspect, each of the odd-numbered CSL type inverters and the feedback CSL type inverter has a bias application terminal, and Wherein the bias applied to at least one of the inverters is varied to make the oscillation frequency variable.

According to a fifth aspect of the present invention, in the ring oscillator according to the third aspect, the odd-numbered-stage CSL type inverter has first and second biases to which first and second biases are applied, respectively. The feedback CSL-type inverter has a third bias application terminal to which a third bias is applied, and applies a fixed first bias to the first bias application terminal. And a variable second bias is applied to the second bias application terminal, and one of the second bias and the third bias is applied to the third bias application terminal. Is applied.

According to a sixth aspect of the present invention, in the ring oscillator according to the fifth aspect, a variable common bias or a variable individual bias is applied to each second bias application terminal of the CSL type inverter. Is applied. As described above, according to the present invention, since the CSL type inverter is used as the inverter, a transient current does not occur during the switching operation, and the generation of noise due to the current can be reduced.

In the present invention, when a CSL type inverter having a lower driving capability is connected in reverse between the input and output of the CSL type inverter, the transition time between the H level and the L level can be adjusted. . Therefore, when obtaining the same oscillation frequency, the number of inverters connected in series can be reduced as compared with the conventional ring oscillator.

Further, in the present invention, when the bias applied to the CSL type inverter is varied, the oscillation frequency can be externally controlled by varying the bias. Furthermore, since the oscillation frequency can be varied in the present invention, if the oscillation frequency can be reduced and the device can be used, power consumption can be reduced by decreasing the oscillation frequency.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a ring oscillator according to the present invention will be described with reference to the drawings. The ring oscillator according to the first embodiment has a CSL (Current Steering Log) as an inverter as shown in FIG.
Since the ic) type inverter 11 is used, the CSL type inverter will be described first.

FIG. 1 is a circuit diagram showing a specific configuration of a CSL type inverter, and FIG. 2 is a diagram showing an example of symbols of the inverter. This CSL type inverter 11
As shown in FIG. 1, it has an NMOS transistor Q11 as a switching element, and a diode-connected NMOS transistor Q12 is connected in parallel to this NMOS transistor. Also, the NMOS transistor Q
11, Q12 include PMOS transistors Q13, Q1
The constant current source 4 supplies a constant current.

More specifically, in the NMOS transistor Q11, the input voltage IN is applied to the gate, the source is grounded, and the output voltage OUT is taken out from the drain. NMOS transistor Q1
2 has a gate that has its own drain, the drain of the NMOS transistor Q11, and the
14, and the source is grounded.

The PMOS transistors Q13 and Q14 are cascode-connected to form a constant current source. And
The power supply voltage is supplied to the source of the PMOS transistor Q13, and the drain of the PMOS transistor Q14 is set to NM.
Commonly connected to the drain and the like of the OS transistor Q11. The bias voltage BIAS1 is applied to the gate of the PMOS transistor Q13, whereby the amount of current of the constant current source is adjusted. PMO
The gate of the S transistor Q14 has a bias voltage BI
AS2 is applied, which causes the PMOS transistor Q
14 is operated in the saturation region to increase the constant current property.

Next, an operation example of the CSL type inverter having such a configuration will be described below. Now, P
It is assumed that the constant current source including the MOS transistors Q13 and Q14 supplies a predetermined constant current (for example, 500 μA) to the NMOS transistors Q11 and Q12.

At this time, when an H level is input to the gate of the NMOS transistor Q11, the NMOS transistor Q11 turns on, and its constant current flows through the NMOS transistor Q11. In the NMOS transistor Q11, there is a predetermined voltage drop (for example, about several tens mV) with respect to this constant current, and this is output as an L level. on the other hand,
When an L level is input to the gate of the NMOS transistor Q11, the NMOS transistor Q11 is turned off, and the constant current is supplied to the diode-connected NMOS transistor Q11.
Flows to 12. The NMOS transistor Q12 has a voltage drop of about 2 V with respect to the constant current, and this is output as the H level.

As described above, according to the CSL type inverter, a constant current always flows, and a transient current does not occur during the switching operation, so that noise caused by the transient current can be reduced. Next, the ring oscillator according to the first embodiment will be described with reference to FIG.

In the ring oscillator according to the first embodiment, as shown in FIG. 3, the CSL type inverters 11 shown in FIG. 1 are connected in series in an odd number of stages, and the output of the last stage CSL type inverter 11 is connected to the first stage. The signal is fed back to the input side of the CSL type inverter 1 and self-oscillates. Further, as shown in FIG. 3, the ring oscillator according to the first embodiment has bias application terminals 12 and 13 for applying bias voltages BIAS1 and BIAS2, respectively. The bias application terminal 12 is connected to the CSL type inverter 1
1 is connected to each gate of the PMOS transistor Q13, and the bias application terminal 13 is connected to the CSL type inverter 1
Commonly connected to each gate of one PMOS transistor Q14.

Further, in the ring oscillator according to the first embodiment, during the oscillation operation, a fixed voltage as the bias voltage BIAS1 is externally supplied to the bias application terminal 12, and the bias application terminal 13 is supplied with the bias voltage. As the voltage BIAS2, a voltage whose voltage value changes is supplied from the outside, whereby the oscillation frequency is externally controlled (variable).

As described above, according to the first embodiment, since the CSL type inverter is used, no transient current is generated at the time of the switching operation, and the transient current is generated. Generation of noise can be reduced. Further, according to the first embodiment, since the bias voltage BIAS2 whose voltage is variable is externally applied to the gate of the PMOS transistor Q14, which is the bias application terminal, the oscillation frequency can be externally controlled.

Furthermore, according to the first embodiment, since the oscillation frequency can be varied, when the oscillation frequency can be reduced, the power consumption can be reduced by lowering the oscillation frequency. In the first embodiment, all the CSL type inverters 1 constituting the ring oscillator
1, a case has been described in which a common bias voltage whose voltage value changes is uniformly supplied from the outside as the bias voltage BIAS2, thereby controlling the oscillation frequency from the outside.

However, instead of this, the bias voltage BI
As the AS2, an individual voltage whose voltage value changes may be supplied to each inverter to control the oscillation frequency. Further, among all the CSL type inverters 11, a bias voltage whose voltage value changes is supplied to at least one inverter 11, and a bias voltage whose voltage value is fixed is supplied to the remaining inverters 11, thereby controlling the oscillation frequency. You may do it.

Next, a second embodiment of the ring oscillator of the present invention will be described with reference to FIGS.
As shown in FIG. 4, the ring oscillator according to the second embodiment is based on the ring oscillator of the first embodiment shown in FIG. 3, and a CSL type inverter is provided between the input and output of each CSL type inverter 11. In this configuration, a feedback CSL type inverter 21 having a lower driving capability than the inverter 11 is reversely connected. The common bias voltage BIAS2 applied to the CSL type inverter 11 is applied to the CSL type inverter 21.

Here, since the configuration of the other parts of the second embodiment is the same as that of the first embodiment of FIG. 3, the same components are denoted by the same reference numerals, and the description thereof will be omitted. CS
The specific configuration of the L-type inverter 21 will be described with reference to FIG. As shown in FIG. 5, the CSL type inverter 21 has an NMOS transistor Q21 as a switching element, and a diode-connected NMOS transistor Q22 is connected in parallel to the NMOS transistor Q21. Also, the NMOS transistor Q2
1, Q22 include PMOS transistors Q13, Q24
The constant current source is configured to supply a constant current.

More specifically, the NMOS transistor Q21 has a gate connected to the drain of the NMOS transistor Q11, a source grounded, and a drain connected to the gate of the NMOS transistor Q11. The gate of the NMOS transistor Q22 has its own drain, the drain of the NMOS transistor Q21, the gate of the NMOS transistor Q11,
Commonly connected to the drain of the OS transistor Q24,
And its source is grounded.

The gate of the PMOS transistor Q24 is connected to the gate of the PMOS transistor Q14, and a common bias voltage BIAS2 is applied.
Its source is connected to the drain of the PMOS transistor Q13. As described above, according to the second embodiment, since the CSL type inverter is used, no transient current is generated at the time of the switching operation, and noise generated due to the transient current is generated. Can be reduced.

According to the second embodiment, the CSL
By connecting a CSL-type inverter 21 having a lower driving capability than the CSL-type inverter 21 between the input and output of the
The transition time between the level and the L level is adjusted. Therefore, if the oscillation frequency is the same, the number of inverters 11 connected in series can be reduced as compared with the conventional ring oscillator.

Although the number of serially connected CSL type inverters 11 can be reduced, the CSL type inverters 21 are connected in parallel with the CSL type inverters 11, but since the CSL type inverters 21 are smaller in circuit scale than the CSL type inverters 11, The layout area can be reduced as a whole. further,
According to the second embodiment, the PMOS transistor Q1
4. Since the bias voltage BIAS2 whose voltage changes is externally applied to each gate of Q24, the oscillation frequency can be externally controlled.

In the second embodiment, all the CSL type inverters 11 and 21 constituting the ring oscillator are provided with:
As the bias voltage BIAS2, a case has been described in which a common bias voltage whose voltage value changes is uniformly supplied from the outside, and thereby the oscillation frequency is externally controlled. However, instead of this, an individual voltage whose voltage value changes as the bias voltage BIAS2 may be supplied to each inverter to control the oscillation frequency. Also,
A bias voltage whose voltage value changes is supplied to at least one of the CSL type inverters 11 and 21, and a bias voltage having a fixed voltage value is supplied to the remaining inverters, thereby controlling the oscillation frequency. You may do it.

Next, a third embodiment of the ring oscillator of the present invention will be described with reference to FIGS.
As shown in FIG. 6, the ring oscillator according to the third embodiment has the same basic configuration as the ring oscillator of the second embodiment shown in FIG. 4, and the difference is that the bias application for applying the bias voltage BIAS3 is performed. Add terminal 31,
The bias application terminal 31 is connected to the CSL type inverter 21.
Are commonly connected to each gate of the PMOS transistor Q24. Therefore, as shown in FIG. 7, a bias voltage BIAS3 whose voltage changes is independently applied to the gate of the PMOS transistor Q24.

Here, since the configuration of the other parts of the third embodiment is the same as that of the second embodiment of FIG. 4, the same components are denoted by the same reference numerals and description thereof will be omitted. In the third embodiment having such a configuration, a common bias voltage is used as the bias voltages BIAS2 and BIAS3, and an example of the relationship between the change in the bias voltage and the change in the oscillation frequency is shown in FIG. Become.

As described above, according to the third embodiment, the same effects as in the second embodiment can be realized. Next, the conventional circuit shown in FIG. 1, the circuit of the first embodiment shown in FIG. 3, and the circuit of the second embodiment shown in FIG. 4 were compared with each other by simulation. Shown in

As shown in FIG. 9, when the oscillation frequency is the same, the circuits of the first embodiment and the second embodiment are superior to the conventional circuit in both the number of connected inverters and the layout area. You can see that it is. Also, comparing the circuits of the first embodiment and the second embodiment, it can be seen that the circuit of the second embodiment is superior.

[0042]

As described above, according to the present invention,
Since the CSL type inverter is used as the inverter, no transient current is generated during the switching operation, and the generation of noise due to the current can be reduced. Further, in the present invention, when a CSL type inverter having a lower driving capability is connected in reverse between the input and output of the CSL type inverter, the transition time between the H level and the L level can be adjusted. Therefore, when obtaining the same oscillation frequency, the number of inverters connected in series can be reduced as compared with the conventional ring oscillator.

Further, in the present invention, when the bias applied to the CSL type inverter is varied, the oscillation frequency can be externally controlled by varying the bias. Furthermore, since the oscillation frequency can be varied in the present invention, when the oscillation frequency can be reduced and used,
Power consumption can be reduced by lowering the oscillation frequency.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a specific configuration of a CSL inverter used in a first embodiment of a ring oscillator of the present invention.

FIG. 2 is a diagram showing symbols of the CSL type inverter.

FIG. 3 is a block diagram illustrating a configuration of a ring oscillator according to a first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a second embodiment of the ring oscillator of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a CSL type inverter used in a second embodiment.

FIG. 6 is a block diagram showing a configuration of a third embodiment of the ring oscillator of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a CSL type inverter used in a third embodiment.

FIG. 8 is a diagram showing a relationship between a bias voltage and an oscillation frequency.

FIG. 9 is a diagram showing a comparative example of a conventional circuit and the circuit of the embodiment.

FIG. 10 is a block diagram illustrating an example of a conventional ring oscillator.

FIG. 11 is a circuit diagram showing a configuration of a CMOS inverter.

[Explanation of symbols]

Q11, Q12, Q21, Q22 NMOS transistors Q13, Q14, Q24 PMOS transistor BIAS1 bias voltage (first bias) BIAS2 bias voltage (second bias) BIAS3 bias voltage (third bias) 11 CSL type inverters 12, 13 , 31 Bias application terminal 21 CSL type inverter

Claims (6)

[Claims] 1. A ring oscillator in which inverters are connected in series in an odd number of stages and an output of a last stage inverter is fed back to an input side of a first stage inverter to perform self-oscillation.
c) A ring oscillator characterized by being formed by a type inverter. 2. The method according to claim 1, wherein each of the CSL type inverters has a bias application terminal, and a bias applied to a bias application terminal of at least one of the CSL type inverters is variable to make the oscillation frequency variable. The ring oscillator according to claim 1, wherein: 3. A ring oscillator in which inverters are connected in series in an odd-numbered stage, and the output of the last-stage inverter is fed back to the input side of the first-stage inverter to perform self-oscillation. And at least one of the CSL-type inverters has a lower driving ability than the CSL-type inverter and includes a feedback CSL-type inverter reversely connected between input and output. Characterized ring oscillator. 4. Each of the odd-numbered CSL-type inverters and the feedback CSL-type inverter has a bias application terminal, and oscillates by changing a bias applied to at least one of the CSL-type inverters. 4. The ring oscillator according to claim 3, wherein the distance is variable. 5. The odd-numbered-stage CSL type inverter has first and second bias application terminals to which first and second biases are applied, respectively, and the feedback CS line.
The L-type inverter has a third bias application terminal to which a third bias is applied, and applies a fixed first bias to the first bias application terminal and the second bias application terminal. , A variable second bias is applied, and one of the second bias and the third bias is applied to the third bias application terminal. The ring oscillator according to claim 3, wherein 6. The variable bias according to claim 5, wherein a variable common bias or a variable individual bias is applied to each second bias application terminal of the CSL type inverter. Ring oscillator.