JP2002182993A - Bus interface circuit and initiator target system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform self-restoration in a hardware level even in the case of non-response concerning the response of a control signal. SOLUTION: Each one of more than one target side units 2 transfers data with an initiator side unit 1 by a hand shake system protocol by each first bus interface part through the use of an SCSI bus 3 which is provided with the control signal and a data bus. The initiator side unit 1 transfers data with the target side units 2 by the hand shake system protocol by a bus interface circuit 4 through the use of the SCSI bus 3, monitors the state of the control signal to be used for hand-shake, grasps the situation of data transfer from the state of the control signal, measures a data transfer time, interrupts data transfer when the measured data transfer time becomes a predetermined time and releases the SCSI bus 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit and an initiator / target system using the circuit, and more particularly to a bus interface circuit for transferring data by a handshake protocol using a bus and a bus interface circuit using the bus interface circuit. Regarding the initiator / target system.

[0002]

2. Description of the Related Art Conventionally, a bus interface circuit of this kind and an initiator / target system using this circuit have been used to transfer data by a handshake protocol using a bus.

As a bus for performing such data transfer, for example, a SCSI (Small Computer System Interface) bus having a control signal and a data bus is known as a known technique. Referring to FIGS. 9 to 13 showing timing charts of data transfer according to the prior art, an initiator-side device and a target-side device, for example, showing a host computer, a disk controller and other peripheral devices connected to this SCSI bus. An example of an operation at the time of data transfer by handshake using a bus interface circuit provided in each device between the devices will be described.

FIG. 9 is a timing chart when data is transferred from the target device to the initiator device.
The target-side device outputs data on the bus at time T1 (that is, the time when data was output was T1, and the other time indicated by Tn is similarly a certain time during data transfer simply by handshake). After that, REQ, which is a control signal, is asserted (that is, the signal is made active) to request the initiator-side device to perform data transfer. In response to the assertion of REQ, the initiator-side device takes in data when the data bus is busy, for example, and at the same time, asserts ACK as a control signal and responds to the target-side device (time T3). The target device releases REQ in response to the assertion of ACK, and stops outputting data to the data bus (at time T
4). In response to the release of REQ, the initiator device
Release K.

FIG. 10 is a timing chart at the time of data transfer from the initiator side device to the target side device. The target device asserts REQ and makes a data transfer request to the initiator device (time T1). In response to the assertion of REQ, the initiator device outputs data to the data bus when the data bus is not busy (time T2), and asserts ACK to respond to the target device (time T3). The target-side device receives the assertion of ACK, takes in the data on the data bus, and releases REQ at the same time (time T4), and the initiator-side device releases ACK in response to the release of REQ.

[0006] Such data transfer by the handshake method enables reliable transfer, but when the handshake falls into an invalid state for some reason, an abnormality cannot be detected at the hardware level. Have a problem of malfunction. Factors that cause an invalid state include, firstly, a case where an incorrect response is detected by adding noise to a control signal for handshake,
Secondly, it is considered that response detection fails and there is no response because the bus interface circuit malfunctions due to electrical noise or the transmission path of the control signal is physically damaged and the signal does not arrive. Can be First, an operation in a case where an incorrect response is detected due to the noise mixed with the control signal will be described. As an example, FIG.
Shows the operation in the case where noise is mixed in the data. The transfer direction is from the target device to the initiator device. The target device outputs the transfer data to the data bus at time T1, and asserts REQ at time T2. Upon receiving this REQ, the initiator-side device asserts ACK (time T3). Normally, the asserted ACK is released after the REQ is released (similar to FIG. 9) (time T5). However, noise (T3
1 to T41), the bus interface circuit may operate erroneously. That is, the initiator-side device fetches data on the data bus at time T3 as usual, asserts ACK, and releases ACK at time T5 after waiting for REQ release. On the other hand, the target-side device erroneously detects the ACK release at T31 and outputs the next transfer data (Data (2)) to the data bus (time T42). Then, after obtaining a certain margin (for example, several tens to several hundreds of ns; however, depending on the operation clock of each device, there may be a case outside this range.)
EQ is asserted (time T51). Then T4
Since the cancellation of the ACK noise in step 1 is erroneously recognized as the assertion of the ACK, the REQ is canceled again (time T52). In other words, although the target device recognizes that two data (Data (1), Data (2)) have been transferred, the initiator device can capture only one data (Data (1)). become.

Next, the operation when the control signal becomes unresponsive will be described with reference to an example. FIG. 12 shows an operation when the target device cannot detect the assertion of ACK from the initiator device. The target-side device outputs the transfer data to the data bus at time T1, and outputs the transfer data at T2.
Assert Q to notify the initiator device of the transfer request. If the target-side device cannot detect an ACK that should be asserted at time T3, the bus interface circuit of the target-side device keeps waiting with ACK assertion. Since the REQ cannot be released even in the initiator-side device, the ACK cannot be released, so that the entire system is deadlocked while the data bus is occupied.

[0008] Similarly, FIG. 13 shows an operation in the case where the REQ release from the target device cannot be detected by the initiator device. At the initiator side device, the time T4
If the REQ to be released is not detected at the point of time, the bus interface circuit of the initiator device
It keeps waiting for release. Since the ACK is not released from the target-side device, it is not possible to shift to the next data transfer. In this case, the system is in a deadlock state.

In order to recover from the deadlock state caused by such a problem, for example, the state of the data bus is polled at a certain interval, and if the data bus is not released from being busy for a certain period, the deadlock is performed. It is necessary to perform recovery processing by monitoring with software, such as resetting a device connected to the SCSI bus, by determining that the device is in the state.

As a hardware level detection method of a transfer protocol error, for example, Japanese Patent Laid-Open No. 2000-21
In the method disclosed in Japanese Patent Application Laid-Open No. 5113, the values of the REQ and ACK signals are monitored as shown in FIG. 14 showing an error detection circuit, and the combination of the two control signal values cannot be taken in a normal state. Sometimes, a method of determining an abnormality has been proposed. In the case where the handshake is in an invalid state due to the noise mixed with the REQ or ACK, that is, in the case of the first cause described above, the synchronization of the REQ and the ACK is incorrectly combined. It is possible to detect. However, in the case of the second cause in which the control signal is not responding, since the status of REQ and ACK is a normal combination, it cannot be determined that an error has occurred, and the system deadlock can be avoided. Absent.

[0011]

The above-described conventional bus interface circuit and the initiator / target system using the circuit detect a transfer protocol error by the method disclosed in Japanese Patent Application Laid-Open No. 2000-215113. . That is, the error detection circuit
The values of the Q and ACK signals are monitored, and when the values of the two control signals are in a combination that cannot be taken under normal conditions, it is determined that there is an abnormality. Therefore, REQ or A
If the handshake is in an invalid state due to the noise mixed with the CK (that is, in the case of the first cause described above), the synchronization between the REQ and the ACK results in an incorrect combination. It is possible to However, in the case of the second cause in which the control signal has become non-responsive, since the states of REQ and ACK are a normal combination, it cannot be determined that an error has occurred, and a deadlock state cannot be avoided. There is a problem. Further, in order to recover from the deadlock state by software, it is necessary to monitor and perform recovery processing by software, so that there is a problem that the load of software processing increases.

An object of the present invention is to eliminate such a conventional drawback, so that when a response of a control signal becomes unresponsive,
An object of the present invention is to provide a bus interface circuit capable of self-recovery at a hardware level and an initiator / target system using the circuit.

[0013]

SUMMARY OF THE INVENTION A bus interface circuit of the present invention transfers data by a handshake protocol using a bus having a control signal and a data bus, and a data transfer time elapses a predetermined time. A bus interface unit for interrupting the data transfer and releasing the bus in response to a time-out signal indicating that the status of the data transfer is monitored from the state of the control signal used for the handshake. And a data transfer time monitoring unit that outputs the time-out signal when the measured data transfer time exceeds the predetermined time.

The data transfer time monitoring section of the bus interface circuit of the present invention detects the data transfer status from the state of the control signal used for the handshake and detects the start timing and the end timing of the data transfer. A bus monitoring unit that outputs a transfer start signal and a transfer end signal, and starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit and receives the data in response to the transfer end signal. A timeout monitoring unit that outputs the timeout signal when the measurement of the transfer time is completed and the data transfer time during the measurement exceeds the predetermined time.

The timeout monitoring unit of the bus interface circuit according to the present invention starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit, and receives the data in response to the transfer end signal. A data transfer time measurement unit for ending the measurement of the transfer time and outputting the data transfer time during the measurement, and receiving the data transfer time during the measurement output by the data transfer time measurement unit and receiving the data transfer A time-out determination unit that outputs the time-out signal when the result of the check indicates that the predetermined time has elapsed. I have.

A first initiator / target system according to the present invention includes an initiator-side device connected to a bus and acquiring an access right to the bus to take the initiative in data transfer.
An initiator / target system connected to the initiator-side device via the bus and provided with the initiator-side device and a plurality of target-side devices for transferring the data under the initiative of the initiator-side device. A plurality of target-side devices including a first bus interface unit for performing the data transfer with the initiator-side device by a handshake protocol using the bus having a bus; Performs the data transfer with the plurality of target-side devices according to the protocol of the shake method, monitors the state of the control signal used for the handshake, grasps the state of the data transfer from the state of the control signal, and determines the data transfer time. And the measured data transfer time is determined in advance. Wherein is configured by including an initiator device, a said interrupt the data transfer with a bus interface circuit to release the bus when the elapsed between.

The bus interface circuit of the first initiator / target system of the present invention performs the data transfer with the plurality of target-side devices by the protocol of the handshake system using the bus, and performs the data transfer time. A second bus interface unit for interrupting the data transfer and releasing the bus in response to a timeout signal indicating that the predetermined time has elapsed, and monitoring and controlling the state of the control signal used for the handshake. A data transfer time monitoring unit that grasps the state of the data transfer from the state of the signal, measures the data transfer time, and outputs the timeout signal when the measured data transfer time exceeds the predetermined time; , Is configured.

A second initiator / target system according to the present invention includes an initiator device connected to a data bus and acquiring an access right of the data bus to take the initiative of data transfer, and the initiator device and the data bus. And an initiator / target system including the initiator-side device and the plurality of target-side devices for data transfer under the leadership of the initiator-side device, wherein the bus having a control signal and a data bus is provided. Using a handshake protocol to perform the data transfer with the initiator-side device, receive a time-out signal indicating that a data transfer time has passed a predetermined time, interrupt the data transfer, and release the bus. The plurality of target-side devices provided with one bus interface unit Using the bus, performing the data transfer with the plurality of target-side devices using the protocol of the handshake method, monitoring the state of the control signal used for the handshake, and checking the state of the data transfer from the state of the control signal. The data transfer time is measured and the time-out signal is output to the plurality of target-side devices when the measured data transfer time has passed the predetermined time, and the data transfer is interrupted. The initiator-side device having a bus interface circuit for releasing a bus.

The bus interface circuit of the second initiator / target system of the present invention performs the data transfer with the plurality of target-side devices using the bus by the handshake protocol and receives the timeout signal. A second bus interface unit for interrupting the data transfer and releasing the bus, monitoring the state of the control signal used for the handshake, grasping the state of the data transfer from the state of the control signal, and A data transfer time monitoring unit that measures a transfer time and outputs the timeout signal when the measured data transfer time exceeds the predetermined time.

The data transfer time monitoring unit of the first and second initiator / target systems of the present invention grasps the state of the data transfer from the state of the control signal used for the handshake and starts the data transfer. A bus monitor for detecting a timing and an end timing and outputting a transfer start signal and a transfer end signal, respectively, and receiving the transfer start signal output by the bus monitor, starts measuring the data transfer time and performs the transfer. A timeout monitoring unit that receives the end signal, terminates the measurement of the data transfer time, and outputs the timeout signal when the data transfer time during the measurement exceeds the predetermined time. ing.

In the first and second initiator / target systems according to the present invention, the timeout monitoring unit receives the transfer start signal output by the bus monitoring unit, starts measuring the data transfer time, and performs the transfer. A data transfer time measuring unit for ending the measurement of the data transfer time in response to the end signal and outputting the data transfer time during the measurement, and the data transfer time during the measurement output by the data transfer time measuring unit A time-out determination unit that outputs the time-out signal when the received data transfer time has passed the predetermined time and the result of the check indicates that the predetermined time has passed. , Is configured.

A third initiator / target system according to the present invention comprises: an initiator-side device which is connected to a bus, acquires an access right to the bus, and takes control of data transfer;
An initiator / target system connected to the initiator-side device via the bus and provided with the initiator-side device and a plurality of target-side devices for transferring the data under the initiative of the initiator-side device. And performing the data transfer with the initiator-side device using a protocol of a handshake method using the bus having the bus and monitoring the state of the control signal used for the handshake, and performing the data transfer from the state of the control signal. A first bus interface circuit for measuring the data transfer time by grasping the situation, and interrupting the data transfer and releasing the bus when the measured data transfer time exceeds a predetermined first time; A handshake method using the plurality of target devices and the bus. Performing the data transfer with the plurality of target-side devices according to the protocol, monitoring the state of the control signal used for the handshake, grasping the state of the data transfer from the state of the control signal, and measuring the data transfer time And an initiator-side device having a second bus interface circuit for interrupting the data transfer and releasing the bus when the measured data transfer time exceeds a predetermined second time. Have been.

The first bus interface circuit of the third initiator / target system of the present invention uses the control signal and the data bus to perform the data transfer with the initiator-side device by the handshake protocol. And a third bus interface unit for interrupting the data transfer and releasing the data bus upon receiving a first time-out signal indicating that the data transfer time has passed the predetermined first time, The state of the control signal used for handshake is monitored, the state of the data transfer is grasped from the state of the control signal, the data transfer time is measured, and the measured data transfer time is the predetermined first time. When the first
A first data transfer time monitoring unit that outputs a time-out signal of the target device, wherein the second bus interface circuit communicates with the plurality of target-side devices and the data by the handshake protocol using the bus. A second bus interface unit for performing a transfer and interrupting the data transfer and releasing the bus in response to a second timeout signal indicating that the data transfer time has passed the predetermined second time; The state of the control signal used for handshake is monitored, the state of the data transfer is grasped from the state of the control signal, the data transfer time is measured, and the measured data transfer time is the predetermined second time. And a second data transfer time monitoring unit that outputs the second timeout signal when elapses.

Further, the first data transfer time monitoring section of the third initiator / target system of the present invention comprises:
The state of the data transfer is grasped from the state of the control signal used for the handshake, the start timing and the end timing of the data transfer are detected, and the first transfer start signal and the first transfer end signal are output respectively. A first bus monitoring unit that performs the operation, and the first bus monitoring unit that outputs the first bus monitoring unit.
Receiving the transfer start signal, starting the measurement of the data transfer time, receiving the first transfer end signal, ending the measurement of the data transfer time, and the data transfer time during the measurement is the predetermined number of times. A first time-out monitoring unit that outputs the first time-out signal when a time of 1 has elapsed, and wherein the second data transfer time monitoring unit is configured to change the state of the control signal used for the handshake from the state of the control signal. A second transfer start signal and a second transfer end signal which are obtained by grasping the data transfer situation and detecting a start timing and an end timing of the data transfer;
A bus monitoring unit, and starts measuring the data transfer time in response to the second transfer start signal output by the second bus monitoring unit, and measures the data transfer time in response to the second transfer end signal. A second timeout monitoring unit that outputs the second timeout signal when the data transfer time during the measurement ends the predetermined second time while ending the measurement. I have.

Further, in the third initiator / target system of the present invention, the first timeout monitoring unit receives the first transfer start signal output by the first bus monitoring unit, and monitors the data transfer time. A first data transfer time measuring unit that starts measurement, receives the first transfer end signal, terminates the measurement of the data transfer time, and outputs the data transfer time during the measurement, and the first data Receiving the data transfer time during the measurement output by the transfer time measuring unit, and checking whether or not the received data transfer time has passed the predetermined first time. A first time-out determination unit that outputs the first time-out signal when it indicates that one time has elapsed, and the second time-out monitoring unit includes:
Upon receiving the second transfer start signal output by the second bus monitoring unit, the second bus monitoring unit starts measuring the data transfer time.
A second data transfer time measuring unit for ending the measurement of the data transfer time in response to the transfer end signal of the second and outputting the data transfer time during the measurement, and outputting the second data transfer time measuring unit. Receiving the data transfer time during the measurement, checking whether the received data transfer time has passed the predetermined second time, and determining that the result of the check has passed the predetermined second time; And a second timeout determination unit that outputs the second timeout signal when

[0026]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the initiator / target system of the present invention.

In this embodiment shown in FIG. 1, an initiator-side device 1 which is connected to a bus and acquires an access right to the bus to take the initiative in data transfer, and via the initiator-side device 1 and the bus. In an initiator / target system having the initiator-side device 1 and a plurality of target-side devices 2 for transferring data under the initiative of the initiator-side device 1, a bus (for example, SCSI bus) having a control signal and a data bus is provided. 3. A first method for performing data transfer with the initiator device 1 using a handshake protocol using the SCSI bus 3).
A plurality of target-side devices 2 having a bus interface unit, and data transfer with the plurality of target-side devices 2 using a handshake protocol using the SCSI bus 3 and monitoring of the state of a control signal used for handshake Then, the state of the data transfer is grasped from the state of the control signal to measure the data transfer time, and the measured data transfer time is set to a predetermined time (for example, a value within a range of about several hundred ns to several ms. The data transfer is interrupted when the value exceeds this range.
And an initiator-side device 1 having a bus interface circuit 4 for releasing the bus 3.

Next, the operation of the initiator / target system of the present embodiment will be described in detail with reference to FIGS. 2, 3, 4 and 5.

FIG. 2 is a block diagram showing an example of the bus interface circuit according to the present invention. The bus interface circuit 4 uses the SCSI bus 3 to communicate with a plurality of target devices 2 by a handshake protocol. A second bus interface unit for interrupting data transfer upon receiving a timeout signal indicating that the data transfer time has passed a predetermined time and releasing the SCSI bus, and a state of a control signal used for handshaking; A data transfer time monitoring unit 6 which monitors the data transfer state from the state of the control signal to measure the data transfer time and outputs a timeout signal when the measured data transfer time exceeds a predetermined time. It consists of. The data transfer time monitoring unit 6 grasps the state of the data transfer from the state of the control signal used for handshake, detects the start timing and the end timing of the data transfer, and outputs a transfer start signal and a transfer end signal, respectively. The monitoring unit 7 starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit 7, ends the data transfer time measurement in response to the transfer end signal, and determines the data transfer time being measured in advance. And a time-out monitoring unit 8 that outputs a time-out signal when the elapsed time has elapsed. The timeout monitoring unit 8 starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit 7, ends the data transfer time measurement in response to the transfer end signal, and outputs the data transfer time being measured. The data transfer time measuring unit 10 performs the data transfer time during measurement output by the data transfer time measurement unit 10 and checks whether or not the received data transfer time has passed a predetermined time. Timeout determination unit 9 that outputs a timeout signal when it indicates that a predetermined time has elapsed.
It is composed of Data transfer time measurement unit 10
Receives the transfer start signal output by the bus monitor 7 and starts measuring the data transfer time, and terminates the measurement of the data transfer time when the data transfer time during the measurement has passed a predetermined time. ing. The control signal includes an REQ signal input to the second bus interface unit 5 and indicating a data transfer request, and an ACK signal generated by the second bus interface unit 5 and indicating acknowledgment of the data transfer request. I have.

FIG. 3 is a diagram showing an example of a timing chart 1 (during normal operation) of data transfer according to the present embodiment.

FIG. 4 is a diagram showing an example of the data transfer timing chart 2 (no ACK response) according to the present embodiment.

FIG. 5 is a diagram showing an example of a timing chart 3 (no REQ response) of data transfer according to the present embodiment.

Referring to FIG. 1, first, an operation in a case where normal data transfer is performed will be described with reference to FIG. There are two possible data transfer paths: a case where data is transferred from the initiator device 1 to the target device 2 and a case where data is transferred from the target device 2 to the initiator device 1. The case of data transfer from the device 2 to the initiator device 1 will be described as an example. The internal signals (transfer start signal (for example, transfer start pulse),
The issuing position of the transfer end signal (for example, transfer end pulse), timeout signal, and the like, the assertion period, and the like are merely examples, and do not specify any phase.
When the data bus is empty (that is, when it is not busy), the target-side device 2 outputs transfer data to the data bus (time T1). The target side device 2 takes a sufficient margin from the time T1 and then sets the time T2
Asserts the REQ signal to notify the initiator-side device 1 of a transfer request. In the initiator device 1, R
In response to the assertion of the EQ and taking in the data on the data bus, the ACK is asserted and the target device 2
(Time T3). At this time, the bus monitor 7 shown in FIG. 2 issues a transfer start signal. The data transfer time measuring unit 10 receives this transfer start signal and starts incrementing the monitoring timer. Thereafter, the data transfer time measurement unit 10 continues to increment the monitoring timer until a transfer end signal is notified from the bus monitoring unit 7. In response to the assertion of ACK, the target-side device 2 releases REQ and stops outputting data to the data bus (at time T
4). The initiator-side device 1 waits for the release of the REQ, and releases the ACK (time T5). The bus monitor 7 detects this, and issues a transfer end signal. Upon receiving the transfer end signal, the data transfer time measuring unit 10 stops incrementing the monitoring timer and clears the timer value. The above is one cycle of the data transfer process. During this series of processing, the timer value of the data transfer time measuring unit 10 is notified to the timeout judging unit 9 and monitored, but the timeout signal is not asserted because it is in normal operation.

Next, when the control signal does not reach the opposing device for some reason and the handshake process is stopped,
An operation for detecting a timeout will be described.

First, ACK from the initiator device 1
The operation in the case where the assertion is not detected by the target device 2 will be described with reference to FIG. The target device 2 outputs the transfer data to the data bus at time T1, asserts REQ at time T2, and sets the initiator device 1
To the transfer request. At time T3, ACK is asserted from the initiator device 1, and the bus monitoring unit 7 shown in FIG. 2 issues a transfer start signal at time T2. The data transfer time measuring section 10 receives this signal and starts incrementing the monitoring timer. At time T3, an ACK is asserted from the initiator device 1, but if this ACK is not detected by the target device 2, the target device 2 enters a standby state with the ACK assertion waiting after time T2, and the REQ is released. Not done.
At this time, since the bus monitor 7 cannot generate the transfer end signal, the data transfer time measuring unit 10 continues incrementing the monitoring timer. The data transfer time measurement unit 10 stops incrementing the monitoring timer when a preset timeout determination threshold value (predetermined time) is reached (time T4), and the timeout determination unit 9 performs data transfer from the monitoring timer value. It is determined to have failed, and a timeout signal is asserted (time T4). After receiving the timeout signal, the second
The bus interface unit 5 resets the internal circuit to release the asserted control signal and suspends data transfer (that is, releases the SCSI bus 3).

Next, the operation in the case where the release of the REQ from the target device 2 cannot be detected by the initiator device 1 will be described with reference to FIG. The target device 2 outputs the transfer data to the bus at time T1, and REQ at time T2.
Is asserted to notify the initiator-side device 1 of a transfer request. In response to the assertion of REQ, the initiator-side device 1 captures data on the data bus and asserts ACK to respond to the target-side device 2. And
The bus monitoring unit 7 shown in FIG. 2 issues a transfer start signal at time T3. The data transfer time measuring unit 10 receives this signal and starts incrementing the monitoring timer. If it is normal, this ACK should be released in response to the REQ release at time T4, but since the release of REQ is not detected, the initiator-side device 1 enters a standby state waiting for REQ release from time T3. , ACK is not released. Since the ACK is not released, the target-side device 2 cannot shift to the next data transfer. At this time, since the bus monitoring unit 7 cannot generate the transfer end signal, the data transfer time measurement unit 10 continues to increment the monitoring timer.
The data transfer time measurement unit 10 stops incrementing the monitoring timer when a preset timeout determination threshold is reached (time T5), and the timeout determination unit 9 determines that data transfer has failed based on the value of the monitoring timer. Assert the signal (time T5). Upon receiving the time-out signal, the second bus interface unit 5 resets the internal circuit to release the asserted control signal, and interrupts the data transfer.

In the case of data transfer from the initiator-side device 1 to the target-side device 2, a timeout is detected by the same operation as described above. (However, in this embodiment, since the monitoring is performed by the initiator device 1, the assertion of the REQ from the target device 2 cannot be detected by the initiator device 1, or the release of the ACK from the initiator device 1. Is the target device 2
In the case where it is not possible to detect the timeout, the timeout cannot be detected. To detect these cases, a third embodiment described later is required. FIG.
FIG. 5 is a block diagram illustrating a second embodiment of the initiator / target system of the present invention.

In the present embodiment shown in FIG. 6, an initiator-side device 11 which is connected to the SCSI bus 3 and acquires the access right of the SCSI bus 3 to take the initiative in data transfer,
In an initiator / target system having an initiator-side device 11 and a plurality of target-side devices 12 which are connected to the initiator-side device 11 via the SCSI bus 3 and transfer data with the initiator-side device 11 under the initiative of the initiator-side device 11, SCSI with signal and data bus
Data transfer is performed with the initiator-side device 11 by a handshake protocol using the bus 3 and the data transfer is interrupted by receiving a timeout signal indicating that the data transfer time has passed a predetermined time, and the SCSI bus 3 is released. And a plurality of target-side devices 1 using a SCSI bus 3 and a handshake protocol.
2. Data transfer is performed, the state of the control signal used for handshake is monitored, the state of the data transfer is grasped from the state of the control signal, the data transfer time is measured, and the measured data transfer time has passed a predetermined time. An initiator device 11 having a bus interface circuit 13 for outputting a time-out signal to a plurality of target devices 12 and interrupting data transfer and releasing the SCSI bus 3
It is composed of

The bus interface circuit 13 is the same as that shown in FIG. 2 described in the first embodiment, except that the bus interface circuit 13 notifies the target device 12 via the initiator device 11 via the timeout signal. .

Next, the operation of the initiator / target system of this embodiment will be described. This embodiment is the first
With respect to the embodiment, the method of using the timeout signal is further devised. In FIG. 6, the timeout signal generated in the bus interface circuit 13 of the initiator device 11 is simultaneously notified not only to the second bus interface unit 5 in the bus interface circuit 13 of the initiator device 11 but also to the target device 12. I do. The bus interface circuit 13
Stops the data transfer and releases the SCSI bus 3 as in the operation of the first embodiment. At the same time, the target device 12 also receives the timeout signal from the initiator device 11, stops the data transfer, and releases the SCSI bus 3. In the first embodiment, the monitoring of the timeout and the release of the SCSI bus 3 are performed only by the initiator-side device 1, and therefore, when the bus interface of the target-side device 2 is subjected to an improper handshake, the hardware is reset. (Suspension of data transfer and release of the SCSI bus 3) cannot be performed, and the recovery of the target-side device 2 requires the intervention of a higher-order protocol, which takes time. Indicates an upper layer application that instructs data transfer, and as a method of notifying the upper layer protocol, for example, direct notification by an interrupt signal to a processor or the like that is processing the application.) In the present embodiment, the target-side device 12 can be reset in synchronization with the initiator-side device 11, so that high-speed recovery is possible.

FIG. 7 is a block diagram showing a third embodiment of the initiator / target system of the present invention.

In this embodiment shown in FIG. 7, an initiator-side device 14 which is connected to the SCSI bus 3 and acquires the access right of the SCSI bus 3 to take the initiative in data transfer,
In an initiator / target system having a plurality of target devices 15 connected to the initiator device 14 via the SCSI bus 3 and transferring data with the initiator device 14 under the control of the initiator device 14, SCSI with signal and data bus
The data transfer with the initiator side device 14 is performed by the protocol of the handshake method using the bus 3 and the state of the control signal used for the handshake is monitored, and the state of the data transfer is grasped from the state of the control signal to reduce the data transfer time. A plurality of target-side devices 15 having a first bus interface circuit 17 for interrupting data transfer and releasing the SCSI bus 3 when the measured data transfer time exceeds a predetermined first time; Data is transferred to and from a plurality of target devices 15 using a handshake protocol using the bus 3 and the state of control signals used for handshake is monitored, and the state of data transfer is grasped from the state of the control signal to transfer data. The time is measured and when the measured data transfer time exceeds a predetermined second time. It is constituted by the initiator side device 14 having a second bus interface circuit 16 to release the SCSI bus 3 suspends over data transfer. Here, the predetermined first time and the predetermined second time are:
For example, it is set to a value within a range of about several hundred ns to several ms (however, it is not limited to a value in this range because it differs depending on circumstances of an applicable system).

The first bus interface circuit 17
Data transfer is performed with the initiator device 14 using the handshake protocol using the SCSI bus 3 and the data transfer is performed in response to a first timeout signal indicating that the data transfer time has passed a predetermined first time. A third bus interface unit for interrupting and releasing the SCSI bus 3, and monitoring the state of a control signal used for handshaking, grasping the state of data transfer from the state of the control signal, measuring the data transfer time, and measuring the measured data A first data transfer time monitoring unit that outputs a first time-out signal when the transfer time exceeds a predetermined first time. The second bus interface circuit 16 includes a control signal and a data bus. Is used to transfer data to and from a plurality of target-side devices 15 using a handshake protocol, and to transfer data. The second bus interface unit 5 that interrupts data transfer and releases the SCSI bus 3 in response to a second timeout signal indicating that a predetermined second time has elapsed, and the state of a control signal used for handshake. The second is to monitor and grasp the data transfer status from the state of the control signal to measure the data transfer time, and to output a second timeout signal when the measured data transfer time passes a predetermined second time. And a data transfer time monitoring unit.

Next, the operation of the initiator / target system of this embodiment will be described with reference to FIG.

In each of the first and second embodiments, it is assumed that the initiator-side device monitors the data transfer time. In the third embodiment, this is extended, and a bus interface circuit (first
Bus interface circuit 17) is used. Second bus interface circuit 1 of initiator-side device 14
6 is the same as the bus interface circuit 4 shown in FIG. The configuration of the first bus interface circuit 17 of the target device 15 may be the same as the configuration of the second bus interface circuit 16 of the initiator device 14,
The monitoring period (time period for counting the timer value) is a period from when the target device 15 asserts REQ to when the ACK from the initiator device 14 is released and the release is detected.

Referring to FIG. 8, an example of the operation of the bus interface circuit (first bus interface circuit 17) of the target-side device 15 will be described with reference to FIG. The period from when the target-side device 15 outputs the transfer data to the data bus to assert REQ to the initiator-side device 14 until the data transfer ends and the ACK from the initiator-side device 14 is released is monitored. . If the time required for data transfer exceeds a preset threshold value (first predetermined time), it is determined that a data transfer error has occurred, the data transfer is interrupted, and the SCSI bus 3 is released. In the present embodiment, similarly to the second embodiment, in addition to the effect that the target-side device 15 can recover autonomously when a transfer error occurs without waiting for the reset process by the higher-level protocol, the second embodiment can Since the notification of the timeout signal, which is required in the embodiment, is not required, the effect that the number of control signals can be reduced by the timeout signal can be obtained. In addition, since the target device 15 also monitors the timeout, when the initiator device 14 cannot receive the REQ from the target device 15, or when the ACK from the initiator device 14 is released, the target device 15 cancels the ACK. There is an advantage that a timeout can be detected even in a case where detection was not possible in the first embodiment, such as a case where reception was not possible.

In the above description, the data transfer time measuring unit 1
Although all 0s have been described as increment counters (monitoring timers), they can also be implemented as decrement counters. That is, the data transfer time measurement unit 10 starts decrementing from the reception of the data transfer start signal with the threshold value for judging timeout as an initial value, and stops decrementing when the counter value (timer value) becomes 0. . The timeout determination unit 9 determines that a timeout has occurred when the timer value becomes zero.

[0049]

As described above, according to the bus interface circuit of the present invention and the initiator / target system using this circuit, each of the plurality of target-side devices has a first bus interface unit. By using a bus having a control signal and a data bus, data transfer is performed with an initiator device using a handshake protocol using a bus.The initiator device uses a bus interface circuit to perform data transfer using a bus with a handshake protocol. Performs data transfer with multiple target devices and monitors the status of control signals used for handshaking, grasps the status of data transfer from the status of control signals, measures the data transfer time, and determines the measured data transfer time in advance. Data transfer when the specified time has elapsed In order to suspend and release the bus, the state of the control signal is monitored, the data transfer time is measured, and when the data transfer time exceeds a predetermined time, the data transfer is suspended and the bus is released. Even if there is no response, self-recovery can be performed at the hardware level.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an initiator / target system of the present invention.

FIG. 2 is a block diagram illustrating an example of a bus interface circuit according to the present invention.

FIG. 3 is a diagram showing an example of a timing chart 1 (during normal operation) of data transfer.

FIG. 4 is a diagram showing an example of data transfer timing chart 2 (no ACK response);

FIG. 5 is a diagram showing an example of a data transfer timing chart 3 (no REQ response);

FIG. 6 is a block diagram showing a second embodiment of the initiator / target system of the present invention.

FIG. 7 is a block diagram showing a third embodiment of the initiator / target system of the present invention.

FIG. 8 is a diagram illustrating an example of the operation of the bus interface circuit of the target-side device.

FIG. 9 is a diagram showing a timing chart 1 (during normal operation) of data transfer according to the related art.

FIG. 10 is a diagram showing a timing chart 2 (during normal operation 2) of data transfer according to the related art.

FIG. 11 is a diagram showing a timing chart 3 (when noise is mixed) of data transfer according to the related art.

FIG. 12 is a diagram showing a timing chart 4 (no ACK response) of data transfer according to the related art.

FIG. 13 is a diagram showing a timing chart 5 (no response to REQ) of data transfer according to the conventional technique.

FIG. 14 is a diagram illustrating an error detection circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 initiator-side device 2 target-side device 3 SCSI bus 4 bus interface circuit 5 second bus interface unit 6 data transfer time monitoring unit 7 bus monitoring unit 8 timeout monitoring unit 9 timeout determination unit 10 data transfer time measurement unit 11 initiator-side device 12 Target Side Device 13 Bus Interface Circuit 14 Initiator Side Device 15 Target Side Device 16 Second Bus Interface Circuit 17 First Bus Interface Circuit

Claims (18)

[Claims] The data transfer is performed by using a bus having a control signal and a data bus according to a handshake protocol and receiving a timeout signal indicating that a data transfer time has passed a predetermined time. A bus interface unit for interrupting the bus and releasing the bus, monitoring the state of the control signal used for the handshake, grasping the state of the data transfer from the state of the control signal, and measuring the data transfer time. A data transfer time monitoring unit that outputs the timeout signal when the data transfer time exceeds the predetermined time. 2. The data transfer time monitoring section grasps the state of the data transfer from the state of the control signal used for the handshake, detects the start timing and the end timing of the data transfer, and detects a transfer start signal. A bus monitoring unit that outputs a transfer end signal, and starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit, and measures the data transfer time in response to the transfer end signal. 2. The bus interface circuit according to claim 1, further comprising: a timeout monitoring unit that outputs the timeout signal when the data transfer time during the measurement has elapsed and the predetermined time has elapsed. 3. The timeout monitoring unit starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit, and ends the data transfer time measurement in response to the transfer end signal. A data transfer time measuring unit for outputting the data transfer time during the measurement, and receiving the data transfer time during the measurement output by the data transfer time measuring unit, the received data transfer time being the predetermined time 3. A time-out judging unit that outputs the time-out signal when the result of the check indicates that the predetermined time has elapsed. Bus interface circuit. 4. The data transfer time measurement unit starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit, and the data transfer time during the measurement is the predetermined time. 4. The bus interface circuit according to claim 3, wherein the measurement of the data transfer time is terminated when the time has elapsed. 5. The control signal includes an REQ signal input to the bus interface unit and indicating a data transfer request, and an ACK signal generated by the bus interface unit and indicating acknowledgment of the data transfer request. The bus interface circuit according to claim 1, 2, 3, or 4, wherein 6. An initiator-side device connected to a bus to acquire an access right of the bus to take the initiative of data transfer, and an initiator-side device connected to the initiator-side device via the bus to take the initiative of the initiator-side device. And an initiator / target system including the initiator-side device and the plurality of target-side devices for transferring the data, wherein the initiator-side device is formed by a handshake protocol using the bus having a control signal and a data bus. And the plurality of target-side devices having a first bus interface unit for performing the data transfer, and performing the data transfer with the plurality of target-side devices using the bus in accordance with the protocol of a handshake method. The state of the control signal used for handshake is monitored, and the state of the control signal is monitored. A bus interface circuit that interrupts the data transfer and releases the bus when the measured data transfer time elapses a predetermined time by grasping the state of the data transfer from the state and measuring the data transfer time. An initiator / target system comprising: the initiator-side device. 7. The bus interface circuit performs the data transfer with the plurality of target-side devices by the handshake protocol using the bus, and the data transfer time has passed the predetermined time. A second bus interface unit for interrupting the data transfer and releasing the bus in response to a time-out signal indicating the status of the control signal used for the handshake and monitoring the status of the data transfer from the status of the control signal A data transfer time monitoring unit that outputs the timeout signal when the measured data transfer time exceeds the predetermined time by measuring the data transfer time by grasping
The initiator / target system according to claim 6, further comprising: 8. An initiator-side device connected to a data bus to acquire an access right of the data bus and take the initiative of data transfer, and an initiator-side device connected to the initiator-side device via the data bus. An initiator / target system including the initiator device and a plurality of target devices for transferring the data under the initiative, wherein the bus having a control signal and a data bus is used in a handshake protocol using the bus. A plurality of first bus interface units for performing the data transfer with the initiator side device and receiving a timeout signal indicating that a data transfer time has passed a predetermined time, interrupting the data transfer and releasing the bus; And a target device of a handshake method using the bus. The data transfer is performed with the plurality of target-side devices according to protocol, the state of the control signal used for the handshake is monitored, the state of the data transfer is grasped from the state of the control signal, and the data transfer time is measured. The initiator having a bus interface circuit for outputting the timeout signal to the plurality of target-side devices when the measured data transfer time exceeds the predetermined time, and for interrupting the data transfer and releasing the bus; An initiator / target system comprising: a side device; 9. The bus interface circuit performs the data transfer with the plurality of target-side devices using the bus in accordance with the protocol of a handshake method, receives the timeout signal, interrupts the data transfer, and interrupts the data transfer. And a second bus interface unit for releasing the state, monitoring the state of the control signal used for the handshake, grasping the state of the data transfer from the state of the control signal, measuring the data transfer time, and measuring the data transfer time. The initiator / target system according to claim 8, further comprising: a data transfer time monitoring unit that outputs the time-out signal when the data transfer time exceeds the predetermined time. 10. The data transfer time monitoring section grasps the state of the data transfer from the state of the control signal used for the handshake, detects a start timing and an end timing of the data transfer, and determines a transfer start signal. A bus monitoring unit that outputs a transfer end signal, and starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit, and measures the data transfer time in response to the transfer end signal. 10. The initiator according to claim 7, further comprising: a timeout monitoring unit that outputs the timeout signal when the data transfer time during the measurement has elapsed and the predetermined time has elapsed. Target system. 11. The timeout monitoring unit starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit, and ends the measurement of the data transfer time in response to the transfer end signal. A data transfer time measuring unit for outputting the data transfer time during the measurement, and receiving the data transfer time during the measurement output by the data transfer time measuring unit, the received data transfer time being the predetermined time 11. A time-out judging unit that outputs the time-out signal when the result of the check indicates that the predetermined time has elapsed. Initiator target system. 12. The data transfer time measurement unit starts measuring the data transfer time in response to the transfer start signal output by the bus monitoring unit, and the data transfer time during the measurement is the predetermined time. 12. The initiator / target system according to claim 11, wherein the measurement of the data transfer time is terminated when the time has elapsed. 13. An initiator-side device connected to a bus and acquiring the access right of the bus to take the initiative of data transfer, and an initiator-side device connected to the initiator-side device via the bus to take the initiative of the initiator-side device. And an initiator / target system including the initiator-side device and the plurality of target-side devices for transferring the data, wherein the initiator-side device is formed by a handshake protocol using the bus having a control signal and a data bus. And performing the data transfer and monitoring the state of the control signal used for the handshake, grasping the state of the data transfer from the state of the control signal, measuring the data transfer time, and measuring the data transfer time in advance. Interrupting the data transfer and releasing the bus when a predetermined first time has elapsed The plurality of target-side devices including a first bus interface circuit; and the control using the bus for performing the data transfer with the plurality of target-side devices using the protocol of a handshake method and using the handshake. The state of the data transfer is monitored by monitoring the state of the signal, and the state of the data transfer is grasped from the state of the control signal. The data transfer time is measured when the measured data transfer time has passed a second predetermined time. And an initiator-side device having a second bus interface circuit for interrupting the bus and releasing the bus. 14. The first bus interface circuit performs the data transfer with the initiator-side device using the control signal and the data bus according to the protocol of a handshake method, and performs the data transfer time in advance. A third bus interface unit for interrupting the data transfer and releasing the data bus in response to a first timeout signal indicating that a predetermined first time has elapsed, and a state of the control signal used for the handshake Monitoring the state of the data transfer from the state of the control signal to measure the data transfer time, and when the measured data transfer time has passed the predetermined first time, the first A first data transfer time monitoring unit that outputs a time-out signal, wherein the second bus interface circuit Receiving a second timeout signal indicating that the data transfer time is longer than the predetermined second time by performing the data transfer with the plurality of target-side devices using the protocol of the handshake method. A second bus interface unit for interrupting the data transfer and releasing the bus; and monitoring the state of the control signal used for the handshake, grasping the state of the data transfer from the state of the control signal, and performing the data transfer. A second data transfer time monitoring unit that measures time and outputs the second time-out signal when the measured data transfer time exceeds the predetermined second time. The initiator / target system according to claim 13, wherein: 15. The first data transfer time monitoring unit,
The state of the data transfer is grasped from the state of the control signal used for the handshake, the start timing and the end timing of the data transfer are detected, and the first transfer start signal and the first transfer end signal are output respectively. Receiving a first transfer start signal output by the first bus monitoring unit, and starting measurement of the data transfer time,
Receiving the transfer end signal of the first step, terminating the measurement of the data transfer time, and outputting the first time-out signal when the data transfer time during the measurement has passed the predetermined first time. A timeout monitoring unit,
The second data transfer time monitoring unit grasps the state of the data transfer from the state of the control signal used for the handshake, detects the start timing and the end timing of the data transfer, and A second bus monitor that outputs a transfer start signal and a second transfer end signal, respectively, and measures the data transfer time in response to the second transfer start signal output by the second bus monitor. Start the second
A second time-out signal is output when the measurement of the data transfer time is completed in response to the transfer end signal of the second and the data transfer time during the measurement has passed the predetermined second time. The initiator / target system according to claim 14, further comprising: a timeout monitoring unit. 16. The first time-out monitoring unit receives the first transfer start signal output by the first bus monitoring unit, starts measuring the data transfer time, and outputs the first transfer end signal. A first data transfer time measurement unit that terminates the measurement of the data transfer time and outputs the data transfer time during the measurement, and the first data transfer time measurement unit that outputs the data transfer time during the measurement. Receiving the data transfer time and checking whether or not the received data transfer time has passed the predetermined first time; when the result of the check indicates that the predetermined first time has passed; A first timeout determination unit that outputs the first timeout signal, wherein the second timeout monitoring unit receives the second transfer start signal output by the second bus monitoring unit, De A second data transfer time measuring unit that starts measuring the data transfer time, receives the second transfer end signal, ends the data transfer time measurement, and outputs the data transfer time during the measurement, Receiving the data transfer time during the measurement output by the second data transfer time measuring unit, and checking whether or not the received data transfer time has passed the second predetermined time. 16. The initiator / target system according to claim 15, further comprising: a second timeout determination unit that outputs the second timeout signal when it indicates that a predetermined second time has elapsed. 17. The first data transfer time measuring section,
Receiving the first transfer start signal output by the first bus monitoring unit, and starting the measurement of the data transfer time; and when the data transfer time during the measurement has passed the predetermined first time. The second data transfer time measurement unit receives the second transfer start signal output by the second bus monitoring unit and measures the data transfer time. 17. The initiator / target according to claim 16, wherein the measurement of the data transfer time is terminated when the data transfer time during the measurement exceeds the predetermined second time. system. 18. The control signal includes a REQ signal input to the second bus interface unit and indicating a data transfer request, and acknowledges the data transfer request generated by the second bus interface unit. AC indicating
And a K signal.
18. The initiator / target system according to 11, 12, 14, 15, 16, or 17.