JP2001101090A - Inputting and outputting device for computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inputting and outputting device which can be suitably used at the time of operating data transfer with a host device by using an SCSI interface as an I/O interface. SOLUTION: In the inputting and outputting device of a computer system for operating data transfer through an interface with a host device, a data transfer control circuit counts the number of data designated from the host device and the number of data to be transferred to the host device, and when the number of data to be transferred is smaller than the number of data designated from the host device, the data transfer control circuit checks the number of REQ pulses and ACK pulses counted in a prescribed time by an REQ/ACK pulse monitoring circuit, and when the number of pulses are the same, data transfer processing in an interface control circuit is forcedly ended, and when the number of pulses is different, the data transfer processing in the interface control circuit is error-ended.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output device of a computer system, and more particularly to an input / output device which can be suitably used when data is transferred to a higher-level device using a SCSI interface as an I / O interface.

[0002]

2. Description of the Related Art A SCSI interface is known as an I / O interface for connecting a small computer such as a host computer or a workstation to peripheral devices such as a hard disk and an optical disk device.
Since the SCSI interface can use a plurality of peripheral devices in a mixed manner, it is widely used for connection between computer devices and peripheral devices.

In data transfer processing using such a SCSI interface, in order to improve the reliability of data transfer, for example, when performing data transfer from the target to the initiator, the REQ of the data transfer is used.
(Request) The target sends out transfer data synchronized with the pulse to the initiator, and the initiator sends an ACK (acknowledge) pulse to the target when the initiator normally receives the data. .

[0004]

SUMMARY OF THE INVENTION However, SCS
In the I interface, a plurality of devices are connected, so an input / output device (target) and a host device (initiator)
In data transfer processing between the devices, an interface error often occurs due to a change in transmission characteristics of each device.

[0005] One of such transmission errors is an interface error when forced termination is performed due to lower-order termination. That is, when transferring data from the target to the initiator, when the number of data to be transferred from the target side is smaller than the number of data specified by the initiator side, and a so-called lower end in which transfer data runs out occurs, the target sets REQ. After a certain time elapses after the pulse is transmitted, the data transfer forced termination process is automatically executed regardless of whether the data transfer is normally performed.

Here, the conventional input / output device is not provided with a means for confirming that the response of the ACK pulse to the REQ pulse has been reliably performed, so that the initiator responds to the REQ pulse from the target from the initiator. ACK
If the response by the pulse is delayed for a certain period or more, the SCSI phase is erroneously transited before the target receives the ACK pulse, and a SCSI interface error occurs.

Further, since the conventional device does not have a function for the target to check the validity of the transfer data, when the target executes the forced termination process of the data transfer due to the lower end, the transfer data is not normally transmitted. There is also a problem that it is not possible to judge whether or not the data transfer is performed, and the reliability of data transfer is lacking.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is performed through a SCSI interface by preventing the above-described SCSI interface error from occurring and determining whether or not transfer data is normal. It is an object of the present invention to provide an input / output device of a computer system that improves the reliability of data transfer.

[0009]

In order to solve the above-mentioned problems, an input / output device according to the present invention is an input / output device of a computer system which performs data transfer with an upper device via an interface. Interface control circuit for controlling data transfer, a data transfer control circuit for controlling data transfer performed by the upper interface control circuit, a request pulse (REQ pulse) sent to the upper device, and the upper device in response to the REQ pulse. Response pulse (ACK) sent from
A REQ / ACK pulse monitoring circuit that counts the number of pulses with an input / output device, and an input / output device control circuit that controls the operation of the higher-level interface control circuit. And counting the number of data to be transferred to the higher-level device, and when the number of data to be transferred is smaller than the number of data specified by the higher-level device, the REQ / ACK pulse monitoring circuit within a predetermined time period. The number of counted REQ and ACK pulses is checked, and if the number of pulses is the same, the data transfer process in the interface control circuit is forcibly terminated. If the number of pulses is different, the data in the interface control circuit is deleted. The transfer process is terminated with an error.

[0010] With this configuration, when the data transfer is forcibly terminated by the lower end, after the input / output device sends out the REQ pulse, the A / A
The response by the CK pulse can be reliably performed after waiting. For this reason, it is possible to prevent the occurrence of a SCSI interface error due to the erroneous transition of the SCSI phase at an undefined timing before the host device transmits the ACK pulse.

Further, the input / output device of the present invention further comprises a data check circuit for checking a state of data to be transferred to the higher-level device. If the transferred data is checked for validity and the state of the transferred data is valid, the data transfer processing in the upper interface control circuit is forcibly terminated, and the state of the data transferred by the data transfer processing is not valid. Is characterized in that the data transfer processing in the upper interface control circuit is terminated with an error.

With this configuration, when data transfer is forcibly terminated by lower-order termination, it is possible to confirm whether or not the data is valid, thereby improving the reliability of the transferred data. it can.

Further, the input / output device of the present invention further comprises the above R
A timer means for detecting a timeout of a pulse monitoring time when the ACK pulse is not responded within a predetermined time in the EQ / ACK pulse monitoring circuit, and controlling the upper interface control when a timeout is detected by the timer means; The data transfer processing in the circuit is terminated with an error.

With this configuration, if there is no response to the ACK pulse within a certain period of time, error processing is performed, which speeds up processing in the entire input / output device and reliability of data transfer. Can be improved.

Further, the input / output device of the present invention is further characterized in that the input / output device control circuit includes a memory means, and stores an event when the pulse monitoring timer means detects a timeout in the memory means. I do.

With such a configuration, by reading the record on the memory later, the A
By verifying whether the response of the CK pulse is delayed, it is possible to accurately grasp an event when the data transfer performance is reduced.

Further, the input / output device of the present invention includes a lower interface control circuit for controlling the lower interface while the input / output device is connected to the lower device via a lower interface. May be configured to control data transfer between the lower interface control circuit and the upper interface control circuit.

Also, the input / output device of the present invention can be suitably used when the upper interface is a SCSI interface.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration of a first embodiment of an input / output device according to the present invention.
5 is a flowchart for explaining a data transfer operation in the device of FIG. As shown in FIG. 1, the input / output device 1 is connected to a higher-level device (not shown) via an interface 21 and to a lower-level device (not shown) via an interface 22. In this example, the SCSI interface 21 is used as an I / O interface for data transfer with a higher-level device (not shown).

The input / output device 1 is a SCSI interface control circuit 11 for controlling a SCSI interface 21.
And interface 2 for data transfer with lower-level devices
2, a lower interface control circuit 12 for controlling
A direct transfer control circuit 13 for controlling data transfer between the CSI interface control circuit 11 and the lower interface circuit 12, an input / output device control circuit 14 for controlling the operation of the SCSI interface control circuit 11, and an interrupt when an interrupt occurs And an interrupt control circuit 15 for sending a generated signal to the input / output control circuit 14.

Further, the input / output device 1 includes a SCSI interface 21 and a SCSI interface control circuit 11.
REQ / monitoring the status of data transfer provided between
ACK pulse monitoring circuit 16, also SCSI interface 21 and SCSI interface control circuit 1
1 and a data check circuit 17 for checking the presence or absence of a data error at the end of data transfer.
The input / output control circuit 14 is also connected to the REQ / ACK pulse monitoring circuit 16 and the data check circuit 17.

The direct transfer control circuit 13 has a SCSI
It controls data transfer between the interface control circuit 11 and the lower interface control circuit 12. Further, the direct transfer control circuit 13 includes a counter for counting the number of data to be transferred, and counts the number of data to be transferred, and the number of data transferred from the input / output device 1 to the upper device is smaller than the number of data specified by the higher device. In this case, the lower end is detected and the interrupt control circuit 15 sends a “DATA SHOR
T signal is output.

In the interrupt control circuit 15, this "DAT
"A SHORT signal" and "DATA SHORT
To the input / output device control circuit 14.

The REQ / ACK pulse monitoring circuit 16 counts the number of REQ pulses sent from the input / output device 1 to the host device and the number of ACK pulses sent from the host device to the input / output device 1, and counts the number of both pulses. Are equal to each other, the number of each of the REQ pulse and the ACK pulse is displayed.

When the data transfer is completed, the data check circuit 17 checks for the presence or absence of a data error and displays it, and if a data error has occurred, displays the content of the error.

When the input / output device control circuit 14 receives the "DATA SHORT interrupt signal" from the interrupt control circuit 15, the input / output device control circuit 14 checks with the pulse monitoring circuit 16 whether the number of both the REQ pulse and the ACK pulse is equal. Is performed, and if they are equal, the SCSI interface control circuit 11 is instructed to forcibly end data transfer, and if they are not equal, an error end is instructed. REQ pulse and AC
If the number of K pulses is equal and the data transfer forced termination is instructed, the data check circuit 17 is checked whether there is an error in the data transfer, and if there is no error and the data transfer processing is properly performed, Resets the SCSI interface control circuit 11 and instructs error termination processing if an error occurs.

Next, a data transfer operation in the input / output device 1 according to the first embodiment of the present invention will be described with reference to FIG. First, data transfer from the target to the initiator is started in the SCSI interface 21 (step 201). When the transfer data runs out before the number of data designated by the initiator during the execution of the data transfer processing, and a so-called lower end occurs, the direct transfer control circuit 13 detects this lower end, and the interrupt control circuit 15 A DATA SHORT signal "is notified. Upon receiving this signal, the interrupt control circuit 15 outputs “D
An ATA SHORT interrupt signal "is notified to the input / output device control circuit 14 (step 202).

The input / output device control circuit 14 receiving this notification
Checks with the REQ / ACK pulse monitoring circuit 16 whether the number of both the REQ pulse and the ACK pulse within the predetermined time is the same (step 20).
3). If the number of REQ pulses and the number of ACK pulses are the same (step 203, YES), the input / output device control circuit 1
4 instructs the SCSI interface control circuit 11 to forcibly end the data transfer (step 204). Also,
When the REQ pulse and the ACK pulse are different (step 2
03, NO) waits for the elapse of a predetermined time (step 2).
07), error termination is instructed.

When the forced termination of the data transfer ends normally,
The input / output device control circuit 14 checks whether the data transferred from the data check circuit 17 is valid. If there is no error (step 205, NO), the data displayed from the counter of the direct transfer control circuit 13 The number of data transfers is compared with the number of data transfers displayed on the counter of the REQ / ACK pulse monitoring circuit 16 to confirm that the number of data transfers is equal, and the SCSI interface control circuit 11
A reset instruction of the internal data transfer circuit is issued (step 206), and the forced termination process of the data transfer due to the lower end in the data transfer process from the target to the initiator ends. If the data check circuit 17 detects an error in the transfer data in step 205 (step 205, YES), the data transfer forcible termination process is terminated with an error.

FIG. 3 is a diagram showing the configuration of a second embodiment of the input / output device according to the present invention. As shown in FIG. 3, the input / output device 30 according to the second embodiment includes a REQ / ACK pulse monitoring circuit 16 and an REQ
A / ACK pulse monitoring timer 31 is provided so that a timeout is reported to the interrupt control circuit 15 when there is no response of the ACK pulse to the REQ pulse output from the input / output device for a certain period of time.

This REQ / ACK pulse monitoring timer 31
Has a relatively small timer value. When no ACK pulse response to the REQ pulse is received within the set time, a timeout is detected and a timeout signal is sent to the interrupt control circuit 14. Upon receiving the timeout signal, the interrupt control circuit 15 notifies the input / output device control circuit 14 of an interrupt. The input / output control circuit 14 having received the interrupt sends an error signal to the SCSI interface control circuit 11, The circuit 11 executes error termination. Therefore, when the AKC pulse is not responded for some reason, the processing of the entire apparatus is promoted.

Further, in the present embodiment, the memory 32 is connected to the input / output device control circuit 14 so that the event when the above-mentioned timeout occurs is recorded on the memory 32. By reading the record on the memory 32 later, it is possible to verify when the response of the ACK pulse is delayed, and it is possible to always monitor the event when the data transfer performance is reduced. For example, performance degradation occurs when data is being transferred and multiplex processing is performed, and there is a problem in the processing at that time. The performance that occurs when the confirmation of data transfer completion by the firmware is delayed and the negation of the last ACK pulse is delayed. Refers to a decline. In addition, REQ
Since the configuration other than the / ACK pulse monitoring timer 31 and the memory 32 is the same as the configuration of the first embodiment, the same reference numerals as those used in FIG. 1 are used and the description is omitted here.

FIG. 4 is a flowchart of an operation process in the input / output device of the second embodiment shown in FIG. When there is no response to the ACK pulse in the pulse monitoring circuit 16 (step 208, NO), the state of no response exceeds the timer value set in the monitoring timer 31, and the REQ / ACK pulse monitoring timer 31 detects a timeout ( Step 20
9, YES), the input / output device control circuit 14 receives the timeout interrupt signal from the interrupt control circuit 15, and
An error end signal is output to the CSI interface control circuit 11. On the other hand, if there is an ACK pulse response within the set timer value (step 208, YES), R
The EQ / ACK pulse monitoring circuit 16 continues to monitor the number of pulses, and performs the processing after step 203 described in FIG. The processing of steps 201 to 207 is performed in the first
Since the processing is the same as that in the embodiment, the description is omitted here.

[0034]

As described above, according to the input / output device of the present invention, when the data transfer from the target to the initiator via the SCSI interface is forcibly terminated by lower-order termination, the response of the ACK pulse is ensured. Can be confirmed whether or not. Therefore, AC
It is possible to effectively prevent occurrence of a SCSI interface error due to transition of the SCSI interface at an undefined timing before K pulse transmission.

Further, when the data transfer is forcibly terminated by the lower end, it is possible to confirm whether the transferred data is valid or not, so that the reliability of the transferred data can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of an input / output device according to the present invention.

FIG. 2 is a flowchart for explaining a data transfer operation in the device of FIG. 1;

FIG. 3 is a diagram showing a configuration of a first embodiment of an input / output device according to the present invention.

FIG. 4 is a flowchart for explaining a data transfer operation in the device of FIG. 3;

[Explanation of symbols]

 1, 30 I / O device 11 SCSI interface control circuit 12 Lower interface control circuit 13 Direct transfer control circuit 14 I / O device control circuit 15 Interrupt control circuit 16 REQ / ACK pulse monitoring circuit 17 Data check circuit 21 SCSI interface 22 Lower interface 31 REQ / ACK pulse monitoring timer 32 memory

Claims (6)

[Claims] An input / output device of a computer system for performing data transfer with a higher-level device via an interface, wherein the higher-level interface control circuit controls an interface with the higher-level device, and controls data transfer performed by the higher-level interface control circuit. A data transfer control circuit for counting the number of pulses of a request pulse (REQ pulse) sent to the host device and a response pulse (ACK pulse) sent from the host device in response to the REQ pulse. An ACK pulse monitoring circuit and an input / output device control circuit for controlling the operation of the higher-level interface control circuit, wherein the data transfer control circuit specifies the number of data specified by the higher-level device and the data to be transferred to the higher-level device. And counts the number specified by the host device. When the number of transfer data is smaller than the number of data, the REQ / ACK pulse monitoring circuit checks the number of REQ pulses and ACK pulses counted within a predetermined time, and determines that the number of pulses is the same. An input / output device for a computer system, wherein the data transfer processing in the interface control circuit is forcibly terminated, and when the number of pulses is different, the data transfer processing in the interface control circuit is terminated with an error. 2. The input / output device according to claim 1, wherein
The input / output device further includes a data check circuit for checking a state of data to be transferred to the higher-level device, and when the data transfer process in the interface control circuit is forcibly terminated, further checks the validity of the transferred data. If the state of the transferred data is valid, the data transfer processing in the upper interface control circuit is forcibly terminated. If the state of the data transferred by the data transfer processing is not valid, the upper interface control circuit An input / output circuit of a computer system, wherein the data transfer process in the computer is terminated with an error. 3. The input / output device according to claim 1, wherein the input / output device further includes a pulse monitoring time when the REQ / ACK pulse monitoring circuit does not respond to the ACK pulse within a predetermined time. An input / output device for a computer system, comprising: timer means for detecting a time-out, wherein when the time-out is detected by the timer means, the data transfer processing in the higher-level interface control circuit is terminated with an error. 4. The input / output device according to claim 3, wherein
The input / output device of a computer system, wherein the input / output device control circuit includes a memory unit, and stores an event when the pulse monitoring timer unit detects a timeout in the memory unit. 5. An input / output device according to claim 1, wherein said input / output device is connected to a lower device via a lower interface and controls said lower interface. An input / output device for a computer device, wherein the data transfer control circuit controls data transfer between the lower interface control circuit and the upper interface control circuit. 6. The input / output device according to claim 1, wherein the upper interface is an SCS.
An input / output device for a computer system, which is an I interface.