JP2002171290A - Atm exchanging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM exchanging device which avoids waste of network resources on the occurrence of congestion. SOLUTION: Message types and processing modes are stored in the ATM exchanging device correspondingly to connections. When discard of a cell occurs, the connection to which the discarded cell belongs is set to an discard mode by a cell discard control circuit 300, and cells constituting the same message as the discarded cell out of following cells are discarded, and the processing mode is switched back to a transfer mode upon detection of the delimiter of the message, and then following received cells are transferred as normal. Consequently, cells which are useless in a reception terminal are discarded in a network to prevent an influence of congestion from being distributed to other connections, and thus throughput reduction in the entire network is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell switching device used in an ATM type packet communication network, and more particularly to an ATM having a function of controlling useless ATM cells.
The present invention relates to a cell switching device.

[0002]

2. Description of the Related Art In a packet communication network,
Information transmitted by each terminal device is assembled into a message of a specific format according to a protocol for transfer control. Each message is generally of variable length, the length of which varies depending on the data to be transmitted.If this message is sent out to the network as it is, software exchange is required in the exchange process, and the communication speed is increased. Is inconvenient.

[0003] Therefore, a variable-length message is divided into a plurality of fixed-length packets called "cells", and only the fixed-length cells are processed in a network. ATM networks have been developed that can process data at high speed. According to the ATM system, in the cell processing in the network, it is not necessary to be conscious of the message structure of the upper level, and the cell transfer processing and the like can be performed by focusing only on the header part of each ATM cell.

In the ATM system, the maximum bandwidth required by each terminal device is not always occupied among the communication bandwidths of the network side, and the bandwidth is used only when transmission data is present. A multiplexing gain called the statistical multiplexing effect can be expected. Therefore, it is possible to arbitrarily set the cell discard rate in the network depending on the call admission control method.

[0005] Of the cells input to the ATM exchange, a plurality of burst data cells may concentrate on a specific output line and exceed the bandwidth capacity of the output line, causing a congestion state. In this case, it is necessary to perform a discard process for an excessive cell exceeding the capacity of the buffer, but for the discard process of the cell in the congested state, for example, the cell is selectively discarded according to a discard priority assigned to each cell. The method is described on pages 131-132 of the document "Introduction to B-ISDN" (Ohm). When the discard control based on the priority is not adopted, new arrival cells that cannot be accumulated due to lack of buffers are discarded one after another. In any of the above cases, in the conventional method, regarding the discarded cells,
No consideration is given to the connection to which each cell belongs or the relationship with the message unit of the higher-level protocol.

[0006]

However, for each terminal device connected to the ATM network, if at least one cell constituting a received message is subjected to a discarding process during transmission, a normal message is reconstructed. Can not be done. When cell discarding occurs, cells before the discarded cell constituting the same message or cells following the discarded cell become meaningless cells even if they are normally received by the terminal device.

In the conventional ATM network, no consideration is given to the treatment of another cell in the same message, which has become meaningless to the receiving terminal device due to the above-described cell discard. For this reason, the above-mentioned insignificant cells on the output line in the congested state waste the bandwidth, or the buffer area of the exchange is used by the insignificant cells arriving at the exchange after the occurrence of the cell discard, and the other valid cells are used. The switching resources and the use of the transmission line band are hindered, which may cause new cell discarding.

An object of the present invention is to actively discard cells that have become meaningless to the receiving terminal device in the network so that other significant cells can be prevented from being discarded as much as possible. The present invention provides an ATM switching device and a cell discard control method.

[0009]

In order to achieve the above object, according to the present invention, when a cell is discarded on a connection, a cell belonging to the connection is set to a valid cell belonging to the next message. Until the message arrives, the upper message unit is delimited and discarded.

In order to realize such cell discarding, the ATM switching apparatus of the present invention stores, for example, a processing mode of a cell corresponding to each connection, and associates a new cell with the cell every time a new cell arrives. The cell transfer / discard is determined by referring to the processing mode to be performed. For the processing mode of each connection, for example, at first, the mode of all connections is set to “transfer mode”,
When the buffer control circuit that controls cell writing to the buffer memory discards the cell, the mode of the connection corresponding to the discarded cell is changed to “discard mode”, and the last cell (the last cell of the message to which the discarded cell belongs) The mode of the connection may be returned to the “transfer mode” again when the (separation cell) is detected.

The detection of the delimiter cell may be changed according to the type of message used on each connection. For example, the position of the field to be inspected in each cell and the value to be detected are changed depending on the message type, and it is determined whether or not the cell is a message separation cell.

[0012] Further, depending on the connection, there is a case where the discard control of the cell is not performed. Therefore, the type of the upper message is registered for each connection, and upon arrival of the cell, whether or not the cell is the connection for which the discard control is to be performed. Should be determined. Examples of the type of the upper message used on the connection include “AAL Type 5” and “Type 3/4”. These types are used for connection-type and connectionless-type data communication, and [AAL Type 5] has an end indication in the ATM header, and [Type 3/4] has an end indication in the SAR header. is there. To determine which connection each cell belongs to, refer to the virtual path identifier “VPI” and the virtual channel identifier “VCI” included in the ATM header of each cell.

[0013]

According to the present invention, by performing cell discard control on a message-by-message basis for connections that have encountered cell discard, the bandwidth on the output line can be used effectively. In addition, by actively discarding meaningless cells, network resources can be allocated to valid cells on other connections, avoiding the occurrence of new congestion and causing cell discard to occur in many messages. There is an advantage that dispersion can be prevented.

[0014]

FIG. 1 shows an AT to which the present invention is applied.
1 shows the overall configuration of an M switching device. An ATM switching device using a common buffer type switch is described in, for example, Japanese Patent Application Laid-Open No. 2-1669, "Switching System and Configuration Method".

Input lines 151 to 15N and output line 1
61 to 16N are respectively connected to a subscriber terminal device or another ATM switching device. Input line processing circuit 101
10 to 10N are optical / electrical conversions, transmission frame terminations for each ATM cell input from the input lines 151 to 15N,
Processing such as cell synchronization, header conversion, and addition of internal information required by the switch circuit are performed.

The cell to which the internal information is added has the internal cell format shown in FIG. 9 and, after being input to the switch circuit 200, of the output lines 160 to 16N determined by the routing information (outgoing line number) 902. Output to either. Each cell output from the switch circuit 200 is subjected to processing such as cell synchronization, transmission frame termination, and electrical / optical conversion in output line processing circuits 111 to 11N, and then output to each output line 161 to 16N. Is done.

The cells for call control or network management are distributed to the output line 160 and input to the control circuit 121. The control circuit 121 controls the control line 1 according to the information of the input cell.
70 and input line 150, switch circuit 20
0 or the line processing circuits 101 to 10N and 111 to 11N are controlled or monitored. Further, a cell including control information to be transmitted to another ATM switching device or terminal device is generated, and input to the switch circuit 200 from the input line 150.
Transfer to destination device.

FIG. 2 shows an embodiment of an ATM switch circuit unit to which the present invention is applied. The switch circuit 200 includes a multiplexing circuit 201, a cell discard control circuit 300, a common buffer 203, a buffer control circuit 800, and a separation circuit 20.
And 2. The cells input in parallel from each input line are converted into serial cell rows by the multiplexing circuit 201,
It is input to the cell discard control circuit 300.

The cell discard control circuit 300 makes a judgment on passage / discard for each input cell. Cells passing through the cell discard control circuit 300 are stored in the buffer control circuit 80.
0 assigns a storage area in the common buffer 203. Buffer area shortage, buffer control circuit 8
If the input cell is discarded at 00, the result is transmitted to the cell discard control circuit 300 via the discard detection signal line 850, and the pass / discard attribute information is updated. When the process of storing one cell in the buffer memory is thus completed, the cell discard control circuit 300 starts processing the next cell. The buffer control circuit 800 outputs a read address at a predetermined timing that matches the distribution cycle of the separation circuit 202, and reads cells from the common buffer 203.
The read cell is output by the separation circuit 202 to any output line specified by the routing information.

FIG. 3 shows an embodiment of the cell discard control circuit 300 in the ATM switch circuit. When the cell discarding control circuit 300 takes in the cells serialized by the multiplexing circuit 201 one by one, the cell analysis circuit 301 extracts a connection identifier from each cell and gives the connection identifier to the connection attribute table circuit 500 as an address.

The connection attribute table circuit 500 includes:
The message type used in the connection specified by the connection identifier and the current processing mode for cells on the connection are output. It should be noted that VPI and VCI in an ATM cell can be used as the connection identifier. When the upper protocol is, for example, “AAL Type 3/4”, the above V
MID can be used in addition to PI and VCI.

As the processing mode, three values of “transfer”, “replace”, and “discard” are prepared. In accordance with the value of the processing mode, the selector 302 determines the output cell from the cell analysis circuit 301 and the end cell 30 as shown in FIG.
3. Select and output one of the empty cells 304.

The connection attribute table circuit 500 shown in FIG.
Values that are not subject to cell discard control are represented by “0”, and message types to be subject to cell discard control are represented by assigning values in order from “1”. Even if the message type used on a certain connection is subject to cell discard control, “0” is set if exceptional cell discard control is not performed for that connection. This makes it possible to select whether or not to perform cell discard control on a connection using a message type to be subjected to cell discard control. When the selector 302 selects the end cell 303, the type register circuit 501 outputs a message type value for selecting the format of the end cell to be output.

The above-described processing mode value and message type value are stored in the type register circuit 501 and the mode register circuit 502 for each connection. The type register circuit 501 and the mode register circuit 502 each select a register to be read according to the value of the connection identifier input from the input line 350, and output the value of the selected register as it is as the message type value. Regarding the processing mode value, when the message type value is “0”, the selector 503 replaces the value stored in the selected register.
Output a value “0” indicating the transfer mode.
If the message type value is other than "0", the value of the selected register is output as it is.

In the cell discarding control circuit 300, the cells taken in from the multiplexing circuit 201 are input to the separation cell detection circuit 700 together with the cell analysis circuit 301. The delimiter cell detection circuit 700 detects a cell serving as a delimiter of a message from input cells, and selects a position of a check field in an ATM cell and its value.

FIG. 7 shows an embodiment of the separation cell detection circuit 700. In the delimiter cell detection circuit 700, the input cells are temporarily stored in the memory 701, and then, when a message type value is input from the connection attribute table circuit 500, the offset register circuit 702 and the mask register circuit 703 are compared. From the value register circuit 705, a register to be read is selected in accordance with each type value, and a value set for each type is output.

The offset value output from the offset register circuit 702 specifies a specific field position in a cell to be read from the memory. Data read from the memory is input to the AND circuit 704. The mask value output from the mask register circuit 703 is one in which 0 is set in the read data other than the bit position to be inspected, and the AND circuit 704 reads the mask value and the read value from the memory 701. AND with data
And outputs the result to the coincidence detection circuit 706. The comparison value output from the comparison value register circuit 705 is a bit pattern indicating a bit position serving as a delimiter cell.
The output value of the circuit 704 is compared, and if the values match, a detection signal indicating that a separation cell has been detected is output.

As the offset value, the mask value and the comparison value, when the data to be read is one byte, for example, “AAL Type 5”, “3”, “10”,
What is necessary is just to set "2". In the case of “AAL Type 3/4”, “5”, “192”, and “64” may be set, respectively.

The connection attribute table circuit 500
After outputting the processing mode value and the message type value for performing the above-described cell discard control, the buffer control circuit 800
Result output from the memory and the delimiter cell detection circuit 700
The current processing mode is updated according to the detection result output from. The mode is updated, for example, according to the change logic shown in FIG. When the above mode has been updated,
The processing of one input cell in the cell discard control circuit is completed, and the above-described processing is repeated for the next cell.

The reason why the processing mode includes "replacement" in addition to "transfer" and "discard" is to inform the receiving terminal that cell discarding has occurred and to make it impossible to correctly assemble the message. This is to promptly notify. By this notification, the receiving terminal device does not needlessly continue to reserve unnecessary resources, and can quickly execute an operation when a message cannot be normally received. In addition, the notification cell may be repeatedly generated and transmitted a plurality of times in case a cell for notifying the cell discarding is discarded on the way.

Next, a method of detecting cell discard will be described. FIG. 8 shows an embodiment of a buffer control circuit having a cell discard detection function. In the switch circuit of the common buffer system, an arbitrary empty address is assigned to the queue corresponding to the output line each time without preparing the output queue corresponding to each output line at a fixed position in the buffer, and the empty area of the buffer memory is allocated. And a plurality of queues in a logical FIFO format that are structured in a list with pointer addresses. When a new cell is input, the address of the cell storage area to be connected to each queue (write address), the storage area of the cell to be taken out of each queue corresponding to the output line (read address), and the order between the cell storage areas The relationship is centrally managed by the buffer control circuit 800.

The storage area in the buffer of each cell is determined every time a cell storage request is generated, and an arbitrary free address at that time read from a free address buffer (FIFO) is allocated. The addresses of the storage areas that have been removed from the queue and have become vacant are sequentially registered in the vacant address buffer. Therefore, in this type of switch circuit, as long as there is a free address in the free address buffer, an input cell can be connected to a queue corresponding to an arbitrary output line. However, when there are no more free addresses in the free address buffer, the input cells cannot be written to the buffer and must be discarded. Whether or not cell discard has occurred can be detected by determining whether or not a free address remains in the free address buffer. If the length of each queue is limited in advance, it is possible to detect whether or not a new input cell is discarded based on the value of each queue length counter.

The cells output from the cell discard control circuit 300 are input to the common buffer 203 and the buffer control circuit 800 as shown in FIG. Buffer control circuit 80
As shown in FIG. 9, each cell input to 0 has an empty cell display section 901 and internal line number section 902 which are internal information added by the input line processing circuits 101 to 10N. In this example, the VPI and VCI of each cell are written in a part of the outgoing line number section 902 for simplicity. You may arrange | position in front of the display part 901.
In the empty cell display section 901, a value “1” is set when the cell is an empty cell, and “0” is set in other cases.

The header separation circuit 801 extracts the header portion of the input cell, and outputs a display signal indicating whether or not the cell is empty and a signal indicating the write line number in the fields 901 and 902 according to the contents. When the input cell is an empty cell, a write permission signal is not output from the NOR circuit 802, so that no buffer area is allocated and the common buffer 203
Is not written to the cell. In this case, the AND circuit 803 does not output a discard detection signal regardless of the presence or absence of an empty address.

If the input cell is not an empty cell, the outgoing line number is input to the queue length counter 804 and the address register circuit 808 as a write line number for queue selection. The address register circuit 808 has an empty address FIFO 807 at the time of initialization or the previous cell write.
From the common buffer 203 as the write address of the common buffer 203.
The vacant address obtained from 807 is output as the next write address. Thereby, the common buffer 203
The input cell and the next write address are written in pairs at the write address positions in FIG. By storing the cell and the next address in a pair as described above, when one cell to be output to a certain line is read from the common buffer memory 203, it is possible to know the next cell address to be read on that line. By holding this until the next read operation is performed,
Cells can be read out sequentially from the head cell for each queue.

On the other hand, the next write address obtained from the empty address FIFO 807 is stored in the address register circuit 80.
8 is stored as the write address of the next cell in the queue. When the next cell to be output to the same output line is input, by performing a cell write operation using the next write address read from the address register circuit 808, the common buffer is paired with the previous cell. The next cell can be written to a memory location stored in the memory 203 and pointed to by the address (pointer address), whereby a list-structured queue corresponding to a line can be configured.

When a cell is written in the common buffer memory, the value of the queue length counter 804 is increased by one. When the empty address FIFO 807 becomes empty, a signal indicating that there is no empty area (buffer full) is output to the signal line 851. In this state, a discard detection signal is output from the AND circuit 803 and the NOR circuit 80
2 does not output a write enable signal, so that writing of a new input cell to the buffer is suppressed. Also, the value of the queue length counter 804 is held as it is.

When a cell is read from the common buffer 203, a line number for designating an output line queue from which a cell is to be read is output from the read control table 805 in synchronization with a timing signal generated by the output timing counter 806. The line number is input to the queue length counter 804 and the address register circuit 808. The queue length counter 804 selects a register storing the queue length of the line number, and when the queue length is “1” or more, decreases the count value by one and outputs a read permission signal. When the queue length is “0”, the count value does not decrease and the read permission signal is not output.

When the read enable signal is output, a read address is output from the address register circuit 808, and based on the address, the common buffer 203 outputs one address.
The cell and address of the pair are read. The address is input to the address register circuit 808 and stored as the next cell read address of the output line. The used read address used for accessing the common buffer is released as a free address and stored in the free address FIFO 807.

According to this embodiment, cell discarding is performed for each message of the upper protocol, so that the load on the network at the time of congestion is reduced, and it is possible to suppress the discarded cells from spreading to other messages. Further, since it is possible to promptly notify the receiving terminal of the connection in which the cell has been discarded that the reception of the message being received cannot be normally completed, useless use of resources in the receiving terminal device can be avoided.

(Embodiment 2) FIG.
A system configuration in which a cell discarding control circuit 300 is added as an external circuit to a conventional switching device having no cell discarding control function inside 00 is shown. FIG.
In the example shown in FIG. 7, a configuration example is shown in which the cell discard control circuit 300 is simultaneously provided when the connectionless service function module 1001 is added to the exchange. The "connectionless service function" referred to here means a function described in, for example, Japanese Patent Application Laid-Open No. 4-179336 "Connectionless Message Exchange Processing Method in ATM System". The cells are distributed to the output line 1060 by the switch circuit 1000.

On a connection using the connectionless service function, "AALType 3/4" is generally used. A series of sequence numbers are given to cells communicated by a connection using this type. Connectionless service function (C
The LSF) module 1001 can detect cell loss due to other causes in the network by monitoring continuity of sequence numbers for each connection in addition to detecting cell discard due to buffer overflow of the switch. .

If cell loss occurs due to any of the above causes,
The CLSF module 1001 outputs a cell discard detection signal and notifies the cell discard control circuit 300 via the signal line 1070. The cell discarding control circuit 300 executes a cell discarding process on a subsequent cell to be input to the CLSF module 1001 as in the first embodiment.

According to the present embodiment, a cell discarding control function can be added to an existing exchange in the form of an external circuit, and an unnecessary cell selective discarding service can be performed in a specific range of connections. Further, according to the system configuration shown in FIG. 10, since the input of extra cells to other additional modules such as the connectionless service function is prevented, the load on these additional functions is reduced and the processing capacity is increased. Can be.

(Embodiment 3) FIG. 11 shows a configuration in which the present invention is applied to an ATM switching apparatus having a switch circuit of an output buffer system. For the principle of the switch circuit of the output buffer system, see, for example, the document “Output Buffer Switch Architecture Fore-Synchronous Transfer Mode (Original Title: Output Buffer Switch Archite).
cture for Asynchronous Transfer Mode.) '' (ICC '89, Pr
oceeding pp.99-103).

The switch circuit 200 includes a multiplex circuit 1101
And a plurality of address filters 11 provided for output lines.
02, a cell discard control circuit 300 connected to each address filter, an output FIFO buffer 1104 and a counter 1103 connected to each cell discard control circuit 300
After the cells input in parallel from the input line are converted into a serial cell string by the multiplexing circuit 1101, the cells are taken into the cell discard control circuit 300 corresponding to the output line by the address filter 1102, and the pass / discard judgment is made. I do. Cells that have passed through the cell discard control circuit 300 are output from the FIFO.
The data is stored in the buffer 1104 and output to each output line via the output line processing circuit 11 (111 to 11N) shown in FIG.

Each time a cell is stored in the output FIFO buffer 1104, the value of the counter 1103 is incremented by one.
When the counter value reaches the capacity of the buffer 1104 or exceeds a preset threshold, the signal line 11
The cell discard detection signal is output to 50, and the occurrence of a discarded cell is notified to the cell discard control circuit 300. In this state,
The new input cell is discarded without being stored in the buffer 1104. The operation of each cell discard control circuit 300 is the same as in the first and second embodiments.

If the counter value does not exceed the capacity of the buffer or does not exceed the threshold value, the input cell is stored in the buffer, and when the cell is read, the value of the counter is decreased by one. . If the counter value is 0 at the time of the read operation, the cell is not read because the buffer is empty.

[0049]

According to the present invention, cells relayed by an exchange are subjected to selective discard processing of cells based on a higher-level message structure, and cells which have become insignificant for a receiving terminal device are actively removed from the network. In order to eliminate it,
There is an advantage that network resources can be effectively used and cell discard due to congestion can be prevented from spreading to other messages. In addition, when a cell is discarded, the switching device notifies the receiving terminal device of the cell to that effect, so that the receiving terminal does not continue to wastefully reserve resources, and the message is normally received. There is an advantage that it is possible to promptly shift to a measure to be taken in the case where it cannot be performed.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing one embodiment of an ATM switching device to which the present invention is applied.

FIG. 2 is a diagram showing one embodiment of a common buffer type switch circuit to which the present invention is applied.

FIG. 3 is a diagram showing one embodiment of a cell discard control circuit 300 in FIG. 2;

FIG. 4 is a diagram showing a relationship between an operation of a selector 302 and a processing mode in FIG. 3;

FIG. 5 is a connection attribute table circuit 5 in FIG. 3;
The figure which shows 1 Example of 00.

6 is a connection attribute table circuit 5 in FIG.
The figure which shows the rewriting operation | movement of the mode of 00.

FIG. 7 is a diagram showing one embodiment of a break cell detection circuit 700 in FIG. 3;

FIG. 8 is a diagram showing one embodiment of a buffer control circuit 800 in FIG. 2;

FIG. 9 is a diagram showing an example of an internal cell format.

FIG. 10 is a block diagram showing another embodiment of the ATM switching apparatus to which the present invention is applied.

FIG. 11 is a diagram showing an embodiment of an output buffer type switch circuit unit to which the present invention is applied.

[Explanation of symbols]

101 to 10N ... input line processing circuits, 111 to 11N ...
Output line processing circuit, 121: control circuit, 200: ATM
Switch circuit, 201: multiplex circuit, 202: separation circuit,
203: common buffer, 250: next read address signal line, 300: cell discard control circuit, 301: cell analysis circuit, 302: selector, 303: end cell generation circuit, 3
04: empty cell generation circuit, 500: connection attribute table circuit, 501: type register circuit, 502: mode register circuit, 503: output suppression circuit, 700: separation cell detection circuit, 701: memory, 702: offset register circuit, 703 ... Mask register circuit, 704 ...
AND circuit, 705: comparison value register circuit, 706: match detection circuit, 800: buffer control circuit, 850: discard detection signal output line, 851: free address absence signal output line, 1000: ATM switch circuit, 1001: connectionless service Functional module, 1070 ... cell discard detection signal output line, 1102 ... address filter, 11
50 ... Cell discard detection signal output line.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission Date] December 6, 2001 (2001.12.
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Dewa 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Information and Communication Division, Hitachi, Ltd. 5K030 GA13 HA10 HB09 HB29 KX27 LC18

Claims (4)

[Claims] 1. An ATM switching apparatus which temporarily stores input cells received from an input line and outputs the cells to any one of output lines determined by header information. An ATM switching device, comprising: cell discard control means for discarding a cell constituting the same higher-level message as a discarded cell among subsequent cells having the same logical connection as the discarded cell. 2. The terminal device according to claim 1, wherein the cell discarding control means reports from the terminal device at the time of parameter setting or call setting specified by a maintenance command in advance that detection of a break of an upper message of the discarded cell or execution of a discarding operation on a subsequent cell is performed. 2. The ATM switching device according to claim 1, wherein the switching is performed based on the parameter values. 3. The cell discarding control means sends a cell for notifying a receiving terminal of the cell of the discard of a subsequent cell, instead of a next cell having the same logical connection as the discarded cell. The ATM switching device according to claim 1 or 2, wherein 4. A plurality of input lines, a plurality of output lines, a buffer memory, and input cells received from each of the input lines are temporarily stored in a buffer memory while forming a queue corresponding to the output line. In an ATM switching apparatus having buffer control means for outputting to any output line determined by information, at least a processing mode and an upper message type are stored in correspondence with connection identification information included in each input cell. Means for detecting a cell loss occurring in the switching device; means for detecting a cell serving as a delimiter of the message in which the cell loss has occurred from subsequent input cells; Of the subsequent cells having the same connection identifier as the cell discarded by Means for performing cell discarding in accordance with the processing mode and the type of the upper message stored in the storage means, and a cell for notifying the receiving apparatus that the cell discarding has been performed. Means for generating and sending a packet.