JP2002170931A - High frequency semiconductor device - Google Patents
High frequency semiconductor deviceInfo
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- JP2002170931A JP2002170931A JP2000364220A JP2000364220A JP2002170931A JP 2002170931 A JP2002170931 A JP 2002170931A JP 2000364220 A JP2000364220 A JP 2000364220A JP 2000364220 A JP2000364220 A JP 2000364220A JP 2002170931 A JP2002170931 A JP 2002170931A
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- Prior art keywords
- semiconductor device
- frequency semiconductor
- frequency
- terminal
- mim capacitor
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- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はマイクロ波、ミリ波
周波数帯で用いられる高周波半導体チップと該高周波半
導体チップをパッケージに封止した高周波半導体装置及
び前記高周波半導体チップあるいは前記高周波半導体装
置を搭載したマザーボードを有する高周波通信機に関す
るものである。The present invention relates to a high-frequency semiconductor chip used in microwave and millimeter-wave frequency bands, a high-frequency semiconductor device in which the high-frequency semiconductor chip is sealed in a package, and the high-frequency semiconductor chip or the high-frequency semiconductor device mounted thereon. The present invention relates to a high-frequency communication device having a motherboard.
【０００２】[0002]
【従来の技術】高周波用の半導体デバイス（例えばHEMT
やMODFETを含む広義のGaAs MESFET、GaAs HBT、SiGe
HBTなど）は、高周波で動作させるため微細加工が必
要となり静電気破壊に弱いという問題があった。従来、
静電気破壊から半導体デバイスを保護する手段として
は、図５に示すような保護ダイオードを保護すべき端子
と接地間に挿入し、静電気電流を接地に逃がすという方
法が多く用いられてきた。例えば特公平6-69101号公
報、特公平7-40571号公報、特公平6-26243号公報、特公
平7-19782号公報などに記載されている通りである。し
かし、マイクロ波、ミリ波などの高周波領域では保護ダ
イオードの寄生容量、寄生抵抗及び非線形性により信号
の損失、歪みの発生が生じ、高周波特性が劣化するとい
う問題があった。一方、高周波特性を重視した保護ダイ
オードを用いない高周波半導体チップでは、静電気破壊
を生じさせないため特殊な組立ラインが必要となり、パ
ッケージ組立やベアチップ実装が困難であるという課題
があった。2. Description of the Related Art High frequency semiconductor devices (eg, HEMTs)
GaAs MESFET, GaAs HBT, SiGe
HBT, etc.) has a problem in that it requires fine processing to operate at a high frequency and is susceptible to electrostatic breakdown. Conventionally,
As a means for protecting a semiconductor device from electrostatic breakdown, a method of inserting a protection diode as shown in FIG. 5 between a terminal to be protected and ground to release an electrostatic current to ground has been used in many cases. For example, as described in Japanese Patent Publication No. 6-69101, Japanese Patent Publication No. 7-40571, Japanese Patent Publication No. 6-26243, and Japanese Patent Publication No. 7-19782. However, in a high frequency region such as a microwave and a millimeter wave, signal loss and distortion occur due to the parasitic capacitance, parasitic resistance, and non-linearity of the protection diode, and there is a problem that high frequency characteristics are deteriorated. On the other hand, a high-frequency semiconductor chip that does not use a protection diode that emphasizes high-frequency characteristics requires a special assembly line in order to prevent electrostatic breakdown, and has a problem that package assembly and bare chip mounting are difficult.
【０００３】[0003]
【発明が解決しようとする課題】本発明の課題は、ダイ
オードを用いずに半導体チップの静電気破壊耐性を改善
する手段を提案し、半導体デバイスの高周波特性を劣化
させることなく、高周波半導体チップを実現し、特殊な
組立ラインを必要としない高周波性能の良好な高周波半
導体装置及び高周波通信機を実現することである。SUMMARY OF THE INVENTION An object of the present invention is to propose a means for improving the electrostatic breakdown resistance of a semiconductor chip without using a diode, and to realize a high-frequency semiconductor chip without deteriorating the high-frequency characteristics of a semiconductor device. It is another object of the present invention to realize a high-frequency semiconductor device and a high-frequency communication device having good high-frequency performance without requiring a special assembly line.
【０００４】[0004]
【課題を解決するための手段】静電気破壊モデルの静電
気波形を検討したところ、キロヘルツ程度までの低周波
成分の瞬間的エネルギーが大きく、ギガヘルツ以上の成
分は小さいことが確認できている。このため、高周波用
の半導体デバイスを静電気破壊から保護する手段として
は低周波をカットする、あるいは低周波成分の通過時定
数を長くすることにより瞬間的発熱量を低減することが
有益であり、高周波用の半導体デバイスの保護すべき端
子に直列に非線形性を持たないＭＩＭキャパシタを挿入
することあるいは高周波用の半導体デバイスの保護すべ
き端子に並列に接地に対してスパイラルインダクタを挿
入することが有用である。なお、ＭＩＭキャパシタと
は、容量絶縁膜が２枚の平板電極で挟まれた構成のコン
デンサを指すものとする。When the electrostatic waveform of the electrostatic breakdown model is examined, it has been confirmed that the instantaneous energy of the low frequency component up to about kilohertz is large, and the component above gigahertz is small. For this reason, as a means for protecting the high-frequency semiconductor device from electrostatic breakdown, it is useful to cut the low frequency or to reduce the instantaneous heat generation by increasing the passing time constant of the low-frequency component. It is useful to insert a non-linear non-linear MIM capacitor in series with the terminal of the semiconductor device for protection or a spiral inductor with respect to the ground in parallel with the terminal of the high frequency semiconductor device to be protected. is there. Note that an MIM capacitor refers to a capacitor having a configuration in which a capacitance insulating film is sandwiched between two plate electrodes.
【０００５】本発明では、ＭＩＭキャパシタを複数個直
列にすることを以下の理由から提案するものである。 １．ＭＩＭキャパシタの層間絶縁膜の組成、厚さによっ
てＭＩＭキャパシタ自体が静電気破壊されてしまう場合
があるため、直列に複数個接続することにより、ＭＩＭ
キャパシタ１個あたりの電圧を分割し、ＭＩＭキャパシ
タ自体の破壊を防止する。 ２．ＭＩＭキャパシタの直列挿入損失はスパイラルイン
ダクタの並列挿入損失及びダイオードの並列挿入損失に
比較して十分小さいため、特性劣化が最小限に抑えられ
る。 ３．ＭＩＭキャパシタを複数個直列に接続することによ
り、小さな容量値を大きなパターンで実現できるため、
精度の高いキャパシタが実現できる。The present invention proposes that a plurality of MIM capacitors be connected in series for the following reasons. 1. Depending on the composition and thickness of the interlayer insulating film of the MIM capacitor, the MIM capacitor itself may be damaged by static electricity.
The voltage per capacitor is divided to prevent destruction of the MIM capacitor itself. 2. Since the series insertion loss of the MIM capacitor is sufficiently smaller than the parallel insertion loss of the spiral inductor and the parallel insertion loss of the diode, the characteristic deterioration is minimized. 3. By connecting a plurality of MIM capacitors in series, a small capacitance value can be realized in a large pattern.
A highly accurate capacitor can be realized.
【０００６】高周波用の半導体デバイスの保護すべき端
子に直列に非線形性を持たないＭＩＭキャパシタを複数
個挿入することにより、特性劣化を生じずにチップの静
電気破壊耐性が改善されるため、特殊な組立ラインを構
築することなくパッケージ組立やベアチップ実装が可能
になり、特性良好な高周波通信機を実現することができ
る。[0006] By inserting a plurality of MIM capacitors having no non-linearity in series with the terminals to be protected of a high-frequency semiconductor device, the chip can be improved in electrostatic breakdown resistance without deterioration of characteristics. Package assembly and bare chip mounting can be performed without constructing an assembly line, and a high-frequency communication device with good characteristics can be realized.
【０００７】[0007]
【発明の実施の形態】次に、本発明の実施の形態におけ
る高周波半導体装置について図面を用いて説明する。Next, a high-frequency semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
【０００８】（実施の形態１）まず、図１及び図２を用
いて本発明の実施の形態１における高周波半導体装置に
ついて説明する。(First Embodiment) First, a high-frequency semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.
【０００９】図１（ａ）は本発明の実施の形態１におけ
る高周波半導体装置の回路図であり、１はGaAs MODFET
で保護すべき半導体素子であり、２及び３は静電気破壊
保護用に挿入された直列接続されたそれぞれ１０ｐＦの
ＭＩＭキャパシタ、４は２ｋΩのゲートバイアス抵抗、
５は信号入力端子であり外部接続端子（パッド）に相当
し、６は１のゲート端子であり保護すべき端子であり、
７は信号出力端子であり１のドレイン端子（他の外部接
続端子）である。実施の形態１における高周波半導体装
置におけるこれらの構成は、全て基板（図示せず）上に
形成されている。FIG. 1A is a circuit diagram of a high-frequency semiconductor device according to a first embodiment of the present invention, where 1 is a GaAs MODFET.
2 and 3 are series-connected 10 pF MIM capacitors inserted for electrostatic discharge protection, 4 is a 2 kΩ gate bias resistor,
Reference numeral 5 denotes a signal input terminal, which corresponds to an external connection terminal (pad), 6 denotes a gate terminal, which is a terminal to be protected,
Reference numeral 7 denotes a signal output terminal, which is a drain terminal (another external connection terminal). These components in the high-frequency semiconductor device according to the first embodiment are all formed on a substrate (not shown).
【００１０】図１（ｂ）は比較用の高周波半導体装置
（チップ）の回路図であり、図１（ａ）から２及び３の
キャパシタが除かれたものである。FIG. 1B is a circuit diagram of a high-frequency semiconductor device (chip) for comparison, in which the capacitors 2 and 3 are removed from FIG. 1A.
【００１１】図１（ｂ）の静電気破壊耐性を端子６と接
地間について静電気破壊モデル（マシンモデル）を用い
て測定した場合１８Ｖであったが図１（ａ）の場合の５
と接地間の静電気破壊耐性は４０Ｖであり、本発明によ
り静電気破壊耐性が改善されていることが分かる。When the electrostatic breakdown resistance of FIG. 1B is measured by using an electrostatic breakdown model (machine model) between the terminal 6 and the ground, it is 18 V.
The electrostatic breakdown resistance between the ground and the ground is 40 V, which indicates that the electrostatic breakdown resistance is improved by the present invention.
【００１２】これは、２及び３のＭＩＭキャパシタの容
量成分により、静電気の低周波成分に大きな時定数が生
じ端子６に印加される時間が長くなるため、結果的に瞬
間的発熱量が低減され静電気破壊耐性が改善されたもの
である。This is because, due to the capacitance components of the 2 and 3 MIM capacitors, a large time constant occurs in the low-frequency component of static electricity and the time applied to the terminal 6 becomes longer, and as a result, the instantaneous heat generation is reduced. The electrostatic breakdown resistance is improved.
【００１３】図２（ａ）は図１（ａ）における直列接続
されたキャパシタ２及び３の平面図であり、図２（ｂ）
は図２（ａ）のＡ−Ａ’での断面図である。FIG. 2A is a plan view of the series-connected capacitors 2 and 3 in FIG. 1A, and FIG.
FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.
【００１４】１１はＭＩＭキャパシタの下層金属で厚さ
２００ｎｍのＰｔ膜で２及び３の接続を兼ねており、１
２及び１３はそれぞれＭＩＭキャパシタ２及び３の層間
絶縁膜であり厚さ３００ｎｍのＳｒＴｉＯ3膜であり、
１４及び１５はそれぞれＭＩＭキャパシタ２及び３の上
層金属であり厚さ７００ｎｍのＡｕ／Ｔｉ膜である。Reference numeral 11 denotes a lower metal layer of a MIM capacitor, which is a Pt film having a thickness of 200 nm, and serves as a connection between 2 and 3.
Reference numerals 2 and 13 denote SrTiO 3 films having a thickness of 300 nm, which are interlayer insulating films of the MIM capacitors 2 and 3, respectively.
Numerals 14 and 15 are upper metal layers of the MIM capacitors 2 and 3, each of which is an Au / Ti film having a thickness of 700 nm.
【００１５】１２あるいは１３は単独の場合３０Ｖの静
電気破壊耐性であるが、直列に接続することにより４０
Ｖまで改善されている事が分かる。Although 12 or 13 has a resistance to electrostatic breakdown of 30 V when used alone, 40 or 40
It can be seen that it has been improved to V.
【００１６】図１（ａ）と図１（ｂ）での高周波特性の
違いは、５ＧＨｚにおけるＮＦが図１（ａ）で０．８ｄ
Ｂであるのに対し図１（ｂ）では０．９ｄＢでありほと
んど劣化が生じていないことが確認できる。The difference between the high-frequency characteristics shown in FIGS. 1A and 1B is that the NF at 5 GHz is 0.8 d in FIG. 1A.
In FIG. 1B, B is 0.9 dB, which means that almost no deterioration has occurred.
【００１７】なお、本実施の形態では、保護すべき素子
としてGaAs MODFETを使ったが、GaAs HEMTを含む広義の
MESFETであっても、Si MOSFETであっても、同様の効果
が得られる。また、ＭＩＭキャパシタの層間絶縁膜をＳ
ｒＴｉＯ3として説明したが、ＢａＳｒＴｉＯ3等の強誘
電体材料、一般的な酸化シリコン、窒化シリコンでも同
様の効果を得ることができる。In this embodiment, the GaAs MODFET is used as an element to be protected.
The same effect can be obtained regardless of whether it is a MESFET or a Si MOSFET. Further, the interlayer insulating film of the MIM capacitor is made of S
Although described as rTiO 3 , a similar effect can be obtained with a ferroelectric material such as BaSrTiO 3 or general silicon oxide or silicon nitride.
【００１８】また、本実施の形態では、同じ容量値のＭ
ＩＭキャパシタを２個直列に接続した例について説明し
たが、それぞれ異なる容量値で有っても、また、３つ以
上のＭＩＭキャパシタを直列に接続しても同様の効果を
得ることができる。Further, in the present embodiment, M
Although an example in which two IM capacitors are connected in series has been described, the same effect can be obtained even if they have different capacitance values, or if three or more MIM capacitors are connected in series.
【００１９】（実施の形態２）次に、本発明の実施の形
態２における高周波半導体装置について図３を用いて説
明する。(Embodiment 2) Next, a high-frequency semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG.
【００２０】図３は、実施の形態２における高周波半導
体装置の回路図であり、１はGaAs MODFETで保護すべき
素子であり、２及び３は静電気破壊保護用に挿入された
直列接続されたそれぞれ１０ｐＦのキャパシタ、５は信
号入力端子であり外部接続パッドに相当し、６は１のゲ
ート端子であり保護すべき端子であり、７は信号出力端
子であり１のドレイン端子で外部接続端子であり、８は
２ｋΩのゲートバイアス抵抗である。なお、図１（ａ）
と同じ番号のものは同じ素子、端子を示している。FIG. 3 is a circuit diagram of a high-frequency semiconductor device according to the second embodiment. Reference numeral 1 denotes an element to be protected by a GaAs MODFET, and reference numerals 2 and 3 each connect in series for protection against electrostatic breakdown. 10 pF capacitor, 5 is a signal input terminal and corresponds to an external connection pad, 6 is a gate terminal and a terminal to be protected, 7 is a signal output terminal, 1 drain terminal and an external connection terminal , 8 are 2 kΩ gate bias resistors. FIG. 1 (a)
The same numbers indicate the same elements and terminals.
【００２１】実施の形態１では、１のＭＯＤＦＥＴのゲ
ートバイアス電圧は接地電位に固定されてしまうため、
チップ外部からゲートバイアス電圧を変更することが不
可能であった。In the first embodiment, the gate bias voltage of one MODFET is fixed to the ground potential.
It was impossible to change the gate bias voltage from outside the chip.
【００２２】本実施の形態では、ＭＩＭキャパシタ２、
３と並列にゲートバイアス抵抗８を挿入しているため入
力端子５からゲートバイアス電圧を設定することが可能
となる。In the present embodiment, the MIM capacitor 2,
Since the gate bias resistor 8 is inserted in parallel with 3, the gate bias voltage can be set from the input terminal 5.
【００２３】（実施の形態３）次に図４を用いて本発明
の実施の形態３における高周波半導体装置について説明
する。Third Embodiment Next, a high-frequency semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
【００２４】図４は本発明の実施の形態３における高周
波半導体装置の回路図であり、２１はGaAs HBTで保護す
べき素子であり、２２及び２３は静電気破壊保護用に挿
入された直列接続されたそれぞれ１０ｐＦのキャパシ
タ、２４は２１のベースにベース電流を供給するベース
バイアス回路、２５は信号入力端子であり外部接続パッ
ドに相当し、２６は２１のベース端子であり保護すべき
端子であり、２７は信号出力端子であり２１のコレクタ
端子で外部接続端子である。FIG. 4 is a circuit diagram of a high-frequency semiconductor device according to the third embodiment of the present invention. Reference numeral 21 denotes an element to be protected by GaAs HBT, and reference numerals 22 and 23 are connected in series and inserted for protection against electrostatic breakdown. Each has a 10 pF capacitor, 24 is a base bias circuit for supplying a base current to 21 bases, 25 is a signal input terminal and corresponds to an external connection pad, 26 is a 21 base terminal and a terminal to be protected, Reference numeral 27 denotes a signal output terminal, and a collector terminal 21 is an external connection terminal.
【００２５】本実施の形態においても実施の形態１で述
べたように静電気破壊耐性の改善効果が得られる。In this embodiment, as described in the first embodiment, the effect of improving the resistance to electrostatic breakdown can be obtained.
【００２６】なお、本実施の形態では、GaAs HBTを用い
たが、SiGe HBTやSi バイポーラトランジスタでも同様
な効果が得られる。Although the GaAs HBT is used in this embodiment, the same effect can be obtained with a SiGe HBT or a Si bipolar transistor.
【００２７】実施の形態１ないし３による高周波チップ
を用いることにより、例えばマシンモデルにおけるクラ
ス０（２５Ｖ以下）のラインでしか組み立てられなかっ
たチップがクラス１（２５〜１００Ｖ）のラインで組み
立てられるようになるため、容易に組み立てができるよ
うになり、高周波性能の良好な高周波半導体装置、高周
波通信機を実現することが可能となる。なお、高周波半
導体装置には、高周波半導体チップがプラスチックパッ
ケージやセラミックパッケージに封止され母基板である
プリント基板あるいはセラミック基板上に実装されてい
るもの又はベアチップ状態で母基板に実装されているも
の、及びプリント基板あるいはセラミック基板上に高周
波半導体チップとチップ部品が実装されている、いわゆ
るモジュール型の高周波半導体装置を含む。By using the high-frequency chip according to the first to third embodiments, for example, a chip that can be assembled only on a class 0 (25 V or less) line in a machine model can be assembled on a class 1 (25 to 100 V) line. Therefore, it is possible to easily assemble and realize a high-frequency semiconductor device and a high-frequency communication device having good high-frequency performance. The high-frequency semiconductor device includes a high-frequency semiconductor chip sealed in a plastic package or a ceramic package and mounted on a printed circuit board or a ceramic substrate, which is a mother substrate, or mounted on the mother substrate in a bare chip state. And a so-called modular high-frequency semiconductor device in which a high-frequency semiconductor chip and a chip component are mounted on a printed board or a ceramic substrate.
【００２８】[0028]
【発明の効果】本発明によれば、高周波性能を劣化させ
ることなく静電気破壊耐性を改善することができる。ま
た、静電気破壊耐性を改善することによって、パッケー
ジや通信機のマザーボードに容易に組み立てができるよ
うになり高周波性能の良好な半導体装置や高周波通信機
を実現することができる。According to the present invention, electrostatic breakdown resistance can be improved without deteriorating high frequency performance. Further, by improving the electrostatic breakdown resistance, the semiconductor device and the high-frequency communication device having good high-frequency performance can be easily assembled on a package or a motherboard of the communication device.
【図１】（ａ）本発明の実施の形態１における高周波半
導体装置の回路図 （ｂ）比較用の高周波半導体装置の回路図FIG. 1A is a circuit diagram of a high-frequency semiconductor device according to a first embodiment of the present invention. FIG. 1B is a circuit diagram of a high-frequency semiconductor device for comparison.
【図２】（ａ）本発明の実施の形態１における高周波半
導体装置のキャパシタの平面図 （ｂ）同キャパシタの断面図2A is a plan view of a capacitor of the high-frequency semiconductor device according to the first embodiment of the present invention; FIG.
【図３】本発明の実施の形態２における高周波半導体装
置の回路図FIG. 3 is a circuit diagram of a high-frequency semiconductor device according to a second embodiment of the present invention.
【図４】本発明の実施の形態３における高周波半導体装
置の回路図FIG. 4 is a circuit diagram of a high-frequency semiconductor device according to a third embodiment of the present invention.
【図５】保護ダイオードを用いた従来の高周波半導体装
置の回路図FIG. 5 is a circuit diagram of a conventional high-frequency semiconductor device using a protection diode.
１ ＭＯＤＦＥＴ ２、３ ＭＩＭキャパシタ ４ ゲートバイアス抵抗 ５ 信号入力端子 ６ ゲート端子 ７ 信号出力端子 ８ ゲートバイアス抵抗 １１ 下層金属 １２、１３ 層間絶縁膜 １４、１５ 上層金属 ２１ ＨＢＴ ２２、２３ キャパシタ ２４ ベースバイアス回路 ２５ 信号入力端子 ２６ ベース端子 ２７ 信号出力端子 DESCRIPTION OF SYMBOLS 1 MODFET 2, 3 MIM capacitor 4 Gate bias resistance 5 Signal input terminal 6 Gate terminal 7 Signal output terminal 8 Gate bias resistance 11 Lower layer metal 12, 13 Interlayer insulating film 14, 15 Upper layer metal 21 HBT 22, 23 Capacitor 24 Base bias circuit 25 signal input terminal 26 base terminal 27 signal output terminal
Claims (9)
続端子と、前記外部接続端子に接続された半導体素子
と、前記半導体素子と前記外部接続端子との間に直列に
接続された複数のキャパシタとを有することを特徴とす
る高周波半導体装置。1. A substrate, an external connection terminal formed on the substrate, a semiconductor element connected to the external connection terminal, and a plurality of semiconductor elements connected in series between the semiconductor element and the external connection terminal. A high-frequency semiconductor device comprising:
ることを特徴とする請求項１に記載の高周波半導体装
置。2. The high-frequency semiconductor device according to claim 1, wherein said capacitor is an MIM capacitor.
列に抵抗が接続されていることを特徴とする請求項２記
載の高周波半導体装置。3. The high-frequency semiconductor device according to claim 2, wherein a resistor is connected in parallel to said plurality of MIM capacitors.
効果トランジスタであり、前記電界効果トランジスタの
ゲートが前記ＭＩＭキャパシタに接続されていることを
特徴とする請求項２または請求項３に記載の高周波半導
体装置。4. The semiconductor device according to claim 2, wherein the semiconductor element is a field-effect transistor made of GaAs, and a gate of the field-effect transistor is connected to the MIM capacitor. High frequency semiconductor device.
ポーラトランジスタであり、前記バイポーラトランジス
タのベースが前記ＭＩＭキャパシタに接続されているこ
とを特徴とする請求項２または請求項３に記載の高周波
半導体装置。5. The high-frequency semiconductor according to claim 2, wherein the semiconductor element is a bipolar transistor made of GaAs, and a base of the bipolar transistor is connected to the MIM capacitor. apparatus.
ポーラトランジスタであり、前記バイポーラトランジス
タのベースが前記ＭＩＭキャパシタに接続されているこ
とを特徴とする請求項２または請求項３に記載の高周波
半導体装置。6. The high-frequency semiconductor according to claim 2, wherein the semiconductor element is a bipolar transistor made of SiGe, and a base of the bipolar transistor is connected to the MIM capacitor. apparatus.
ことを特徴とする請求項１ないし請求項６のいずれかに
記載の高周波半導体装置。7. The high-frequency semiconductor device according to claim 1, wherein said substrate is sealed in a package.
載の高周波半導体装置が母基板にベアチップ実装されて
いることを特徴とする高周波半導体装置。8. A high-frequency semiconductor device according to claim 1, wherein the high-frequency semiconductor device according to claim 1 is mounted on a mother board with a bare chip.
ンチウムで構成された容量絶縁膜を有することを特徴と
する請求項１ないし請求項８のいずれかに記載の高周波
半導体装置。9. The high-frequency semiconductor device according to claim 1, wherein said MIM capacitor has a capacitive insulating film made of strontium titanate.
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|---|---|---|---|
| JP2000364220A JP3496639B2 (en) | 2000-11-30 | 2000-11-30 | High frequency semiconductor device |
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| Publication Number | Publication Date |
|---|---|
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| JP3496639B2 JP3496639B2 (en) | 2004-02-16 |
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| Country | Link |
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