JP2002167298A - Single crystal wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LT wafer whose mechanical strength is improved in cracking and chipping and a yield during a mechanical process and a device process is enhanced, and its edging method. SOLUTION: A side 1c of an wafer 1 consisting of a lithium tantalate single crystal is so edged that its cleavage face of >=20% is contained, especially arithmetic mean-surface roughness (Ra) is <=1 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a single crystal wafer made of a lithium tantalate single crystal.

[0002]

2. Description of the Related Art Lithium tantalate single crystal (hereinafter referred to as LT)
Is widely used as a substrate material for electronic components and optical functional devices, and in recent years, has been particularly suitably used as a substrate for surface acoustic wave devices used in communication equipment and information equipment typified by mobile phones and the like. I have.

A wafer made of a single crystal of lithium tantalate is manufactured by a method substantially similar to the manufacturing process of a wafer made of a single crystal of silicon. In other words, after growing a crystal by the rotation pulling method, the outer diameter of the crystal is rounded, the wafer is cut so as to obtain the required crystal orientation, and the wafer is sequentially processed through rough polishing, chamfering, and mirror polishing. (For example, see Toshiba Review, Vol. 33, No. 9, pp. 761 to 763, published in 1978).

[0004] On the other hand, LT wafers have a strong demand for cost reduction due to the reduction in the cost of devices, and the development of a process that satisfies the demands has been required due to the improvement in manufacturing yield and the increase in diameter and thickness. Furthermore, the specifications required for wafers, such as eliminating the surface accuracy of the wafers required in the manufacturing process of devices that form microstructures and cracking during the manufacturing process, are becoming increasingly severe as opposed to larger diameters and cost reductions. ing.

[0005]

SUMMARY OF THE INVENTION As described above, LT
As the diameter and thickness of the wafer become larger and thinner, the frequency of cracking and chipping during wafer processing increases, so chamfering of the wafer end surface is effective in preventing such cracking and chipping. And LT wafers (for example, see JP-A-52-144269, JP-A-61-164269).
146799).

However, an LT wafer having a 33 ° to 46 ° rotational Y-cut orientation, which is a substrate of a surface acoustic wave filter, which is widely used in recent mobile phone terminals and the like, has low crystal symmetry, and is easily warped and cracked. There was a problem that chipping easily occurred. As a method to prevent cracking and chipping of the wafer, it is effective to remove edges by chamfering and relieve mechanical stress.However, such a shape and processing method that avoids a cracked surface is effective for cracking and chipping. And high effect was not obtained.

Accordingly, the present invention has been proposed in view of the above-mentioned problems, and has as its object to provide a single-crystal wafer excellent in mechanical strength which is less likely to cause cracks or chips in a wafer processing step or a device process. I do.

[0008]

In order to solve the above-mentioned problems, a single crystal wafer according to the present invention has a chamfered surface containing 20% or more of a cleavage surface on a side surface of a wafer made of a lithium tantalate single crystal. It is characterized by the following.

[0009] In particular, the arithmetic average roughness (Ra) of the chamfered surface is 1 μm or less. The main surface direction of the wafer can be calculated by the following equation: (1) −60 ° ≦ φ
≦ 60 °, (2) 123 ° ≦ θ ≦ 136 °, (3) ψ satisfies any condition. Further, an angle α formed between the chamfered surface and the main surface of the wafer is 45 ° ≦ α ≦ 51 °.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a lithium tantalate single crystal wafer suitably used as a piezoelectric substrate of a surface acoustic wave filter of a cellular phone and a chamfering method thereof will be described in detail with reference to the drawings schematically shown. explain.

In the single crystal wafer of the present invention, the parameters of the right-handed Euler angle display (φ, θ, ψ) shown in FIG. 1 are predetermined values (−60 ° to 60 °, 123 ° to 136 °, arbitrary (−1)).
80 ° -180 °)), a wafer made of a single crystal of lithium tantalate is prepared.
It has been chamfered as shown in (a) and (b).

In FIG. 2, at least one of the principal surfaces 1a and 1b is a surface on which a device is formed on the surface of the wafer 1. The device forming surface is mirror-polished by polishing, and the surface on which no device is formed is, for example, a surface average. Lapping is performed so that the roughness (arithmetic mean roughness (Ra)) is about 0.2 μm to 1 μm. The side surfaces 1c, 1d, and 1e are edge-processed by a chamfering device using, for example, a grindstone in which diamond or the like is dispersed in a metal or a resin, to remove an edge serving as a starting point of cracks and chips, and to reduce the occurrence rate as much as possible. ing.

In the chamfered side surface (chamfered surface), more than 20% of the area is the cleavage surface.
The right-handed Euler angle display (φ, θ, ψ) means X-
An axis obtained by rotating the X-axis by an angle φ in the Y-axis direction about the Z-axis in the Y-Z crystal axis as a θ-rotation axis, and further rotating the Z-plane by θ about the θ-rotation axis Is a cut plane, and the propagation direction of the surface acoustic wave on this cut plane is a direction rotated ψ counterclockwise from the θ rotation axis.

Here, it is not desirable that the side surface of the wafer does not have a cleavage surface because cracking and chipping of the wafer cannot be eliminated in a polishing step or a device process. In addition, -60 in Euler angle display (φ, θ, 、)
° ≦ φ ≦ 60 °, 123 ° ≦ θ ≦ 136 °, and ψ are arbitrary angles, which is effective on a wafer surface with low crystal symmetry where cracks and chips are likely to occur, and for surface acoustic wave devices. This is because it is useful as a substrate orientation.

The chamfered surface having a cleavage surface is chamfered with a grindstone or the like in which diamond or the like is dispersed in metal or resin, and has an arithmetic average roughness (Ra) of 1.5 μm.
The following are desirable in terms of improving mechanical strength against stress,
The upper limit is 1 μm or less. The reason is that when Ra is larger than 1 μm, it is difficult to form a cleavage plane,
This is because roughness exceeding μm serves as a starting point of a defect, and chipping easily occurs.

In FIG. 2B, the angle α between the chamfered surface (side surface 1c) having the cleavage surface and the wafer main surface 1a is set to 45 ° ≦ α ≦ 51 ° for the reason described later.

Next, a method for manufacturing a single crystal wafer of the present invention will be described. For example, Euler angle display (−60 ° to
A seed crystal cut in a direction substantially perpendicular to 60 °, 123 ° to 136 °, 種 = arbitrary angle) is filled in a crucible made of a high melting point metal such as iridium, and L melted at a melting point or higher.
A single crystal having an outer diameter of about 110 mm is grown by a rotation pulling method (Czochralski method) in which the seed crystal is brought into contact with the raw material melt of T and the temperature is lowered and the seed crystal is rotated and pulled.

The head and the bottom of the grown single crystal are expressed in Euler angles (−60 ° to 60 °, 123 ° to 136) using, for example, an inner peripheral diamond cutting machine and an X-ray diffractometer.
°, ψ) Cut so that the surface becomes the main surface.

Next, silver paste is applied to the upper and lower portions of the crystal to form electrodes, and the electrode is heated at a Curie temperature or higher (for example, 650 ° C.).
A poling process is performed by applying a voltage of 1.5 to 5 V / cm between the electrodes for about 5 hours.

Next, the crystal ingot after the poling treatment is set in a cylindrical grinding device, and is subjected to cylindrical grinding so as to have an outer diameter of 101 mm, and further, is subjected to grinding to form an orientation flat.

After cylindrical processing in this manner, the crystal ingot is placed in a 0.5 m
Cut to a thickness of about m
Lapping both sides using No. GC abrasive grains.

Next, the wafer after lap polishing is set in an automatic chamfering device and chamfering is performed. At this time, the angle α between the main surface 1a of the wafer and the chamfered surface 1c of the side as shown in FIG. 2 is made to coincide with one of the cleavage surfaces. Here, the side surface 1d is a line segment or an arc that is substantially perpendicular to the main surface 1a in cross section, and the angle formed by the upper side surface 1b and the lower side surface 1e is 90 ° -α ° which is one cleavage surface.

The chamfered surface is shown by S in FIGS. 3 (a) and 3 (b).
As confirmed by the electron microscope image by EM, the shape composed preferentially of the cleavage surface (the shape including many flat surfaces of the grinding surface in the unevenness of the ground surface: within the circle in FIG. 3B) Make. FIG. 3A shows that the cleavage planes are widely distributed in a 1000 × electron microscope image, and FIG. 3B is an enlarged view of the cleavage planes in a 3000 × electron microscope image. It was done. Note that the chamfered grinding portion is not limited to a flat shape (a cross section is a straight line), but may be a curved surface (a cross section is an arc shape). The chamfered wafer is
The main surface is mirror-polished by mechanochemical polishing using a colloidal silica abrasive to produce a wafer.

[0024]

[Table 1]

As shown in Table 1, the LT wafer manufactured in such a process is, for example, (0 °, 132 °, ψ
= Optional) when the chamfering process was performed at α = 47.7 ° (the present invention), when no chamfering process was performed (comparative example), and when α was chamfered at approximately 30 °. Regarding (Comparative Example), the polishing yield (the ratio of the number that could be polished without cracking to the number of inputs n), the cracking yield during the device process (the ratio of the number that could be device processed without cracking to the number of inputs n), and As a result of comparing the thermal shock threshold of cracks (the average value of the temperature difference at which cracks occurred when a wafer heated in an oven was put into water at 23 °), the effect of the present invention was clear.

The decrease in the polishing yield in the chamfering process according to the comparative example is caused by cracking from the wafer edge, and is caused by mechanical stress due to pressure polishing and polishing resistance. Cracking in the device process is caused by thermal stress in the heating and cooling process in the process. Therefore, it is considered that the improvement of the yield according to the present invention has improved the resistance to mechanical and thermal stress. The reason is that the crystal is easily cracked in parallel with the cleavage plane, but once the cleavage plane is formed, it is considered that the plane has a high atomic density, so that the plane is unlikely to crack. Also, when the LT is ground on a surface close to the cleavage surface, the processed surface is likely to be composed of the cleavage surface, and ± 1.5% from the cleavage surface.
It is found that the cleavage surface is likely to appear in the machining within °, so that, for example, even when grinding is performed at 50 ° which is close to the cleavage surface of 47.7 °, the cleavage surface appears preferentially. For example, in the case of a wafer having a (0 °, 132 °, ψ = arbitrary) plane, the cleavage plane of the {012} plane is 47.7 ° and α is 9.0 °, 75.0 °, 87.0. ° is present, and in the case of a chamfer having an arc-shaped cross-section, each of the chamfers corresponding to the tangent of the arc appears.
Is more effective if it is formed in an arcuate cross section.

In addition, in the case of an LT (-3 to 3 °, 123 ° to 136 °, ψ = arbitrary) cut wafer having particularly good characteristics as a surface acoustic wave element, a cleavage surface appears as shown in FIG. The chamfering angle α was found to be 45 ° ≦ α ≦ 51 °. In the figure, L1 is α = 0.075θ ² −
2.2θ + 202.3, L2 is α = 0.075θ ² −
2.2θ + 199.3, and L1 and L
The area indicated by oblique lines in the range surrounded by 2 is 45 ° ≦ α ≦ 5
The range is 1 °.

Further, as shown in FIG. 5, when the cut surface in the chamfered portion is 20% or more, the effects of yield and thermal shock in Table 1 are remarkable, and the average surface roughness (arithmetic mean) in that case is obtained. The roughness (Ra) is 0.25 to 1.
It was found to be 0 μm. The ratio of the area of the cleavage plane is a value measured from an electron microscope image.

Further, a right-handed Euler angle display (φ, θ,
It was found that when the parameter φ in ±) was in the range of ± 3 °, similar effects could be obtained from high mechanical strength and device characteristics. Then, with respect to the wafer cutting direction and the chamfer angle, it was possible to improve a wafer which had conventionally had a problem in mechanical strength.

From the above results, it is possible to improve the durability against the physical stress by performing the chamfering process having the cleavage surface on the end surface serving as the starting point of cracking and chipping of the wafer. This makes it possible to reduce the wafer cost by improving the yield during wafer processing,
The generation of cracks and chips during the device process (film formation, etching, dicing, package packing) can be reduced, and the generation of foreign particles due to chips in the fine process can be suppressed, so that the device yield has been significantly improved. Thereby, the manufacturing cost of the surface acoustic wave device can be reduced.

[0031]

EXAMPLES Next, more specific examples of the present invention will be described. [Example 1] In the right-handed Euler angle display (0 °, 132 °,
ii) A method for manufacturing a wafer will be described. 10m from the LT single crystal in the direction perpendicular to the (0 °, 132 °, ψ) cut
A seed crystal having a length of 50 mm and a length of m square was cut out, the LT raw material was melted in an iridium crucible heated by high-frequency induction heating, and the seed crystal was brought into contact therewith.

Then, while rotating the output of the high frequency induction to lower the temperature of the raw material melt, the rotating seed crystal was pulled up to grow an LT single crystal having an outer diameter of 110 mm. The head and bottom of the grown crystal are positioned and cut at the (0 °, 132 °, ψ) plane using an inner peripheral diamond cutting machine and an X-ray diffractometer, and silver paste is applied to the upper and lower parts of the crystal. Then, a poling treatment was performed by applying a voltage of 1.5 to 5 V / cm between the electrodes at 650 ° C. above the Curie temperature for 5 hours.

The crystal ingot after poling was ground using a cylindrical grinding device (RS-h40NAH manufactured by Ueda Giken Co., Ltd.) to a cylinder having an outer diameter of 101 mm and an orientation flat on the X plane. The crystal ingot after cylindrical processing is cut to 0.5 mm thickness with a multi-wire saw, and 0.4 mm
Both sides were lapped and polished using # 1000 GC abrasives.

The wafer after the lap polishing process has an outer diameter of 100 mm using an automatic chamfering device, and the cross-section of the chamfering process is such that the chamfered surface 2 shown in FIG.
Chamfering was performed at 7 °.

The chamfering grindstone used was, for example, a metal bond of # 600. At this time, chamfering processing 1c or 1e
In FIG. 3, a cleavage plane preferentially appeared as in the electron microscope image shown in FIG. The chamfered wafer was mirror-polished by mechanochemical polishing on the main surface to produce a wafer.

In order to confirm the effect of the present invention, as shown in Table 1, the following steps were performed for the case where the chamfered surface α was machined at 47.7 °, the case where the chamfered surface α was machined at 30 °, and the case where no chamfering was performed. The cracking yield during polishing was compared with the cracking yield during device processing, and the thermal shock threshold value of the crack when dropped in water at 23 ° C. after heating in an oven was compared.

As a result, the yield of the LT wafer having a chamfer having a cleavage surface described in the present invention was improved as compared with the LT wafer having a chamfer having no cleavage surface, and the effect was confirmed. This is probably due to the fact that the chamfered LT wafer of the present invention has improved physical strength. If the processed surface is within a range of ± 1.5 ° with respect to the cleavage surface, the same effect can be obtained because the cleavage surface does not necessarily coincide with the cleavage surface but appears even without grinding. Also, the chamfered shape is a difficult surface (0
12) Equivalent to the plane, for example, α is 9.0 °, 75.0 °,
It has also been found that a similar effect can be obtained if the shape shows a cleavage plane of 87.0 °.

Further, a right-handed Euler angle display (φ, θ,
It can be seen that high mechanical strength and good device characteristics can be obtained even when φ of ψ) is ± 3 °, and the wafer which has conventionally had a problem in mechanical strength in this wafer cut orientation and chamfer angle is improved. I was able to.

[0039]

According to the single crystal wafer of the present invention, durability against physical stress can be improved by performing chamfering on the side surface serving as a starting point of cracking and chipping of the wafer. Can be.

As a result, a highly reliable single crystal wafer can be supplied by improving the yield at the time of processing the wafer, and a surface acoustic wave device having excellent reliability and characteristics can be provided.

[Brief description of the drawings]

FIG. 1 is a coordinate diagram illustrating a right-handed Euler angle display.

FIG. 2 is a diagram schematically illustrating a chamfered shape of a wafer edge portion according to the present invention, where (a) is a partially cutaway perspective view,
(B) is an enlarged sectional view of (a).

FIGS. 3A and 3B are electron micrographs of a chamfered surface including a cleavage surface according to the present invention, wherein FIG.
An M image and (b) are SEM images at a magnification of 3000 times.

FIG. 4 is a graph (vertical axis α, horizontal axis θ) showing a relationship between a wafer surface (0 °, θ, ψ) and an optimum chamfer angle α.

FIG. 5 is a graph showing the relationship between the grinding wheel count on the chamfered processing surface including the cleavage surface, the ratio of the cleavage surface, and the average surface roughness.

[Explanation of symbols]

 1: Wafer 1a, 1b: Main surface 1c, 1d, 1e: Side surface

Claims (4)

[Claims] 1. A single crystal wafer having a chamfered surface containing 20% or more of a cleavage surface on a side surface of a wafer made of a lithium tantalate single crystal. 2. The arithmetic average roughness (R) of the chamfered surface.
2. The single crystal wafer according to claim 1, wherein a) is 1 μm or less. 3. The principal plane orientation of the wafer, wherein each parameter of a right-handed Euler angle display (φ, θ, ψ) satisfies the following conditions (1) to (3). The single crystal wafer according to the above. (1) -60 ° ≦ φ ≦ 60 ° (2) 123 ° ≦ θ ≦ 136 ° (3) ψ is optional 4. The single crystal wafer according to claim 3, wherein an angle α between the chamfered surface and a main surface of the wafer satisfies 45 ° ≦ α ≦ 51 °.