JP2002164534A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which secures zero-cross operation even when light illumination increases. SOLUTION: A triac has a pnpn 4-layered structure of a p-type anode area 2, an n-type semiconductor substrate 1, a p-type gate area 3, and an n-type cathode area 4 and a pnpn 4-layered structure of a p-type anode area 2; an n-type semiconductor substrate 1, a p-type gate area 3; and an n-type cathode area 4. The pnp transistors composed of the p-type anode areas 2 and 2', n-type semiconductor substrate 1, and p-type well areas 6 and 6', are made larger in base width than the pnp transistors composed of the p-type anode areas 2 and 2', n-type semiconductor substrate 1, and p-type gate areas 3 and 3' and then the current amplification factors of the latter pnp transistors are made larger than those of the former pnp transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a triac.

[0002]

2. Description of the Related Art A triac having a configuration as shown in FIG. 9 is conventionally known. The triac having the configuration shown in FIG. 9 has a p-p between main terminals MT1 and MT2 as shown in FIG.
An npn four-layer reverse blocking thyristor is integrated in an anti-parallel manner. Two p-type anode regions 2 and 2 ′ are formed on the main surface side of the n-type semiconductor substrate 1 at a distance from each other. N-type semiconductor substrate 1 spaced apart from each other
P-type gate regions 3 and 3 'are formed on the main surface side of
N-type cathode regions 4 and 4 'are formed on the main surface side in p-type gate regions 3 and 3', respectively, and p-type anode region 2 and n-type cathode region 4 'are connected to one main terminal MT1. , P-type anode region 2 ′ and n-type cathode region 4 are connected to the other main terminal MT2.

Therefore, considering the above-mentioned triac operation, when the main terminal MT1 is set at a higher potential than the main terminal MT2, the p-type anode region 2, the n-type semiconductor substrate 1, the p-type gate region 3, the n-type Pnp of cathode region 4
Considering the n4 layer structure, when the main terminal MT2 is set at a higher potential than the main terminal MT1, the p-type anode region layer 2 ', the n-type semiconductor substrate 1, the p-type gate region 3',
What is necessary is just to consider the pnpn four-layer structure of the n-type cathode region 4 '.

An equivalent circuit of a triac having the configuration shown in FIGS. 9 and 10 is represented as shown in FIG. That is, p
The equivalent circuit of the pnpn four-layer structure of the n-type anode region 2, the n-type semiconductor substrate 1, the p-type gate region 3, and the n-type cathode region 4 is represented by a pnp transistor T2 and an npn transistor T1 whose collector and base are connected to each other. The equivalent circuit of the pnpn four-layer structure of the p-type anode region 2 ', the n-type semiconductor substrate 1, the p-type gate region 3', and the n-type cathode region 4 'is a pnp transistor T2' having a collector and a base connected to each other. And an npn transistor T1 ′.

Here, an operation of shifting a thyristor having a pnpn four-layer structure as shown in FIG. 12 from a forward blocking state to a forward conducting state will be described.

An equivalent circuit of a pnpn four-layer structure shown in FIG.
Are connected between the collector and the base as shown in FIG.
Connected pnp transistor T2 "and npn transistor
T1 ", each transistor T2", T2 "
1 "common emitter DC current amplification factor (hereinafter referred to as current amplification
H)_{FE (pnp)}, H_{FE (npn)}Tomorrow
For example, the power of the reproduction feedback loop in the equivalent circuit shown in FIG.
The flow gain g is g = h_{FE (pnp)}× h_{FE (npn)} Is obtained. That is, the current gain g is equal to the pnp transistor
Current amplification factor h of the _{FE (pnp)}And npn transistor
T1 ″ current amplification factor h_{FE (npn)}And the product

In addition, the transistors T2 "and T1"
Current is_(pnp), I_{(np n)}And the collector power
Each flow is Ic_(pnp), Ic_(npn)Then Ic_(pnp)= H_{FE (pnp)}× (Ic_(npn)+ I_(pnp)) + I
_(pnp) Ic_(npn)= H_{FE (npn)}× (Ic_(pnp)+ I_(npn)) + I
_(npn) Becomes Therefore, the flow between the anode A and the cathode K
The total current I is: I = (1 + h_{FE (pnp)}) × (1 + h)_{FE (npn)}) × (I
_(pnp)+ I_(npn)) / (1-g). That is, the current gain g is sufficiently smaller than 1.
And the thyristor is off, and the current gain g approaches unity.
Then it turns on. In this thyristor
_{FE (pnp)}× h_{FE (npn)}Set the value of 1 close to 1 to make it fire
Irradiates light to the pnpn4 layer structure,
There is a method of flowing current.

In recent years, with the increase in the withstand voltage and the capacity of the triac, the dv / dt resistance (that is, the applied voltage between the anode and the cathode in the forward blocking state) while being highly sensitive to the input signal. Therefore, a structure that does not cause a malfunction due to noise or the like is desired.

However, in general, there is a contradictory relationship that when the dv / dt resistance is increased, the sensitivity to an input signal is reduced. That is, in the case where the resistor R is connected between the gate G and the cathode K of the three-terminal thyristor as shown in FIG. The higher the value, the easier the transition to the conductive state. However, when a steep rising voltage is applied such that the anode A has a high potential with respect to the cathode K in the absence of an input signal,
The larger the resistance value of the resistor R, the lower the dv / dt resistance, and the more likely it is for an erroneous ignition to occur. Conversely, as the resistance value of the resistor R decreases, the dv / dt resistance increases, but the sensitivity to the input signal decreases.

As an application example of a semiconductor device which solves this kind of problem, for example, a semiconductor relay 20 having an equivalent circuit as shown in FIG. 15 has been proposed (JP-B-61-23).
666). Semiconductor relay 20 shown in FIG.
Comprises a light emitting element 21 composed of a light emitting diode which is turned on / off by an input signal applied between the input terminals IT1 and IT2, and a triac 22 optically coupled to the light emitting element 21. The main terminals MT1 and MT2 of the triac 22 Each is used as an output terminal. Here, the two thyristors constituting the triac 22 have resistors RB, RB 'and insulated gate field effect transistors T3, T3' respectively connected between the gate and cathode, and the gates of the insulated gate field effect transistors T3, T3 ' Are the thyristor anodes (that is, the main terminals MT1 and M
T2).

In the semiconductor relay 20 having the configuration shown in FIG. 15, when the potential of the main terminal MT1 (or MT2) sharply increases in a state where there is no input signal between the input terminals IT1 and IT2, the main terminal MT1 (or MT1) increases. MT2) whose gate is connected to the insulated gate field effect transistor T
3 (or T3 ') becomes a potential equal to or higher than the threshold value of the insulated gate field effect transistor T3 (or T3'), the insulated gate field effect transistor T3 (or T3 ') is turned on, pnp
Since the impedance between the gate and the cathode of the thyristor including the transistor T2 (or T2 ') and the npn transistor T1 (or T1') is reduced, erroneous firing is prevented. Also, the main terminal M of the triac 22
When the potential of T1 (or MT2) is equal to or higher than the threshold value of the insulated gate field effect transistor T3 (or T3 '), the pnp transistor T2 (or T3)
2 ′) and the npn transistor T1 (or T1 ′), the impedance between the gate and cathode of the thyristor decreases, so that the pnp transistor T2 (or T2 ′) and the npn transistor T1 (or T1)
The thyristor composed of 1 ′) does not shift to the ON state even if there is an input signal. Conversely, when the potential of the main terminal MT1 is lower than the threshold value of the insulated gate field effect transistor T3, the insulated gate field effect transistor T3 does not turn on and the impedance between the gate and cathode of the triac decreases. Therefore, the thyristor including the pnp transistor T2 and the npn transistor T1 is turned on by an input signal. That is, the above-described triac 22 has a false ignition prevention structure, and can increase noise immunity while maintaining high light ignition sensitivity.

By the way, as shown in FIG. 16, a series circuit of a DC power supply E and a switching element S is connected between input terminals IT1 and IT2 of the semiconductor relay 20, and main terminals MT1 and MT2 are connected.
If a series circuit of the load L and the AC power supply (load power supply) Vs is connected between the MTs 2, the power supply path from the AC power supply Vs to the load L can be turned on / off using the triac 22. Less than,
The operation of the circuit shown in FIG. 16 will be briefly described with reference to the operation waveforms in FIG. 17A shows a voltage waveform of the AC power supply Vs, FIG. 17B shows a voltage waveform of an input signal applied between the input terminals IT1 and IT2 by turning on and off the switching element S, and FIG. 17C shows a main terminal. M
A voltage waveform between T1 and MT2 is shown, and (d) shows a current waveform of a load current flowing to the load L.

If an input signal is applied to the light emitting element 21 at time t1 as shown in FIG.
1 (or MT2) is larger than the threshold value of the insulated gate field effect transistor T3 (or T3 '), so that the main terminals MT1 and MT2 do not shift to the ON state, and the voltage between the main terminals MT1 and MT2 does not change. Becomes smaller than the threshold value of the insulated gate field effect transistor T3 (or T3 '), at time t2, the main terminals MT1 and MT2 are turned on. Thereafter, even if the application of the input signal to the light emitting element 21 is stopped at the time t3, the main terminal MT1
(Or MT2) is higher than the threshold value of the insulated gate field effect transistor T3 (or T3 '), so that the main terminals MT1 and MT2 are not turned off.
At time t4 when the voltage between the main terminals MT1 and MT2 becomes smaller than the threshold value of the insulated gate field effect transistor T3 (or T3 ′), the main terminals MT1 and MT2 are turned off.

That is, the above-described triac 22 has a function of performing an on / off operation near zero volts (hereinafter, referred to as a zero cross function).

The advantage of having such a zero-cross function is that the radiation noise generated from the semiconductor relay 20 when the semiconductor relay 20 is turned on is small, and the rush current flowing into the load L at the moment when the semiconductor relay 20 is turned on is reduced. And the like.

The triac 22 having the equivalent circuit shown in FIG. 15 has a structure as shown in FIGS. 18 to 20, and has an n-type semiconductor substrate 1, a p-type gate region 3, and an n-type semiconductor region.
An npn transistor T1 with the n-type cathode region 4, an npn transistor T1 'with the n-type semiconductor substrate 1, the p-type gate region 3' and the n-type cathode region 4 ',
The p-type anode region 2, the n-type semiconductor substrate 1, and the p-type gate region 3 constitute a pnp transistor T2, and the p-type anode region 2 ', the n-type semiconductor substrate 1, and the p-type gate region 3' constitute a pnp transistor. T2 '. Also,
Each of the resistors RB and RB ′ is constituted by each of the p-type regions 5 and 5 ′ formed on the main surface side of the n-type semiconductor substrate 1.
Further, the above-described insulated gate field effect transistors T3, T
Reference numeral 3 'denotes n-type drain regions 7, 7' and n-type source regions 8, 8 'formed in p-type well regions 6, 6' formed on the main surface side of n-type semiconductor substrate 1 with a space therebetween. , Gate electrodes 12 and 12 ′ are formed over the n-type drain regions 7 and 7 ′ and the n-type source regions 8 and 8 ′.

The above-mentioned regions 2 to 8, 2 'to 8' are formed on the main surface side of n-type semiconductor substrate 1, and an insulating film made of a silicon oxide film is formed on the main surface of n-type semiconductor substrate 1. The surface electrodes 10, 10 ', 11, and 11' are formed by appropriately providing contact holes in the insulating film 9. Here, the surface electrodes 10 and 10 'are respectively connected to the main terminals M
T1 and MT2 are formed, and the surface electrodes 11 and 11 'are each configured as a p-gate electrode.

The drain electrodes of the insulated gate field effect transistors T3 and T3 'are surface electrodes 11, 1
1 ′ (that is, common with the p gate electrode), and the source electrode is formed with the surface electrodes 10 ′ and 10 (that is, common with the main terminals MT2 and MT1).

[0019]

By the way, in the semiconductor device described in Japanese Patent Publication No. 23666/1986, when the triac 22 is caused to emit light from the main surface side, the light emitting element 21 If the light output of the light-emitting element 21 is increased by increasing the input current to the light-emitting element 21 to cause ignition with a relatively large light illuminance, the zero-cross operation becomes unstable (increase of the zero-cross voltage, non-zero-cross). Was.

When the triac 22 is switched to the ignition state by irradiating light from the main surface side of the n-type semiconductor substrate 1, for example, a case where the surface electrode 10 'has a higher potential than the surface electrode 10 will be described. When the input current to 21 is increased, the p-type anode region 2 ', the n-type semiconductor substrate 1, the p-type well region 6' of the insulated gate field effect transistor T3 ', and the n-type drain of the insulated gate field effect transistor T3' The light emitting element 21 emits light such that the illuminance of the parasitic thyristor including the region 7 ′ is higher than the illuminance at which the light is ignited.
Is output from the parasitic triac, a current is supplied to the gate of the triac due to light ignition of the triac, so that the zero-cross voltage increases or the main terminals MT1, MT1
The potential between the two is insulated gate field effect transistors T3, T
Even when the potential is equal to or higher than the threshold value of 3 ', there is a problem that a gate current is supplied to the main triac and the main triac shifts to an on state (non-zero crossing). The parasitic triac has a pnpn four-layer structure including a p-type anode region 2 ′, an n-type semiconductor substrate 1, a p-type well region 6 ′, and an n-type drain region 7 ′, and a p-type anode region 2, an n-type semiconductor substrate 1, p-type well region 6, n-type drain region 7
Pnpn four-layer structure.

Here, the rise of the zero-cross voltage will be described. To prevent the triac from shifting to the on state when the voltage between the main terminals MT1 and MT2 is equal to or higher than the zero cross voltage (that is, to ensure the zero cross function), the impedance (resistance) between the gate and cathode of the triac (Combined resistance value of RB, RB 'and ON resistance of insulated gate field effect transistors T3, T3')
Needs to be lower than the state in which the triac shifts to the ON state by itself, the on-resistance of the insulated gate field effect transistors T3 and T3 'must be reduced, and the gates of the insulated gate field effect transistors T3 and T3' Therefore, it is necessary to apply a higher voltage, and the zero-cross voltage increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of ensuring a zero-cross operation even when light illuminance increases.

[0023]

According to a first aspect of the present invention, there is provided a semiconductor device having a triac, two insulated gate field effect transistors, and two resistors on a semiconductor substrate. A drain region and a source region are formed in a well region formed on the main surface side of the semiconductor substrate, each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors constituting the triac; A semiconductor device in which the gate of the insulated gate field-effect transistor is connected to either the anode of the thyristor or the semiconductor substrate, and the ignition sensitivity of the triac is reduced by changing the anode region of the thyristor, the semiconductor substrate, and the well region. Parasitic tria comprising a drain region and the drain region It is characterized in that is larger than the ignition sensitivity of click, the ignition sensitivity of the triac is larger than the ignition sensitivity of the parasitic triac,
Even if the illuminance of the irradiated light is increased, the light emission of the parasitic triac can be prevented, so that the zero-cross operation does not become unstable and the zero-cross operation can be ensured.

According to a second aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a current amplification factor of a transistor including an anode region of the thyristor, a gate region of the semiconductor substrate and a gate region of the thyristor, and a gate region of the semiconductor substrate and the thyristor; The power of the thyristor The product of the current amplification factor of the transistor formed of the thyristor, the current amplification factor of the transistor formed of the anode region of the thyristor, the semiconductor substrate, and the well region, and the semiconductor substrate, the well region, and the drain region Wherein the product of the current amplification factor of the pnp transistor and the current amplification factor of the npn transistor forming the triac is a parasitic triac. Is larger than the product of the current amplification factor of the pnp transistor and the current amplification factor of the npn transistor, so that the ignition sensitivity of the triac is greater than the ignition sensitivity of the parasitic triac, and the illuminance by the emitted light increases. It is possible to prevent the light emission of the parasitic triac even if Ross operation does not become unstable, it is possible to ensure a zero-crossing operation.

According to a third aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a current amplification factor of a transistor including an anode region of the thyristor, a gate region of the semiconductor substrate, and a gate region of the thyristor; The well region and The current amplification factor of the pnp transistor constituting the triac may be higher than that of the pnp transistor if the conductivity type of the semiconductor substrate is n-type. Since the current amplification factor of the pnp transistor forming the triac is larger than the current amplification factor of the pnp transistor forming the triac, the product of the current amplification factor of the npn transistor and the pnp transistor forming the triac is calculated as pn which forms the parasitic triac.
It can be made larger than the product of the current amplification factor of the p transistor and the current amplification factor of the npn transistor, and the ignition sensitivity of the triac becomes greater than the ignition sensitivity of the parasitic triac, increasing the illuminance by the emitted light. Even if this is done, the light emission of the parasitic triac can be prevented, so that the zero-cross operation does not become unstable and the zero-cross operation can be ensured.

According to a fourth aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a base width of a transistor including the anode region of the thyristor, the semiconductor substrate, and the well region is set to an anode region of the thyristor, the semiconductor substrate, and the thyristor. The gate area For example, if the conductivity type of the semiconductor substrate is n-type, the base width of the pnp transistor constituting the parasitic triac constitutes the triac. Since the current amplification factor of the pnp transistor forming the triac is larger than the current amplification factor of the pnp transistor forming the parasitic triac, the current amplification factor of the pnp transistor forming the triac is increased. And the current amplification factor of the npn transistor can be made larger than the product of the current amplification factor of the pnp transistor and the current amplification factor of the npn transistor that constitute the parasitic triac, and the ignition sensitivity of the triac becomes smaller than that of the parasitic triac. Greater than ignition sensitivity Since that, even by increasing the illuminance by the light emitted can be parasitic triac is prevented from light triggered, the zero-crossing operation does not become unstable, it is possible to ensure a zero-crossing operation.

According to a fifth aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a current amplification factor of a transistor including the semiconductor substrate, a gate region of the thyristor, and a cathode region of the thyristor is set to a value corresponding to the semiconductor substrate, the well region, and the drain; Tiger consisting of area It is characterized in that the current amplification factor is larger than the current amplification factor of the transistor. For example, if the conductivity type of the semiconductor substrate is n-type, the current amplification factor of the npn transistor forming the triac reduces the parasitic triac. Since the current amplification factor of the npn transistor is larger than the current amplification factor of the npn transistor, the product of the current amplification factor of the pnp transistor forming the triac and the current amplification factor of the npn transistor is obtained by multiplying the current amplification factor of the pnp transistor forming the parasitic triac by the current amplification factor of the npn transistor. It can be greater than the product of the current amplification factor and the firing sensitivity of the triac becomes higher than the firing sensitivity of the parasitic triac, and the parasitic triac will light even if the illuminance by the irradiated light is increased. Can be prevented, the zero-cross operation does not become unstable, It is possible to ensure the loss behavior.

According to a sixth aspect of the present invention, a semiconductor substrate is provided with a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to one of a semiconductor substrate, wherein a base concentration of a transistor including the semiconductor substrate, the well region, and the drain region is set to a value corresponding to the semiconductor substrate, the gate region of the thyristor, and the cathode region of the thyristor. A tiger consisting of It is characterized in that the base concentration of the transistor is higher than the base concentration. For example, if the conductivity type of the semiconductor substrate is n-type, the base concentration of the npn transistor forming the parasitic triac constitutes the triac Since the base concentration of the npn transistor is higher than the base concentration of the npn transistor, the current amplification factor of the npn transistor forming the triac is higher than that of the npn transistor forming the parasitic triac.
It becomes larger than the current amplification factor of the n transistor, and the product of the current amplification factor of the pnp transistor constituting the triac and the current amplification factor of the npn transistor is obtained by multiplying the current amplification factor of the pnp transistor constituting the parasitic triac by n
Since the firing sensitivity of the triac becomes larger than the firing sensitivity of the parasitic triac, the parasitic triac can be increased even if the illuminance of the irradiated light is increased. Light ignition can be prevented, the zero-cross operation does not become unstable, and the zero-cross operation can be ensured.

According to a seventh aspect of the present invention, a semiconductor substrate is provided with a light-triggering triac, two insulated gate field effect transistors, and two resistors, and the drain region and the source region of each insulated gate field effect transistor are formed on the main surface of the semiconductor substrate. Each insulated gate field effect transistor and each resistor formed in the well region formed on the side are connected between the gate and cathode of each of two thyristors forming a triac, and the gate of the insulated gate field transistor is connected to the anode of the thyristor. Alternatively, the semiconductor device is connected to any one of the semiconductor substrates, and is provided with a light-shielding film that covers a main surface side of the insulated gate field-effect transistor. Shields the irradiating light from irradiating the parasitic triac Therefore, even if the illuminance due to the irradiated light is increased, it is possible to prevent the parasitic triac from igniting light, the zero-cross operation does not become unstable, and the zero-cross operation can be secured. . The light-shielding film is not limited to a film that completely blocks light, but may be a film having a light transmittance that is small enough to prevent light emission of a parasitic triac.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) The semiconductor device of this embodiment is represented by an equivalent circuit of a triac 22 shown in FIG. 15, similarly to the conventional configuration shown in FIGS. As shown in FIGS. 1 and 2, the sectional structure and the surface layout are different from those of the conventional structure shown in FIGS. Here, FIG. 1 is a sectional view taken along the line BB ′ of FIG. The same components as those in the conventional configuration shown in FIGS. 18 to 20 are denoted by the same reference numerals.

In the semiconductor device of this embodiment, the p-type gate regions 3, 3 'are formed on the main surface side of the n-type semiconductor substrate 1 at a distance, and the main surface side in each of the p-type gate regions 3, 3' is formed. N-type cathode regions 4, 4 'are formed on the main surface side of n-type semiconductor substrate 1, and p-type anode regions 2', 2 are formed separately from p-type gate regions 3, 3 '.

Since the semiconductor device of this embodiment is represented by the same equivalent circuit as the triac 22 shown in FIG. 15 as described above, the n-type semiconductor substrate 1, the p-type gate region 3, and the n-type cathode region 4 and npn transistor T
1, the n-type semiconductor substrate 1, the p-type gate region 3 ', and the n-type cathode region 4' form an npn transistor T1 ', and the p-type anode region 2, the n-type semiconductor substrate 1, and the p-type gate region 3 together form a pnp transistor T2, and p
The pnp transistor T2 'is constituted by the n-type anode region 2', the n-type semiconductor substrate 1, and the p-type gate region 3 '.
Further, each resistor R in the equivalent circuit shown in FIG.
B and RB ′ are constituted by the respective p-type regions 5 and 5 ′ formed on the main surface side of the n-type semiconductor substrate 1. Further, the insulated gate field effect transistor T3 in the above equivalent circuit
T3 'is formed between n-type drain regions 7, 7' and n-type drain regions 7, 6 'in p-type well regions 6, 6' formed on the main surface side of n-type semiconductor substrate 1.
Source regions 8, 8 'are formed apart from each other, and gate electrodes 12, 12' are formed over the n-type drain regions 7, 7 'and the n-type source regions 8, 8'.

Each of the above-mentioned regions 2 to 8, 2 'to 8' is formed on the main surface side of n-type semiconductor substrate 1, and an insulating film made of a silicon oxide film is formed on the main surface of n-type semiconductor substrate 1. The surface electrodes 10, 10 ', 11, and 11' are formed by appropriately providing contact holes in the insulating film 9. Here, the surface electrodes 10 and 10 'are respectively connected to the main terminals M
T1 and MT2 are formed, and the surface electrodes 11 and 11 'are each configured as a p-gate electrode.

The drain electrodes of the insulated gate field effect transistors T3 and T3 'are respectively constituted by surface electrodes 11 and 11' (that is, they are shared with the p gate electrode), and the source electrodes are respectively formed on the surface. Electrode 1
0 ′, 10 (that is, the main terminal MT).
2, MT1).

By the way, in the semiconductor device of this embodiment,
The p-type anode regions 2 and 2 'are shared with the p-type well regions 6' and 6 described in the conventional configuration (that is, the p-type anode region 2 and the p-type well region 6 'are shared and the p-type anode The region 2 'and the p-type well region 6 are commonly used), and the parasitic triac formed in the semiconductor device of the present embodiment includes the p-type anode region 2', the n-type semiconductor substrate 1, and the p-type well region 6 ' Of the n-type drain region 7 '
npn 4-layer structure, pnp of p-type anode region 2, n-type semiconductor substrate 1, p-type well region 6, and n-type drain region 7
n4 layer structure.

Here, in the semiconductor device of this embodiment, the p-type anode regions 2 and 2 ′, the n-type semiconductor substrate 1 and the p-type
The base width of each pnp transistor composed of the p-type well regions 6 and 6 'is set to the respective pnp transistors T2 and T2 composed of the p-type anode regions 2 and 2', the n-type semiconductor substrate 1, and the p-type gate regions 3 and 3 '. , The current amplification factor of the pnp transistors T2 and T2 'comprising the p-type anode regions 2 and 2', the n-type semiconductor substrate 1 and the p-type gate regions 3 and 3 ' Region 2,
The current amplification factor is larger than that of a pnp transistor composed of 2 ′, n-type semiconductor substrate 1, and p-type well regions 6, 6 ′. That is, the current amplification factor of each pnp transistor T2, T2 'in the equivalent circuit of the triac 22 is made larger than the current amplification factor of each pnp transistor forming a part of the parasitic triac.

As described above, by making the current amplification factors of the pnp transistors T2 and T2 'forming a part of the triac larger than the current amplification factors of the pnp transistors forming a part of the parasitic triac, the semiconductor of the present embodiment is improved. In the device, the current amplification factors of the pnp transistors T2 and T2 'each including the p-type anode regions 2 and 2', the n-type semiconductor substrate 1, and the respective p-type gate regions 3 and 3 ', and the n-type semiconductor substrate 1 and The product of the current amplification factor of the npn transistors T1 and T1 'composed of the p-type gate regions 3, 3' and the respective n-type cathode regions 4, 4 'is equal to the p-type anode regions 2, 2' and the n-type semiconductor substrate 1. Composed of the p-type well regions 6 and 6 '
The current amplification factor of the p-transistor, the n-type semiconductor substrate 1 and p
It is larger than the product of the current amplification factor of the npn transistor composed of the well regions 6, 6 'and the n-type drain regions 7, 7'. That is, the pn that constitutes the triac
The product of the current amplification factor of the p-transistors T2 and T2 'and the current amplification factor of the npn transistors T1 and T1' is larger than the product of the current amplification factor of the pnp transistor constituting the parasitic triac and the current amplification factor of the npn transistor. I have.

Thus, in the semiconductor device of this embodiment,
Since the light firing sensitivity of the triac is greater than the light firing sensitivity of the parasitic triac, it is possible to prevent the light emission of the parasitic triac even if the illuminance of the irradiated light is increased. The zero-cross operation can be ensured without becoming unstable.

(Embodiment 2) The basic configuration of the semiconductor device of this embodiment is the same as the conventional configuration shown in FIGS. 18 to 20 and has the structure shown in FIGS. 1 and p-type well regions 6, 6 'and n-type drain regions 7, 7', the base concentration of the npn semiconductor substrate 1, p-type gate regions 3, 3 ', n-type cathode region 4, 4 ′ npn transistor T
The feature is that it is higher than the base density of 1, T1 '. In short, the feature is the depth profile of the impurity concentration along the directions of arrows F1 and F2 in FIGS. Here, FIG. 4 is a sectional view taken along line BB ′ of FIG.
FIG. 4 is a sectional view taken along the line CC ′ of FIG. 3. The same components as those in the conventional configuration shown in FIGS. 18 to 20 and 15 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 6 shows the depth profile of the impurity concentration along the directions of the arrows F1 and F2. The depth profile shown by the solid line in FIG. 6 is the depth profile along the arrow F1, and the broken line in FIG. Indicate the depth profile along the arrow F2. In addition,
In FIG. 6, a portion described as an n-type diffusion layer is indicated by an arrow F1.
Corresponds to the n-type cathode region 4 ', and the depth profile along the arrow F2 corresponds to the n-type drain region 7'. In FIG. 6, a portion described as a p-type diffusion layer corresponds to the p-type gate region 3 'with respect to the depth profile along the arrow F1, and corresponds to p with respect to the depth profile along the arrow F2.
It corresponds to the shaped well region 6 '.

In short, in the semiconductor device of this embodiment,
The base concentration (concentration of the p-type diffusion layer in FIG. 6) of the npn transistor forming a part of the parasitic triac is determined by the npn transistor T1 and the npn transistor T1 forming a part of the triac.
By increasing the base concentration of T1 '(the concentration of the p-type diffusion layer in FIG. 6), the semiconductor device is composed of the n-type semiconductor substrate 1, the p-type gate regions 3, 3', and the n-type cathode regions 4, 4 '. The current amplification factor of the npn transistors T1 and T1 'is made larger than the current amplification factor of the npn transistor including the n-type semiconductor substrate 1, the p-type well regions 6, 6', and the n-type drain regions 7, 7 '. . In FIG. 6, the peak value N1 of the impurity concentration of the p-type gate region 3 'is set lower than the peak value N2 of the impurity concentration of the p-type well region 6' (a region corresponding to the gate region of the parasitic triac). is there.

That is, in the semiconductor device of this embodiment,
Npn transistor T in equivalent circuit of triac
1, the current amplification factor of T1 'is made larger than the current amplification factor of the npn transistor which forms a part of the parasitic triac.

As described above, by making the current amplification factor of the npn transistors T1 and T1 'in the equivalent circuit of the triac larger than the current amplification factor of the npn transistor forming a part of the parasitic triac, in the present embodiment, p -Type anode regions 2, 2 ', n-type semiconductor substrate 1, and p-type
Pnp transistor T composed of gate regions 3, 3 '
2, the product of the current amplification factor of T2 'and the current amplification factor of npn transistors T1, T1' comprising n-type semiconductor substrate 1, p-type gate regions 3, 3 'and n-type cathode regions 4, 4'. , P-type anode regions 2 and 2 ′, n-type semiconductor substrate 1 and p-type
Current amplification factor of a pnp transistor composed of n-type well regions 6 and 6 ′, n-type semiconductor substrate 1 and p-type well regions 6 and 6 ′.
It is larger than the product of the current amplification factor of the npn transistor composed of 6 'and the n-type drain regions 7, 7'. That is, the pnp transistor T forming the triac
2, T2 'current amplification factor and npn transistors T1, T
The product of the current amplification factor of 1 ′ is larger than the product of the current amplification factor of the pnp transistor and the current amplification factor of the npn transistor constituting the parasitic triac.

Thus, in the semiconductor device of this embodiment,
Since the light firing sensitivity of the triac is greater than the light firing sensitivity of the parasitic triac, it is possible to prevent the light emission of the parasitic triac even if the illuminance of the irradiated light is increased. The zero-cross operation can be ensured without becoming unstable.

(Embodiment 3) The basic structure of the semiconductor device of this embodiment is the same as that of the embodiment and the conventional structure shown in FIGS. 18 to 20, and as shown in FIGS. Light-shielding films 15 and 15 'are provided above the insulated gate field effect transistors T3 and T3' formed by the drain regions 7, 7 ', the n-type source regions 8, 8', and the gate electrodes 12, 12 '. There is a feature in the point. Here, the light-shielding films 15 and 15 ′ are provided on the main surface side of the n-type semiconductor substrate 1 on the respective electrodes 10, 10 ′, 11, 11 ′, 12,
An insulating film 14 formed so as to cover 12 ′ (see FIG. 8)
Formed above. That is, the light shielding films 15 and 15 ′
It is formed so as to cover the main surface side of the insulated gate field effect transistors T3 and T3 '. In FIG. 7, illustration of the insulating film 14 is omitted.

Thus, in the semiconductor device of this embodiment,
Since the light which irradiates the parasitic triac can be prevented from being irradiated on the parasitic triac by the light shielding films 15 and 15 ', the parasitic triac can be light-irradiated even if the illuminance by the irradiated light is increased. Can be prevented, the zero-cross operation does not become unstable, and the zero-cross operation can be ensured. The light shielding films 15 and 15 '
The film is not limited to a film that completely blocks light, but may be a film having a light transmittance small enough to prevent light firing of a parasitic triac.

The semiconductor device of each of the above embodiments is represented by an equivalent circuit as shown in FIG. 15, and the gates of the insulated gate field-effect transistors T3 and T3 'are connected to the anodes of the thyristors (that is, the main terminals MT1 and MT2). Connected, but with insulated gate field transistors T3, T3 '
The same effect can be obtained even if the gate is changed to be connected to the n-type semiconductor substrate 1. Further, as the n-type semiconductor substrate 1 in each of the above embodiments, for example, a silicon substrate may be used, but a semiconductor substrate other than the silicon substrate may be used.

[0048]

According to the first aspect of the present invention, a semiconductor substrate is provided with a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are on the main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field transistor is connected to the anode of the thyristor Or a semiconductor device connected to any of the semiconductor substrates, wherein the firing sensitivity of the triac is reduced by the firing of a parasitic triac including the anode region of the thyristor, the semiconductor substrate, the well region, and the drain region. Which is larger than the sensitivity Since the firing sensitivity of the triac is higher than the firing sensitivity of the parasitic triac, it is possible to prevent the parasitic triac from firing even if the illuminance of the irradiated light is increased, so that the zero-cross operation is unstable. This has the effect that the zero-cross operation can be ensured.

According to a second aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a current amplification factor of a transistor including an anode region of the thyristor, a gate region of the semiconductor substrate and a gate region of the thyristor, and a gate region of the semiconductor substrate and the thyristor; The power of the thyristor The product of the current amplification factor of the transistor formed of the thyristor, the current amplification factor of the transistor formed of the anode region of the thyristor, the semiconductor substrate, and the well region, and the semiconductor substrate, the well region, and the drain region And the product of the current amplification factor of the pnp transistor forming the triac and the current amplification factor of the npn transistor is the current of the pnp transistor forming the parasitic triac. Since the amplification factor is larger than the product of the current amplification factor of the npn transistor, the ignition sensitivity of the triac becomes greater than the ignition sensitivity of the parasitic triac. Since ignition can be prevented, zero-cross operation becomes unstable Razz, there is an effect that it is possible to ensure a zero-crossing operation.

According to a third aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a current amplification factor of a transistor including an anode region of the thyristor, a gate region of the semiconductor substrate, and a gate region of the thyristor; The well region and Is obtained by larger than the current amplification factor of the Ranaru transistors, for example, if the conductivity type of the semiconductor substrate is n-type, p constituting the triac
Since the current amplification factor of the np transistor is larger than the current amplification factor of the pnp transistor forming the parasitic triac, the product of the current amplification factor of the pnp transistor forming the triac and the current amplification factor of the npn transistor forms the parasitic triac. It can be made larger than the product of the current amplification factor of the pnp transistor and the current amplification factor of the npn transistor, and the ignition sensitivity of the triac becomes greater than the ignition sensitivity of the parasitic triac, increasing the illuminance due to the emitted light. Even if this is done, the light emission of the parasitic triac can be prevented, so that there is an effect that the zero-cross operation does not become unstable and the zero-cross operation can be secured.

According to a fourth aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a base width of a transistor including the anode region of the thyristor, the semiconductor substrate, and the well region is set to an anode region of the thyristor, the semiconductor substrate, and the thyristor. The gate area Composed and made larger than the base width of the transistor, for example, the conductivity type of the semiconductor substrate is n
Pnp that constitutes a parasitic triac
Since the base width of the transistor is larger than the base width of the pnp transistor that forms the triac, the current amplification factor of the pnp transistor that forms the triac becomes larger than the current amplification factor of the pnp transistor that forms the parasitic triac. And the product of the current amplification factor of the pnp transistor and the current amplification factor of the npn transistor can be larger than the product of the current amplification factor of the pnp transistor and the current amplification factor of the npn transistor that constitute the parasitic triac. Since the firing sensitivity of the triac is higher than the firing sensitivity of the parasitic triac, it is possible to prevent the parasitic triac from firing even when the illuminance of the irradiated light is increased, and the zero-cross operation becomes unstable. And ensure zero-cross operation There is an effect that theft can be.

According to a fifth aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to any of the semiconductor substrates, wherein a current amplification factor of a transistor including the semiconductor substrate, a gate region of the thyristor, and a cathode region of the thyristor is set to a value corresponding to the semiconductor substrate, the well region, and the drain; Tiger consisting of area Is obtained by larger than the current amplification factor of the register, for example, if the conductivity type of the semiconductor substrate is n-type, npn current amplification factor of the npn transistors constituting the triac constitutes a parasitic triac
Since the current amplification factor is larger than the current amplification factor of the transistor, the product of the current amplification factor of the pnp transistor constituting the triac and the current amplification factor of the npn transistor is obtained by multiplying the current amplification factor of the pnp transistor constituting the parasitic triac by np
It can be greater than the product of the current amplification factor of the n-transistor and the ignition sensitivity of the triac becomes greater than the ignition sensitivity of the parasitic triac. Since firing can be prevented, the zero-cross operation does not become unstable, and the zero-cross operation can be ensured.

According to a sixth aspect of the present invention, a semiconductor substrate includes a triac, two insulated gate field effect transistors, and two resistors, and a drain region and a source region of each insulated gate field effect transistor are formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of the two thyristors forming the triac, and the gate of the insulated gate field effect transistor is the anode of the thyristor or the A semiconductor device connected to one of a semiconductor substrate, wherein a base concentration of a transistor including the semiconductor substrate, the well region, and the drain region is set to a value corresponding to the semiconductor substrate, the gate region of the thyristor, and the cathode region of the thyristor. A tiger consisting of And made larger than the base density of the register, for example, if the conductivity type of the semiconductor substrate is n-type, npn base concentration of npn transistors constituting the parasitic triac constituting said triac
Since the current density is higher than the base concentration of the transistor, the current amplification factor of the npn transistor forming the triac becomes larger than the current amplification factor of the npn transistor forming the parasitic triac, and the current amplification factor of the pnp transistor forming the triac and npn The product of the current amplification factor of the transistor and pn which constitutes a parasitic triac
It can be made larger than the product of the current amplification factor of the p transistor and the current amplification factor of the npn transistor, and the ignition sensitivity of the triac becomes larger than the ignition sensitivity of the parasitic triac. Even if it is increased, the light emission of the parasitic triac can be prevented, and the zero-cross operation does not become unstable, and the zero-cross operation can be ensured.

According to a seventh aspect of the present invention, a semiconductor substrate is provided with a light-triggering triac, two insulated gate field effect transistors, and two resistors, and the drain region and the source region of each insulated gate field effect transistor are formed on the main surface of the semiconductor substrate. Each insulated gate field effect transistor and each resistor formed in the well region formed on the side are connected between the gate and cathode of each of two thyristors forming a triac, and the gate of the insulated gate field transistor is connected to the anode of the thyristor. Or a semiconductor device connected to one of the semiconductor substrates, wherein a light-shielding film is provided to cover a main surface side of the insulated gate field-effect transistor, and light such that a parasitic triac ignites light is generated. It is possible to prevent the triac from being irradiated by the light-shielding film. Therefore, even if the illuminance due to the irradiated light is increased, it is possible to prevent the parasitic triac from igniting light, and the zero-cross operation does not become unstable, and the zero-cross operation can be ensured. . The light-shielding film is not limited to a film that completely blocks light, but may be a film having a light transmittance that is small enough to prevent light emission of a parasitic triac.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment.

FIG. 2 is a schematic plan view of the same.

FIG. 3 is a schematic plan view showing a second embodiment.

4 is a sectional view taken along the line B-B 'of FIG. 3, showing the above.

FIG. 5 is a sectional view taken along the line C-C 'of FIG. 3, showing the same as above.

FIG. 6 is an explanatory diagram showing a depth profile of an impurity concentration in a main part according to the first embodiment;

FIG. 7 is a schematic plan view showing a third embodiment.

8 is a sectional view taken along the line C-C 'of FIG. 7, showing the same as above.

FIG. 9 is a schematic sectional view showing a conventional example.

FIG. 10 is a schematic configuration diagram of the above.

FIG. 11 is an equivalent circuit diagram of the above.

FIG. 12 is a schematic configuration diagram of another conventional example.

FIG. 13 is an equivalent circuit diagram of the above.

FIG. 14 is a schematic configuration diagram of another conventional example.

FIG. 15 is an equivalent circuit diagram of a semiconductor relay showing still another conventional example.

FIG. 16 is a circuit diagram showing a usage example of the above.

FIG. 17 is an operation explanatory diagram in the usage example of the above.

FIG. 18 is a schematic plan view of a semiconductor device used for the semiconductor relay of the above.

19 is a sectional view taken along line B-B 'of FIG.

20 is a sectional view taken along line C-C 'of FIG.

[Explanation of symbols]

 1 n-type semiconductor substrate 2, 2 'p-type anode region 3, 3' p-type gate region 4, 4 'n-type cathode region 6, 6' p-type well region 7, 7 'n-type drain region 8, 8' n Source region 9 Insulating film 10, 10 'Surface electrode 11, 11' Surface electrode 12, 12 'Gate electrode

Claims (7)

[Claims] 1. A semiconductor substrate comprising a triac, two insulated gate field effect transistors, and two resistors, wherein a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on a main surface side of the semiconductor substrate. Formed, each insulated gate field effect transistor and each resistor being connected between the gate and cathode of each of the two thyristors forming the triac;
A semiconductor device in which the gate of the insulated gate field-effect transistor is connected to either the anode of the thyristor or the semiconductor substrate, and the ignition sensitivity of the triac is reduced by changing the anode region of the thyristor, the semiconductor substrate, and the well region. A semiconductor device, wherein the ignition sensitivity is higher than a firing sensitivity of a parasitic triac including the drain region and the drain region. 2. A semiconductor substrate comprising a triac, two insulated gate field effect transistors, and two resistors, wherein a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on a main surface side of the semiconductor substrate. Formed, each insulated gate field effect transistor and each resistor being connected between the gate and cathode of each of the two thyristors forming the triac;
A semiconductor device in which the gate of the insulated gate field-effect transistor is connected to either the anode of the thyristor or the semiconductor substrate, and the current of a transistor including the anode region of the thyristor, the semiconductor substrate, and the gate region of the thyristor The product of the amplification factor and the current amplification factor of the transistor consisting of the semiconductor substrate, the gate region of the thyristor, and the cathode region of the thyristor is the product of the transistor consisting of the anode region of the thyristor, the semiconductor substrate, and the well region. A semiconductor device characterized by being larger than a product of a current amplification factor and a current amplification factor of a transistor including the semiconductor substrate, the well region, and the drain region. 3. A semiconductor substrate comprising a triac, two insulated gate field effect transistors, and two resistors, wherein a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on a main surface side of the semiconductor substrate. Formed, each insulated gate field effect transistor and each resistor being connected between the gate and cathode of each of the two thyristors forming the triac;
A semiconductor device in which the gate of the insulated gate field-effect transistor is connected to either the anode of the thyristor or the semiconductor substrate, and the current of a transistor including the anode region of the thyristor, the semiconductor substrate, and the gate region of the thyristor A semiconductor device, wherein an amplification factor is larger than a current amplification factor of a transistor including the anode region of the thyristor, the semiconductor substrate, and the well region. 4. A semiconductor substrate comprising a triac, two insulated gate field effect transistors, and two resistors, wherein a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on a main surface side of the semiconductor substrate. Formed, each insulated gate field effect transistor and each resistor being connected between the gate and cathode of each of the two thyristors forming the triac;
A semiconductor device in which the gate of the insulated gate field-effect transistor is connected to either the anode of the thyristor or the semiconductor substrate, wherein the base width of the transistor including the anode region of the thyristor, the semiconductor substrate, and the well region is A semiconductor device comprising: a transistor including an anode region of the thyristor, the semiconductor substrate, and a gate region of the thyristor; 5. A semiconductor substrate comprising a triac, two insulated gate field effect transistors and two resistors, wherein a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on a main surface side of the semiconductor substrate. Formed, each insulated gate field effect transistor and each resistor being connected between the gate and cathode of each of the two thyristors forming the triac;
A semiconductor device in which the gate of the insulated gate field-effect transistor is connected to either the anode of the thyristor or the semiconductor substrate, and the current of a transistor comprising the semiconductor substrate, the gate region of the thyristor, and the cathode region of the thyristor A semiconductor device, wherein an amplification factor is larger than a current amplification factor of a transistor including the semiconductor substrate, the well region, and the drain region. 6. A semiconductor substrate comprising a triac, two insulated gate field effect transistors and two resistors, wherein a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on a main surface side of the semiconductor substrate. Formed, each insulated gate field effect transistor and each resistor being connected between the gate and cathode of each of the two thyristors forming the triac;
A semiconductor device in which the gate of the insulated gate field-effect transistor is connected to either the anode of the thyristor or the semiconductor substrate, wherein the base concentration of the transistor comprising the semiconductor substrate, the well region, and the drain region is A semiconductor device, wherein the base concentration of a transistor including a semiconductor substrate, a gate region of the thyristor, and a cathode region of the thyristor is higher than a base concentration of the transistor. 7. A semiconductor substrate comprising a triac, two insulated gate field effect transistors and two resistors, wherein a drain region and a source region of each insulated gate field effect transistor are formed in a well region formed on a main surface side of the semiconductor substrate. Each insulated gate field effect transistor and each resistor are connected between the gate and cathode of each of two thyristors forming a triac, and the gate of the insulated gate field transistor is connected to either the anode of the thyristor or the semiconductor substrate. A connected semiconductor device, comprising: a light-shielding film that covers a main surface side of the insulated gate field-effect transistor.