JP2002159713A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of easily confirming the operations of respective game devices. SOLUTION: This game machine is provided with the game devices for performing the operations in relation to a game and a control board for controlling the operations of the game devices. A test command output means for transmitting a series of operation commands for tests to the control board is provided. The control board is provided with test operation means (A15 and A16) for making the game devices perform test operations in a predetermined form corresponding to the series of the operation commands for the tests transmitted from the test command output means respectively in the case of shifting to a test mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine having test operation means for testing the operation state of each game machine of the game machine at a manufacturer, a game store, or the like.

[0002]

2. Description of the Related Art Conventionally, the operating state of each gaming machine of a gaming machine,
For example, the blinking state of a game-related lamp, the state of sound generation,
In some cases, the display state of the display device is tested by a manufacturer or a game arcade to confirm the operation. In other words, in order to check whether there is a malfunction in the gaming operation, for example, in a manufacturer, each gaming machine is operated at the final stage of manufacturing a gaming machine to check its state, and in a gaming shop, depending on the situation. Each gaming device is operated to check its state. As a confirmation method at that time, create a game state in which each gaming device operates, for example, if you want to change the display on the display device, by entering the game ball into the starting winning opening, the operation state is changed It is common to confirm. However, in such a gaming machine, a great deal of labor and time is required to check the gaming device.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to provide a gaming machine which allows the user to easily confirm the operation of each gaming machine.

[0004]

According to a first aspect of the present invention, there is provided a gaming machine having a gaming machine for performing an operation related to a game, and a control board for controlling the operation of the gaming machine. A test command output means for transmitting a series of test operation commands to the control board is provided,
A test for causing the gaming machine to perform a test operation in a predetermined manner corresponding to each of a series of test operation commands transmitted from the test command output means when the control board shifts to a test mode. An operating means is provided.

According to a second aspect of the present invention, in the gaming machine according to the first aspect, the control board controls an operation of the gaming machine in accordance with a command from a main control board which performs a main control of a game. The test command output means transmits a series of test operation commands to the sub-control board, and the test mode operation means is provided on the sub-control board. Things.

According to a third aspect of the present invention, in the gaming machine according to the second aspect, the test command output means is included in the main control board.

According to a fourth aspect of the present invention, in the gaming machine according to any one of the first to third aspects, the series of test operation commands are assigned to each signal line of the control board. The operation of the gaming machine is different for each content of the test operation command.

According to a fifth aspect of the present invention, in the gaming machine according to any one of the first to fourth aspects, the test operation means does not accept the test operation command except in the test mode. It is characterized by the following.

According to a sixth aspect of the present invention, in the gaming machine according to any one of the first to fifth aspects, the control board is configured to be able to shift to the test mode only for a predetermined period. It is a feature.

According to a seventh aspect of the present invention, in the gaming machine according to the sixth aspect, the predetermined period is a period from when the power is turned on until a predetermined time elapses.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, a pachinko gaming machine will be described as an embodiment of a gaming machine. However, the present invention is not limited to this, and may be, for example, a coin-type gaming machine or the like. Any gaming machine having a gaming device to be performed and a control board for controlling the operation of the gaming device is all objects.

FIG. 1 is a block diagram of a main part of a control system provided in the pachinko gaming machine of the present embodiment. The main control circuit 1 performs a main control of the game and is provided on a main control board (not shown). The main control circuit 1 includes a one-chip microcomputer 2, an input / output circuit 3, an input / output circuit 4, and the like. The one-chip microcomputer 2 has a CPU 5 therein.
A RAM 6 and a ROM 7 are provided. In this embodiment, the main control circuit 1 or the one-chip microcomputer 2 includes a test command output unit for transmitting a series of test operation commands.

The one-chip microcomputer 2 is connected via an input / output circuit 3 to various control circuits, various driving devices, various switches, and the like. That is, the input / output circuit 3
A start port sensor 8 provided for a start winning port provided on a game board (not shown), a test start switch 9 provided on the back of the game machine, and other winning sensors (for example, left and right gates of the game board). (A normal symbol start switch for detecting the passage of the game ball to the player).

A relay circuit 10 is connected to the input / output circuit 3. The relay circuit 10 has a solenoid 11 for opening a special winning opening (not shown), and a game ball winning the special winning opening. And a specific area sensor 13 for detecting the passage of a game ball to a specific area provided in the special winning opening. Further, the input / output circuit 3 includes a lamp control circuit 14 for controlling lighting of each LED, various display lamps, and the like provided on the game board surface, and a voice control for performing voice control for increasing various sound effects from the speaker 16. The circuit 15 and other solenoids (for example, a solenoid that normally expands the electric accessory) are connected. The lamp control circuit 14 is provided on a lamp control board (not shown), and the voice control circuit 15 is provided on a voice control board (not shown). Although not shown, the lamp control circuit 14 and the voice control circuit 15 include a CPU, a ROM, and a RAM.

The input / output circuit 4 has a payout control circuit 17.
And the special symbol display device 21 is connected. The payout control circuit 17 includes a control CPU (not shown)
A RAM having a storage area for holding and storing a work area by the PU and the number of prize balls corresponding to each prize ball command, and a ROM storing control data, a control program for prize ball payout, and the like are provided. I have.

The payout control circuit 17 controls the drive of the prize ball payout device 18 in accordance with the prize ball command instructed from the main control circuit 1 to control the prize ball payout. Dispensing control circuit 1
7 is connected to the above-mentioned main control circuit 1 through communication, and also connected to a hitting ball firing device 20 for firing a pachinko ball toward a game board via a firing control circuit 19. 20 is controlled to stop operation / cancel operation stop.

The special symbol display device 21 includes a display control circuit 22 connected to the main control circuit 1 via the input / output circuit 4.
And a liquid crystal display panel 23. The display control circuit 22 stores therein a display control CPU (not shown), a RAM having image data and a work area by the CPU, display control data corresponding to each command, and characters and designs. A ROM and the like are provided. The display control circuit 22 is provided on a display control board (not shown).

When the display control circuit 22 receives a strobe signal from the main control circuit 1, the CPU recognizes a display control command based on the strobe signal. Display control data, characters and designs are read from the ROM from a data area corresponding to the display control command, and are stored in a RAM that stores the image data.
When the stored image data comes in the display order, the image data is read out from the RAM and displayed on the liquid crystal display panel 23.

FIG. 8 is a block diagram corresponding to the requirements set forth in claim 1. In the present embodiment, the gaming device according to claim 1 includes a light emitting unit such as a lamp and an LED that lights or blinks in connection with the game, a sound amplification unit for increasing various sounds related to the game, Special symbol display device 2 that can display symbols
1 corresponds. The sub-control board provided with the test operation means according to claim 1 corresponds to the audio control circuit 15, the lamp control circuit 14, and the display control circuit 22, but is not limited thereto. Any control board may be used as long as it controls the operation. Further, for example, a configuration in which the main control circuit 1 directly controls the gaming device, or a configuration in which the control device other than the main control circuit 1 directly controls the gaming device may be adopted. Further, in the embodiment, each of the main control circuit 1 and the sub control circuits (the lamp control circuit 14, the voice control circuit 15, and the display control circuit 22) is provided on the back surface of the gaming machine as separate substrates.

In the pachinko gaming machine of the embodiment configured as described above, the CPU of the main control circuit 1 (hereinafter referred to as CPU)
A test command output process executed by the main CPU and a test operation process executed by a CPU (hereinafter, a sub CPU) of each of the sub control circuits 14, 15, 22 (hereinafter, simply referred to as a sub control circuit) will be described. FIG. 2 is a flowchart showing a main routine of a process executed by the main CPU of the main control circuit 1. 3 and 4
5 is a flowchart showing a main routine of a process executed by each sub CPU of each sub control circuit.

In the main control circuit 1, a main CPU
Executes a main routine every predetermined timing (for example, 4 ms). In the main routine, game-related processing (normal processing) relating to the game and test command output processing shown in steps S04 to S06 in FIG. 2 are executed. Note that the game-related processing (the normal processing in step S03) is not particularly related to the gist of the present invention, and thus the description is omitted.

In each of the sub control circuits, the sub C
The PU executes a main routine at a predetermined timing.
In the main routine of the sub control circuit, each game device (in this embodiment, a lamp / LED, a liquid crystal display panel 23 of a special symbol display device 21, a speaker 1 for sound amplification).
The operation-related processing (normal processing) relating to the normal operation 6) and the test operation processing shown in steps A09 to A17 in FIG. 4 are executed. Control in these sub-control circuits is performed subordinately to the main control circuit. Note that the operation-related processing (normal processing) performed by each sub CPU does not deeply relate to the gist of the present invention, and a description thereof will be omitted.

The test command output processing executed by the main CPU of the main control circuit will be described with reference to the flowchart of FIG. Immediately after the power is turned on, the main CPU performs an initialization process (step S01), and sets the stack and sets R
By initializing the AM area, each flag, each register, and each storage area required for the following processing are initialized. After ending the initialization processing in step S01, the main CPU proceeds to step S02, and determines whether or not the test start switch 9 provided on the back of the gaming machine is on. If the test start switch 9 is not turned on, the main CPU determines that step S02 is false, performs normal processing (step S03), and waits for input of a reset signal after finishing the normal processing.

The main CPU executes a main routine (each program stored in the ROM 7 of the main control circuit 1) every reset interrupt (for example, 4 ms), that is, step S02 to step S06 or step S02 described below. And the processing of step S03. When the reset signal is input, the main CPU performs steps S02 to S03 again.

When performing a test, an operator operates and inputs a test start switch 9 provided on the back of the gaming machine when the power is turned on. When the operator operates and inputs the test start switch 9, the test start switch 9 is turned on. The main CPU determines that step S02 is true, and proceeds to step S04.

The main CPU transmits a test mode shift command to the sub CPU (sub control board) (step S04). After transmitting the test mode shift command, the main CPU sequentially transmits a series of test operation commands to the sub CPU (step S05). When the transmission of the test operation command ends, the main CPU issues a test mode end command. After the transmission to the sub CPU (step S06), the transmission of the test mode end command is completed, and the input of the reset signal is waited.

Here, the test operation command will be described. FIG. 5 is a table showing test operation commands transmitted to the lamp control circuit 14 provided on the lamp control board, which is a part of the sub control board, and the contents of the operation. FIG. FIG. 7 is a table showing test operation commands transmitted to the audio control circuit 15 provided on the audio control board which is a part of the board and the contents of the operation in a table format.
FIG. 5 is a diagram showing, in a table form, test operation commands transmitted to a display control circuit 22 provided on a display control board which is a part of a sub-control board and the contents of the operation.

The test operation command is composed of bit data of at least the number of signal lines assigned to each signal line of the control board, and is composed of 8 bits in this embodiment. As shown in FIGS. 5 to 7, $ 01 (00000
Eight test operation commands from 001) to $ 80 (10000000) are provided. For each of the eight test operation commands, the operation content of each gaming device to be controlled by each sub CPU is predetermined. At the same time, the operation content of each gaming machine is different for each content of the test operation command.

For example, when the sub CPU receives the test operation command “$ 01”, if the sub CPU is the lamp control circuit 14, the audio control circuit 15 turns on the frame decoration lamp 1. In the case of the display control circuit 22 of the special symbol display device 21, the color bar is shifted from right to left with respect to the liquid crystal display panel 23 so as to generate the sound of “do” to the speaker in the case of The sub CPU of each sub control circuit outputs operation data to operate the control target so as to perform scroll display.

For example, when the sub CPU receives the test operation command “$ 02”, if the sub CPU is the lamp control circuit 14, the audio control is performed so that the frame decoration lamp 2 is turned on. In the case of the circuit 15, a color bar is displayed from the left with respect to the liquid crystal display panel 23 in the case of the display control circuit 22 of the special symbol display device 21 so as to generate the sound “レ” to the speaker. The sub CPU of each sub control circuit outputs operation data to operate the control target so as to scroll right. As described above, the contents of the test operation command ($ 0
The operation contents of each gaming machine are different for each of the eight types (1 to $ 80).

Then, for example, if the sound of “do” does not occur from the speaker during the test, the signal line 1 (bit 1 or data bus 1) related to the audio control circuit 15 is abnormal (for example, disconnection, short circuit, etc.). Can easily be determined to have occurred. As described above, if a test operation is performed using a command associated with a bit, it is possible to easily determine where an abnormality has occurred. Further, in the case of a lamp, if the number of commands is increased to the number of lamp systems, it is possible to configure so that a defect in the lamp relay board or the connection harness can be found. With respect to other gaming machines, if configured in this way, it is also possible to find defects in the relay board and the connection harness.

The test operation processing executed by the sub CPU of the sub control circuit will be described with reference to the flowcharts of FIGS. Immediately after the power is turned on, the sub CPU performs initialization processing (step A01), and sets the stack and RAM.
By initializing the area, each flag, each register, and each storage area required for the following processing are initialized.

After completing the initialization processing in step A01, the sub CPU sets a value corresponding to a predetermined time (for example, 60 seconds) as a monitoring time from when the power is turned on to the power-on monitoring timer (step A02). It is determined whether or not a command has been transmitted to the command receiving port (step A).
03).

If there is no command transmission from the main CPU, the sub CPU determines that step A03 is false, shifts to step A04, and determines whether or not the test mode flag is reset (step A04). In addition,
As a result of the test mode flag being reset (the value of the flag is set to 0) by the initialization processing of step A01, the sub CPU determines that step A04 is true and determines that step A04 is true.
The process proceeds to 05, and it is determined whether or not the power-on monitoring timer is 0 (step A05). In this case, the value corresponding to the monitoring time from when the power is turned on is set in the power-on monitoring timer, so that the value of the power-on monitoring timer is not zero. The sub CPU determines that step A05 is false and decrements the power-on monitoring timer (step A5).
06), the normal process of step A07 is executed, and when the normal process is completed, the process returns to step A03, and it is determined again whether or not a command is transmitted to the command receiving port.

When no command is transmitted from the main CPU to the command receiving port, the sub CPU determines that step A03 is false, step A04 is true, and step A05 is false, and the power-on monitoring timer in step A06 is decremented. , The normal processing of step A07 is repeated. As a result, the value set in the power-on monitoring timer is reduced as a result of repeatedly performing the subtraction of the power-on monitoring timer in step A06.

If the test start switch 9 is operated and input within a predetermined time (for example, 60 seconds, etc.) as the monitoring time from when the power is turned on, the main CPU executes step S04, and A test mode transition command is transmitted to the sub CPU. In this case, before the value set in the power-on monitoring timer is reduced to 0 by the processing in step A06, the test mode transition command is transmitted from the main CPU to the command receiving port of the sub CPU. . The sub CPU determines that step A03 is true, receives the transmitted command (step A08), and determines whether the received command is a test mode transition command (step A09).

In this case, the sub CPU determines that the received command is a test mode shift command, shifts to step A10, and determines whether the power-on monitoring timer is 0 or not. In this case, the value of the power-on monitoring timer is 0
As a result, the sub CPU determines that step A10 is false, sets the test mode flag (step A11), clears the power-on monitoring timer to 0 (step A12), returns to step A03, and again executes the command It is determined whether or not a command has been transmitted to the receiving port.

When no command is transmitted from the main CPU to the command receiving port, the sub CPU sets the test mode flag and clears the power-on monitoring timer to 0.
3 is determined to be false and step A04 is determined to be false.
And a standby state in which step A04 is repeated.

As described above, when the main CPU transmits the test mode transition command, a series of test operation commands are sequentially transmitted to the sub CPU. For example, in the case of the lamp control circuit 14,
As shown in FIG. 5, the test operation command "$ 01",
“$ 02”, “$ 04”, “$ 08”, “$ 10”,
“$ 20”, “$ 40”, and “$ 80” are sequentially transmitted,
It is received by the sub CPU of the lamp control circuit 14. In the present embodiment, the audio control circuit 15 and the display control circuit 2
2, the same test operation command “$ 01”,
“$ 02”, “$ 04”, “$ 08”, “$ 10”,
“$ 20”, “$ 40”, and “$ 80” are sequentially transmitted,
It is received by each sub CPU.

The sub CPU determines step A03 to be true each time a test operation command is transmitted, and receives the command transmitted in step A08. In this case, the received command is a test operation command. As a result, it is determined that the process of determining whether the received command in Step A09 is a test mode transition command is false, and the process of determining whether the received command in Step A13 is a test mode end command is false, As a result of the test mode flag being set, step A14 is determined to be true, and the determination processing of step A15 as to whether the received command is a test operation command is determined to be true. Is output to the gaming device to be controlled (step A16). Thereby, a test operation of the gaming machine is executed.

The specific contents of the test operation, which differs for each test operation command, are shown in FIGS. 5 to 7, and the description thereof is omitted here. The sub CPU is
When the process of step A16 is executed, the process returns to step A03, repeats steps A03 and A04 again, and waits until a command is transmitted to the command receiving port.

As described above, when the transmission of the test operation command is completed, the main CPU transmits a test mode end command to the sub CPU. Therefore, the test mode end command is received by the sub CPU. Sub CPU
Determines that step A03 is true, receives a test mode end command in step A08, determines step A09 to be false, and determines step A13 to be true. And
The test mode flag is reset (step A17),
The process proceeds to the normal process of step A07, and after the normal process is completed, the process returns to step A03.

Note that, as a result of resetting the test mode flag, the test operation processing by the sub CPU ends. Hereinafter, as a result of the test mode flag being reset and the power-on monitoring timer being cleared to 0, the sub CPU determines that step A03 is false, determines that step A04 is true, and determines that step A05 is true, Step A
07 is repeatedly executed.

After the test operation process by the sub CPU is completed, the test start switch 9
Is input, the test start switch 9
Is transmitted from the main CPU to the sub CPU based on the operation input. In the sub control circuit, the test mode flag is reset, and the value of the power-on monitoring timer is set to 0 by the processing in step A12.
As a result of being cleared, the sub CPU proceeds to step A03.
Is true, the command is received in step A08, and the command received in step A09 is determined to be a test mode transition command. As a result of the power-on monitoring timer being 0, the normal processing in step A07 Move to Therefore, the test mode flag is not set,
The reset state is maintained. As is clear from the flowchart of FIG. 4, when the test mode flag is in the reset state, the test operation command is not accepted, so that
The test operation processing is not substantially performed by the sub CPU. Therefore, even if the test start switch 9 is operated after the test operation process by the sub CPU is completed, the test operation process is not performed.

Further, even if the test start switch 9 is operated after a predetermined time (for example, 60 seconds) as the monitoring time has elapsed since the power was turned on, the test operation processing is not performed. That is, after the power is turned on, the sub CPU determines that the step A03 is false, the step A04 is true, and the step A05 is false, and repeats the subtraction of the power-on monitoring timer in step A06 and the normal processing in step A07. As a result of the repeated subtraction of the power-on monitoring timer of A06, the value set in the power-on monitoring timer is reduced, and when a predetermined time (for example, 60 seconds or the like) as the monitoring time has elapsed, The value of the power-on monitoring timer becomes 0. Therefore, the test mode flag remains reset, and the value of the power-on monitoring timer is 0. Hereinafter, the sub CPU determines that step A03 is false, and
04 is determined to be true, step A05 is determined to be true, and the normal processing of step A07 is repeatedly executed.

When the test start switch 9 is operated after a predetermined time (for example, 60 seconds) as the monitoring time has elapsed since the power was turned on, a test mode shift command is transmitted from the main CPU to the sub CPU. However, in the sub-control circuit, as a result of the test mode flag being reset and the value of the power-on monitoring timer being 0, as in the case where the above-described test operation processing is completed,
The sub CPU determines step A03 as true, receives the command in step A08, and determines that the command received in step A09 is the test mode transition command.
As a result of shifting to the normal processing in step A07, the test mode flag is not set and the reset state is maintained.
As described above, when the test mode flag is in the reset state, the test operation command is not accepted, so that the sub CPU does not substantially perform the test operation process. Therefore, even when the test start switch 9 is operated after a predetermined time (for example, 60 seconds) as the monitoring time has elapsed since the power was turned on, the test operation process is not performed. As described above, it is possible to shift to the test mode only for a predetermined period (from the time when the power is turned on until a predetermined time elapses).

In this embodiment, the test command output means for transmitting the test operation command to the sub-control circuit is included in the main control circuit 1 (main control board), but is not limited to this. Instead, the configuration may be such that the test command output means is provided outside the gaming machine as a separate device. In this case, the test command output means and the main control circuit are connected to each other, and the test operation can be performed via the main control circuit, or the test command output means can be directly connected to the sub control circuit to perform the test operation. May be configured.

[0048]

According to the first aspect of the present invention, the control board for controlling the operation of the gaming machine is provided with a series of test operation commands transmitted from the test command output means when the mode shifts to the test mode. The game device can be tested in a predetermined manner corresponding to each of the above, so that the test operation can be easily confirmed.

According to the second aspect of the present invention, the sub-control board for controlling the operation of the gaming machine includes a series of test operation commands transmitted from the test command output means when the test mode is entered. The test operation of the gaming machine can be performed in a predetermined manner corresponding to the above, so that the test operation of the gaming machine controlled by the sub-control board can be easily confirmed.

According to the third aspect of the present invention, the test command output means is included in the main control board, so that the board configuration can be simplified.

According to the fourth aspect of the present invention, the series of test operation commands consist of at least the number of bit lines assigned to each signal line of the control board, and the contents of the test operation command Since the operation of the gaming machine differs from one game device to another, it is possible to confirm an abnormality (disconnection, short circuit, etc.) in the communication state of each signal line.

According to the fifth aspect of the present invention, the test operation means does not accept the test operation command except in the test mode. Even if the same command is used when not in the mode, the test operation is not performed.

According to the configuration described in claim 6, the control board is configured to be able to shift to the test mode only for a predetermined period, so that the shift period of the test mode can be limited.

According to the seventh aspect of the present invention, the test mode can be shifted to the test mode only during a predetermined period from when the power is turned on until a predetermined time elapses. In addition to the above, there is no problem that a test operation is performed at a normal time (for example, during business hours) after a predetermined time has elapsed since the power was turned on.

[Brief description of the drawings]

FIG. 1 is a main block diagram of a control system provided in a pachinko gaming machine according to an embodiment.

FIG. 2 is a diagram showing a main C of a main control circuit according to the embodiment;
Flowchart showing a main routine of processing executed by a PU

FIG. 3 is a flowchart showing a part of a main routine of a process executed by each sub CPU of each sub control circuit of the above.

FIG. 4 is a continuation of the flowchart of FIG. 3;

FIG. 5 is a table showing test operation commands transmitted to a lamp control circuit provided on a lamp control board, which is a part of a sub control board, and the contents of the operation.

FIG. 6 is a diagram showing, in a table format, test operation commands transmitted to an audio control circuit provided on an audio control board that is a part of the sub control board and the contents of the operation.

FIG. 7 is a diagram showing, in a table format, test operation commands transmitted to a display control circuit provided on a display control substrate that is a part of a sub-control substrate and their operation contents;

FIG. 8 is a block diagram corresponding to the requirements described in claim 1 of the present invention.

[Explanation of symbols]

 Reference Signs List 1 main control circuit 2 one-chip microcomputer 3 input / output circuit 4 input / output circuit 5 CPU 6 RAM 7 ROM 8 starting port sensor 9 test start switch 10 relay circuit 11 solenoid 12 count sensor 13 specific area sensor 14 lamp control circuit 15 voice control Circuit 16 Speaker 17 Payout control circuit 18 Prize ball payout device 19 Launch control circuit 20 Ball launching device 21 Special symbol display device 22 Display control circuit 23 Liquid crystal display panel

Claims (7)

[Claims] 1. A gaming device that performs an operation related to a game,
In a gaming machine having a control board for controlling the operation of the gaming machine, a test command output means for transmitting a series of test operation commands to the control board is provided, and the control board is set to a test mode. A test operation means for causing the gaming machine to perform a test operation in a predetermined manner corresponding to each of a series of test operation commands transmitted from the test command output means when the operation is shifted is provided. A gaming machine. 2. The control board is a sub-control board that controls the operation of the gaming machine in accordance with a command from a main control board that performs a main control of a game, and wherein the test command output unit controls the sub-control board. 2. The gaming machine according to claim 1, wherein the sub-control board is provided with the test mode operating means for transmitting a series of test operation commands. 3. The test command output means is included in the main control board.
A gaming machine according to claim 1. 4. The series of test operation commands are composed of bit data of at least the number of signal lines allocated to each signal line of the control board, and the content of the test operation command of the gaming machine is The gaming machine according to any one of claims 1 to 3, wherein operation is different. 5. The gaming machine according to claim 1, wherein the test operation unit does not receive the test operation command except in the test mode. 6. The gaming machine according to claim 1, wherein the control board is configured to be able to shift to the test mode only for a predetermined period. 7. The gaming machine according to claim 6, wherein the predetermined period is a period from when the power is turned on until a predetermined time elapses.