JP2002158323A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP2002158323A
JP2002158323A JP2000353064A JP2000353064A JP2002158323A JP 2002158323 A JP2002158323 A JP 2002158323A JP 2000353064 A JP2000353064 A JP 2000353064A JP 2000353064 A JP2000353064 A JP 2000353064A JP 2002158323 A JP2002158323 A JP 2002158323A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead portion
lead
electrode
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000353064A
Other languages
Japanese (ja)
Other versions
JP2002158323A5 (en
Inventor
Shinji Naito
伸二 内藤
Takashi Sato
隆史 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000353064A priority Critical patent/JP2002158323A/en
Publication of JP2002158323A publication Critical patent/JP2002158323A/en
Publication of JP2002158323A5 publication Critical patent/JP2002158323A5/ja
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a method which can thin a resin package in the heightwise direction of the resin package in a structure that a semiconductor chip is bonded to the upper surface of the uplifted inner end of a straight lead frame as the straight lead frame is used for the resin package, and to provide a semiconductor device. SOLUTION: Straight lead frames 1a and 1b of the semiconductor device, which is extendedly provided in a horizontal shape and constitutes a pair of the side of an anode and the side of a cathode are used as the lead frames for a resin package, and a semiconductor chip 2 is mounted on the inner end of the lead frame 1a. After an electrode 3 on the surface of the chip 2 and the inner end of the lead frame 1b are electrically connected with each other through an Au wire 4, the lead frames 1a and 1b, the chip 2 and the wire 4 are covered and sealed with a resin 5.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
技術および半導体装置に関し、リードフレームに半導体
チップを搭載し、その外側を封止してなる半導体装置の
製造方法および半導体装置に適用して有効な技術に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique and a semiconductor device, and more particularly to a semiconductor device manufacturing method in which a semiconductor chip is mounted on a lead frame and the outside thereof is sealed, and applied to a semiconductor device. It is about effective technology.

【０００２】[0002]

【従来の技術】近年、携帯電話をはじめとする、移動体
通信分野における電子機器は、携帯性の向上を目的とし
て、薄型化や小型・軽量化が強く求められている。ま
た、電子機器の小型・軽量化に伴い、半導体装置のパッ
ケージについても薄型化や小型・軽量化が求められてい
る。2. Description of the Related Art In recent years, there has been a strong demand for electronic devices in the field of mobile communication, such as mobile phones, to be thinner and smaller and lighter in order to improve portability. In addition, as electronic devices become smaller and lighter, semiconductor device packages are also required to be thinner and smaller and lighter.

【０００３】ところで、携帯電話をはじめとする小型の
電子機器においては、ダイオードが多数個使用される事
例が増えてきている。そのためダイオードに対しては、
パッケージ外形の薄型化および小型化が要求されてい
る。[0003] By the way, in small-sized electronic devices such as mobile phones, the use of a large number of diodes is increasing. So for diodes,
There is a demand for thinner and smaller packages.

【０００４】上記したダイオードのパッケージは、たと
えば、陽極側と陰極側とが対となったリードフレームを
用意し、ダイオード素子が形成された半導体チップの裏
面電極を、陽極側もしくは陰極側のリードフレームの内
端部（タブ）に接着し、半導体チップの表面電極と他方
のリードフレームの内端部とをＡｕ（金）ワイヤを用い
て接続し、半導体チップ、Ａｕワイヤおよびリードフレ
ームをエポキシ系のレジン材料で覆ったレジンパッケー
ジとなっている。また、半導体チップがダイオードパッ
ケージの中央付近に配置されるように、リードフレーム
の内端部を持ち上げた構造としている。In the diode package described above, for example, a lead frame in which an anode side and a cathode side are paired is prepared, and the back electrode of a semiconductor chip on which a diode element is formed is connected to the anode or cathode side lead frame. And the surface electrode of the semiconductor chip and the inner end of the other lead frame are connected to each other using an Au (gold) wire, and the semiconductor chip, the Au wire and the lead frame are epoxy-based. It is a resin package covered with resin material. Further, the inner end of the lead frame is raised so that the semiconductor chip is arranged near the center of the diode package.

【０００５】また、半導体チップとリードフレームとを
接着する蝋材は、ＡｕとＳｉ（シリコン）とからなるＡ
ｕ−Ｓｉ供晶層であり、半導体チップとリードフレーム
とを熱圧着する際に、そのＡｕ−Ｓｉ供晶層が液状化し
たものである。この蝋材の量が多いと接着強度が確保で
きるので、Ａｕからなる裏面電極の厚さを厚くしたり、
半導体チップが接着する部分のリードフレームにＡｕ箔
を載せることにより、接着強度の向上を図る場合があ
る。[0005] Further, a wax material for bonding the semiconductor chip and the lead frame is made of Au and Si (silicon).
The u-Si crystal layer, which is liquefied when the semiconductor chip and the lead frame are thermocompression bonded. If the amount of the brazing material is large, the bonding strength can be secured, so that the thickness of the back electrode made of Au can be increased,
In some cases, the Au foil is placed on the lead frame at the portion where the semiconductor chip is bonded, thereby improving the bonding strength.

【０００６】ここで、ダイオードの構造および種々のダ
イオードの機能については、たとえば、２０００年７月
２８日、株式会社工業調査会発行、「エレクトロニクス
実装大辞典」、ｐ５２２〜ｐ５２３に記載がある。Here, the structure of the diode and the functions of various diodes are described in, for example, “Electronics Packaging Dictionary”, published on July 28, 2000, by the Japan Industrial Research Association, pp. 522-523.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、上記し
たダイオードのパッケージをはじめとする従来のレジン
パッケージの構造およびその製造方法においては、以下
のような問題があることを本発明者らは見出した。However, the present inventors have found the following problems in the structure of the conventional resin package including the diode package described above and the manufacturing method thereof.

【０００８】すなわち、半導体チップを搭載したリード
フレームは、その内端部が持ち上がり、持ち上がった内
端部上面に半導体チップを搭載した構造となっているた
めに、内端部が持ち上がった分だけレジンパッケージが
高さ方向に大きくなってしまう問題がある。That is, the lead frame on which the semiconductor chip is mounted has a structure in which the inner end is lifted and the semiconductor chip is mounted on the upper surface of the lifted inner end. There is a problem that the package becomes large in the height direction.

【０００９】また、リードフレームの内端部に半導体チ
ップを搭載することから、半導体チップを搭載する領域
が狭くなり、半導体チップがその内端部からはみ出す場
合がある。そのため、その半導体チップがはみ出した部
分に応力が集中し、半導体チップとリードフレームとが
剥離してしまう問題がある。Further, since the semiconductor chip is mounted on the inner end of the lead frame, the area for mounting the semiconductor chip becomes narrower, and the semiconductor chip may protrude from the inner end. Therefore, there is a problem that stress concentrates on a portion where the semiconductor chip protrudes, and the semiconductor chip and the lead frame are separated.

【００１０】半導体チップとリードフレームとの接着部
においては、Ａｕ−Ｓｉ供晶層からなる蝋材の量が少な
いと、熱圧着の際の熱（約３５０℃程度）によってその
接着部においてボイドが発生し、半導体チップとリード
フレームとが剥離する問題がある。上記したように、Ａ
ｕからなる裏面電極の厚さを厚くすることにより、半導
体チップとリードフレームとの接着強度の向上を図った
としても、その蝋材が流れ出してしまうとボイドが発生
しやすくなり、半導体チップとリードフレームとの接着
強度が低下する場合がある。In the bonding portion between the semiconductor chip and the lead frame, if the amount of the brazing material comprising the Au-Si crystal layer is small, voids are formed in the bonding portion due to heat (about 350 ° C.) during thermocompression bonding. This causes a problem that the semiconductor chip and the lead frame are separated from each other. As mentioned above, A
Even if the thickness of the back electrode made of u is increased, the bonding strength between the semiconductor chip and the lead frame is improved, but if the wax material flows out, voids are likely to be generated, and the semiconductor chip and the lead The adhesive strength with the frame may decrease.

【００１１】また、半導体チップが接着する部分のリー
ドフレームにＡｕ箔を載せることにより半導体チップと
リードフレームとの接着強度の向上を図る技術において
は、Ａｕ箔を用いることから、レジンパッケージの製造
コストが増加するという問題がある。Further, in the technique for improving the adhesive strength between the semiconductor chip and the lead frame by mounting the Au foil on the lead frame at the portion where the semiconductor chip is bonded, the manufacturing cost of the resin package is increased because the Au foil is used. There is a problem that increases.

【００１２】本発明の目的は、レジンパッケージをその
高さ方向において薄型化する技術を提供することにあ
る。An object of the present invention is to provide a technique for reducing the thickness of a resin package in its height direction.

【００１３】また、本発明の他の目的は、半導体チップ
とリードフレームとの接着強度を向上する技術を提供す
ることにある。Another object of the present invention is to provide a technique for improving the bonding strength between a semiconductor chip and a lead frame.

【００１４】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１５】[0015]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１６】すなわち、本発明は、第１電極と第２電極
との対である第１リード部および第２リード部を有し、
前記第１リード部および前記第２リード部の少なくとも
一方は水平状に延在するリードフレームを用意する工程
と、その主面上に半導体素子および第３電極が形成され
た半導体チップを前記第１リード部の第１領域の上面に
接着する工程と、前記第３電極と前記第２リード部の第
１領域とを金属線により電気的に接続する工程と、前記
第１リード部、前記第２リード部、前記半導体チップお
よび前記金属線を封止材により封止する工程とを有する
ものである。That is, the present invention has a first lead portion and a second lead portion which are a pair of a first electrode and a second electrode,
A step of preparing a horizontally extending lead frame for at least one of the first lead portion and the second lead portion, and mounting the semiconductor chip having a semiconductor element and a third electrode formed on a main surface thereof on the first surface; Bonding the third electrode to the upper surface of the first region of the lead portion, electrically connecting the third electrode to the first region of the second lead portion by a metal wire, Sealing the lead portion, the semiconductor chip, and the metal wire with a sealing material.

【００１７】また、本発明は、第１電極と第２電極との
対である第１リード部および第２リード部を有し、前記
第１リード部および前記第２リード部が有する第１領域
が所定の高さまで持ち上がったリードフレームを用意す
る工程と、その主面上に半導体素子および第３電極が形
成された半導体チップを前記第１リード部の前記第１領
域の下面に接着する工程と、前記第３電極と前記第２リ
ード部の第１領域の下面とを金属線により電気的に接続
する工程と、前記第１リード部、前記第２リード部、前
記半導体チップおよび前記金属線を封止材により封止す
る工程とを有するものである。Further, the present invention has a first lead portion and a second lead portion which are a pair of a first electrode and a second electrode, and the first region which the first lead portion and the second lead portion have Preparing a lead frame raised to a predetermined height, and bonding a semiconductor chip having a semiconductor element and a third electrode formed on a main surface thereof to a lower surface of the first region of the first lead portion. Electrically connecting the third electrode and the lower surface of the first region of the second lead portion with a metal wire; and connecting the first lead portion, the second lead portion, the semiconductor chip, and the metal wire. Sealing with a sealing material.

【００１８】また、本発明は、第１電極と第２電極との
対である第１リード部および第２リード部を有し、前記
第１リード部および前記第２リード部の少なくとも一方
は水平状に延在するリードフレームを用意する工程と、
その主面上に半導体素子および第３電極が形成された半
導体チップを前記第１リード部の第１領域の上面に接着
する工程と、前記第３電極と前記第２リード部の第１領
域とを金属線により電気的に接続する工程と、前記第１
リード部、前記第２リード部、前記半導体チップおよび
前記金属線を封止材により封止する工程とを有し、前記
第１リード部の前記第１領域の上面は前記半導体チップ
を取り囲む突起または前記半導体チップとの接着部にお
ける凹部を有するものである。Further, the present invention has a first lead portion and a second lead portion which are a pair of a first electrode and a second electrode, and at least one of the first lead portion and the second lead portion is horizontal. Preparing a lead frame extending in a shape,
Adhering a semiconductor chip having a semiconductor element and a third electrode formed on its main surface to an upper surface of a first region of the first lead portion; Electrically connecting the first and second metal wires by a metal wire;
Sealing the lead portion, the second lead portion, the semiconductor chip, and the metal wire with a sealing material, wherein an upper surface of the first region of the first lead portion has a protrusion surrounding the semiconductor chip or The semiconductor device has a concave portion in the bonding portion with the semiconductor chip.

【００１９】また、本発明は、第１電極と第２電極との
対である第１リード部および第２リード部を有し、前記
第１リード部および前記第２リード部が有する第１領域
が所定の高さまで持ち上がったリードフレームを用意す
る工程と、その主面上に半導体素子および第３電極が形
成された半導体チップを前記第１リード部の前記第１領
域の下面に接着する工程と、前記第３電極と前記第２リ
ード部の前記第１領域の下面とを金属線により電気的に
接続する工程と、前記第１リード部、前記第２リード
部、前記半導体チップおよび前記金属線を封止材により
封止する工程とを有し、前記第１リード部の前記第１領
域の下面は前記半導体チップを取り囲む突起または前記
半導体チップとの接着部における凹部を有するものであ
る。Further, the present invention has a first lead portion and a second lead portion which are a pair of a first electrode and a second electrode, and the first region which the first lead portion and the second lead portion have Preparing a lead frame raised to a predetermined height, and bonding a semiconductor chip having a semiconductor element and a third electrode formed on a main surface thereof to a lower surface of the first region of the first lead portion. Electrically connecting the third electrode and the lower surface of the first region of the second lead portion by a metal wire; and forming the first lead portion, the second lead portion, the semiconductor chip, and the metal wire. And a step of sealing the semiconductor chip with a sealing material, wherein the lower surface of the first region of the first lead portion has a projection surrounding the semiconductor chip or a concave portion in a bonding portion with the semiconductor chip.

【００２０】また、本発明は、第１電極と第２電極との
対である第１リード部および第２リード部を有し、前記
第１リード部および前記第２リード部の少なくとも一方
は水平状に延在するリードフレームを用意する工程と、
その主面上に半導体素子および第３電極が形成された半
導体チップを前記第１リード部の第１領域の上面に接着
する工程と、前記第３電極と前記第２リード部の第１領
域とを金属線により電気的に接続する工程と、前記第１
リード部、前記第２リード部、前記半導体チップおよび
前記金属線を封止材により封止する工程とを有し、前記
リードフレームは前記封止材との界面において凹凸部を
有するものである。Further, the present invention has a first lead portion and a second lead portion which are a pair of a first electrode and a second electrode, and at least one of the first lead portion and the second lead portion is horizontal. Preparing a lead frame extending in a shape,
Adhering a semiconductor chip having a semiconductor element and a third electrode formed on its main surface to an upper surface of a first region of the first lead portion; Electrically connecting the first and second metal wires by a metal wire;
Sealing the lead portion, the second lead portion, the semiconductor chip and the metal wire with a sealing material, wherein the lead frame has an uneven portion at an interface with the sealing material.

【００２１】また、本発明は、第１電極と第２電極との
対である第１リード部および第２リード部を有し、前記
第１リード部および前記第２リード部が有する第１領域
が所定の高さまで持ち上がったリードフレームを用意す
る工程と、その主面上に半導体素子および第３電極が形
成された半導体チップを前記第１リード部の前記第１領
域の下面に接着する工程と、前記第３電極と前記第２リ
ード部の前記第１領域の下面とを金属線により電気的に
接続する工程と、前記第１リード部、前記第２リード
部、前記半導体チップおよび前記金属線を封止材により
封止する工程とを有し、前記リードフレームは前記封止
材との界面において凹凸部を有するものである。Further, the present invention has a first lead portion and a second lead portion which are a pair of a first electrode and a second electrode, and the first region which the first lead portion and the second lead portion have Preparing a lead frame raised to a predetermined height, and bonding a semiconductor chip having a semiconductor element and a third electrode formed on a main surface thereof to a lower surface of the first region of the first lead portion. Electrically connecting the third electrode and the lower surface of the first region of the second lead portion by a metal wire; and forming the first lead portion, the second lead portion, the semiconductor chip, and the metal wire. With a sealing material, and the lead frame has an uneven portion at an interface with the sealing material.

【００２２】また、本発明は、（ａ）第１電極と第２電
極との対であり、少なくとも一方は水平状に延在する第
１リード部および第２リード部と、（ｂ）その主面上に
半導体素子および第３電極が形成され、前記第１リード
部の第１領域の上面に搭載された半導体チップと、
（ｃ）前記第３電極と前記第２リード部の前記第１領域
とを電気的に接続する金属線とを有し、前記第１リード
部、前記第２リード部、前記半導体チップおよび前記金
属線は封止材により封止されているものである。Also, the present invention provides (a) a pair of a first electrode and a second electrode, at least one of which is a first lead portion and a second lead portion extending horizontally, and (b) a first lead portion and a second lead portion. A semiconductor chip having a semiconductor element and a third electrode formed on a surface thereof and mounted on an upper surface of a first region of the first lead portion;
(C) a metal wire for electrically connecting the third electrode to the first region of the second lead portion, wherein the first lead portion, the second lead portion, the semiconductor chip, and the metal The wire is sealed with a sealing material.

【００２３】また、本発明は、（ａ）第１電極と第２電
極との対であり、第１領域が所定の高さまで持ち上がっ
た第１リード部および第２リード部と、（ｂ）その主面
上に半導体素子および第３電極が形成され、前記第１リ
ード部の前記第１領域の下面に接着された半導体チップ
と、（ｃ）前記第３電極と前記第２リード部の前記第１
領域の下面とを電気的に接続する金属線とを有し、前記
第１リード部、前記第２リード部、前記半導体チップお
よび前記金属線は封止材により封止されているものであ
る。The present invention also provides (a) a pair of a first electrode and a second electrode, wherein the first region and the second region have a first region lifted to a predetermined height; A semiconductor chip having a semiconductor element and a third electrode formed on the main surface and bonded to a lower surface of the first region of the first lead portion; and (c) the third electrode and the third electrode of the second lead portion. 1
And a metal line electrically connecting the lower surface of the region to the first lead portion, the second lead portion, the semiconductor chip, and the metal wire.

【００２４】上記の本発明によれば、半導体装置のリー
ドフレームとして、第１リード部および第２リード部の
少なくとも一方は水平状に延在するストレートリードフ
レームを用いるので、第１リード部および第２リード部
の第一領域を持ち上げ、その持ち上げた第一領域の上面
に半導体チップを接着した構造の場合より半導体装置を
高さ方向で薄型化することが可能となる。According to the present invention, as the lead frame of the semiconductor device, at least one of the first lead portion and the second lead portion uses a straight lead frame extending in a horizontal direction. It is possible to make the semiconductor device thinner in the height direction than in a structure in which the first region of the two lead portions is lifted and a semiconductor chip is bonded to the upper surface of the raised first region.

【００２５】また、上記の本発明によれば、半導体装置
のリードフレームとして、第１リード部および第２リー
ド部の少なくとも一方は水平状に延在するストレートリ
ードフレームを用いるので、第１リード部の第一領域の
上面に半導体チップを搭載する領域を十分に確保するこ
とが可能となる。According to the present invention, since at least one of the first lead portion and the second lead portion uses a straight lead frame extending horizontally, the first lead portion is used as the lead frame of the semiconductor device. It is possible to secure a sufficient area for mounting the semiconductor chip on the upper surface of the first area.

【００２６】また、上記の本発明によれば、第１リード
部の第一領域の上面に半導体チップを搭載する領域を十
分に確保することができるので、半導体チップとリード
フレームとが剥離することを防ぐことが可能となる。Further, according to the present invention, a region for mounting the semiconductor chip can be sufficiently secured on the upper surface of the first region of the first lead portion, so that the semiconductor chip and the lead frame can be separated. Can be prevented.

【００２７】また、上記の本発明によれば、第１リード
部は半導体チップを取り囲む枠状の突起、または半導体
チップとの接着部における凹部を有するので、リードフ
レームと半導体チップとを接着する蝋材が、その接着部
より流れ出してしまうことを防ぐことが可能となる。Further, according to the present invention, since the first lead portion has a frame-shaped projection surrounding the semiconductor chip or a concave portion in the bonding portion with the semiconductor chip, the first lead portion has a wax for bonding the lead frame and the semiconductor chip. It is possible to prevent the material from flowing out of the bonding portion.

【００２８】また、上記の本発明によれば、リードフレ
ームと半導体チップとを接着する蝋材が、その接着部よ
り流れ出してしまうことを防ぐことができるので、リー
ドフレームと半導体チップとの接着強度を向上すること
が可能となる。Further, according to the present invention, since the brazing material for bonding the lead frame and the semiconductor chip can be prevented from flowing out from the bonding portion, the bonding strength between the lead frame and the semiconductor chip can be prevented. Can be improved.

【００２９】また、上記の本発明によれば、第１リード
部および第２リード部が有する第１領域が所定の高さま
で持ち上がったリードフレームを用い、半導体チップを
第１リード部の第１領域の下面に接着するので、第１リ
ード部および第２リード部の第１領域を持ち上げ、その
持ち上げた第１領域の上面に半導体チップを接着した構
造の場合より、半導体装置を高さ方向で薄型化すること
が可能となる。Further, according to the present invention, a semiconductor chip is mounted on a first region of a first lead portion by using a lead frame in which a first region of a first lead portion and a second lead portion is raised to a predetermined height. The semiconductor device is thinner in the height direction than in the structure in which the first regions of the first lead portion and the second lead portion are lifted, and the semiconductor chip is bonded to the upper surface of the lifted first region. Can be realized.

【００３０】また、上記の本発明によれば、リードフレ
ームの表面に凹凸をつけ、リードフレームと封止材との
接触面積を増加させるので、リードフレームと封止材と
の密着性を向上することが可能となる。According to the present invention, the surface of the lead frame is made uneven so that the contact area between the lead frame and the sealing material is increased, so that the adhesion between the lead frame and the sealing material is improved. It becomes possible.

【００３１】[0031]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。なお、実施の形態を説明す
るための全図において、同一の機能を有する部材には同
一の符号を付し、その繰り返しの説明は省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

【００３２】（実施の形態１）図１は、本実施の形態１
の半導体装置であるレジンパッケージの一例を示す断面
図である。(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
FIG. 3 is a cross-sectional view illustrating an example of a resin package as the semiconductor device of FIG.

【００３３】このレジンパッケージは、水平状に延在
し、かつ陽極（第１電極もしくは第２電極）と陰極（第
１電極もしくは第２電極）との対であるストレートリー
ドフレーム（リードフレーム１ａ（第１リード部）、１
ｂ（第２リード部））の陽極側もしくは陰極側（リード
フレーム１ａ）の内端部（第１領域）の上面に、半導体
素子の形成された半導体チップ２の裏面電極（図示は省
略）が接着され、リードフレーム１ｂの内端部（第１領
域）と半導体チップ２の表面電極（第３電極）３とがＡ
ｕワイヤ（金属線）４により電気的に接続され、リード
フレーム１ａ、１ｂ、半導体チップ２およびＡｕワイヤ
４をエポキシ系のレジン（封止材）５で覆った構造とな
っている。リードフレーム１ａ、１ｂは、たとえばＣｕ
（銅）からなり、その表面にはＡｇ（銀）膜がめっき法
にて形成されている。半導体チップ２の裏面電極は、た
とえばＡｕまたはＡｕ／ＡｕＳｂ（アンチモン）からな
る積層膜で構成されている。また、レジンパッケージの
裏面には、レジンパッケージの実装時においてリードフ
レーム１ａ、１ｂからの電気の漏れを防ぐ目的で、たと
えばポリイミドなどからなる絶縁層６が形成されてい
る。This resin package extends horizontally and is a pair of an anode (first or second electrode) and a cathode (first or second electrode). 1st lead part), 1
The back electrode (not shown) of the semiconductor chip 2 on which the semiconductor element is formed is formed on the upper surface of the inner end (first region) on the anode side or the cathode side (lead frame 1a) of the b (second lead portion)). The inner end (first region) of the lead frame 1b and the surface electrode (third electrode) 3 of the semiconductor chip 2 are A
It is electrically connected by u wires (metal wires) 4, and has a structure in which the lead frames 1a and 1b, the semiconductor chip 2 and the Au wires 4 are covered with an epoxy resin (sealing material) 5. The lead frames 1a and 1b are made of, for example, Cu
(Copper), and an Ag (silver) film is formed on the surface thereof by a plating method. The back electrode of the semiconductor chip 2 is formed of a laminated film made of, for example, Au or Au / AuSb (antimony). An insulating layer 6 made of, for example, polyimide is formed on the back surface of the resin package for the purpose of preventing leakage of electricity from the lead frames 1a and 1b when the resin package is mounted.

【００３４】本実施の形態１のレジンパッケージにおい
ては、リードフレーム１ａ、１ｂとしてストレートリー
ドフレームを用いているので、リードフレーム１ａ、１
ｂの内端部を持ち上げ、その持ち上げた内端部上面に半
導体チップ２を接着した構造の場合よりも、レジンパッ
ケージをその高さ方向で薄型化することができる。本発
明者らの行った実験によれば、リードフレーム１ａ、１
ｂの内端部を持ち上げ、その持ち上げた内端部上面に半
導体チップ２を接着した構造の場合においては、レジン
パッケージの高さは約５５０μｍ程度であったが、リー
ドフレーム１ａ、１ｂとしてストレートリードフレーム
を用いた本実施の形態１のレジンパッケージは、その高
さが約４００μｍ〜４５０μｍ程度となり、リードフレ
ーム１ａ、１ｂの内端部を持ち上げ、その持ち上げた内
端部上面に半導体チップ２を接着した構造と比べて、約
１００μｍ〜１５０μｍ程度薄型化することができるこ
とがわかった。すなわち、本実施の形態１のレジンパッ
ケージを移動体通信分野にて用いた場合には、通信機器
の携帯性を向上することが可能となる。In the resin package of the first embodiment, since straight lead frames are used as the lead frames 1a and 1b, the lead frames 1a and 1b
The resin package can be made thinner in the height direction than in the case where the inner end of b is lifted and the semiconductor chip 2 is bonded to the upper surface of the raised inner end. According to experiments conducted by the present inventors, the lead frames 1a, 1a
In the case of a structure in which the semiconductor chip 2 is bonded to the upper surface of the lifted inner end, and the height of the resin package is about 550 μm, the lead frames 1a and 1b are straight leads. The resin package of the first embodiment using the frame has a height of about 400 μm to 450 μm, lifts the inner ends of the lead frames 1 a and 1 b, and adheres the semiconductor chip 2 to the upper surface of the lifted inner ends. It has been found that the thickness can be reduced by about 100 μm to 150 μm as compared with the above structure. That is, when the resin package of the first embodiment is used in the mobile communication field, the portability of the communication device can be improved.

【００３５】また、リードフレーム１ａの内端部を持ち
上げ、その持ち上げた内端部上面に半導体チップ２を接
着した構造とした場合においては、半導体チップ２を搭
載する領域が狭くなり、半導体チップ２がその内端部か
らはみ出し、半導体チップ２がはみ出した部分に応力が
集中し、半導体チップ２とリードフレーム１ａとが剥離
してしまう場合があった。本実施の形態１においては、
リードフレーム１ａとしてストレートリードフレームを
用いていることから、半導体チップ２を搭載する領域を
十分に確保することができるので、半導体チップ２がリ
ードフレーム１ａの内端部からはみ出すことを防ぐこと
ができる。すなわち、半導体チップ２とリードフレーム
１ａとが剥離することを防ぐことができる。さらに、半
導体チップ２とリードフレーム１ａとが剥離することを
防ぐことができることから、本実施の形態１のレジンパ
ッケージの歩留りを向上することができる。In the case where the inner end of the lead frame 1a is lifted and the semiconductor chip 2 is bonded to the upper surface of the lifted inner end, the area for mounting the semiconductor chip 2 becomes smaller, and the semiconductor chip 2 However, there is a case where the semiconductor chip 2 protrudes from the inner end thereof, stress is concentrated on a portion where the semiconductor chip 2 protrudes, and the semiconductor chip 2 and the lead frame 1a are separated. In the first embodiment,
Since a straight lead frame is used as the lead frame 1a, a sufficient area for mounting the semiconductor chip 2 can be secured, so that the semiconductor chip 2 can be prevented from protruding from the inner end of the lead frame 1a. . That is, separation of the semiconductor chip 2 and the lead frame 1a can be prevented. Further, since the semiconductor chip 2 and the lead frame 1a can be prevented from being separated from each other, the yield of the resin package of the first embodiment can be improved.

【００３６】図２（ａ）、（ｂ）は、それぞれ図１に示
した本実施の形態１のレジンパッケージのリードフレー
ム１ａ、１ｂと半導体チップ２との接着部付近を拡大し
て示した平面図および断面図であり、図２（ｂ）は図２
（ａ）中のＡ−Ａ線における断面図である。FIGS. 2A and 2B are enlarged plan views showing the vicinity of the bonding portion between the lead frames 1a and 1b of the resin package of the first embodiment shown in FIG. 1 and the semiconductor chip 2, respectively. FIG. 2B is a diagram and a sectional view, and FIG.
It is sectional drawing in the AA line in (a).

【００３７】図２に示すように、半導体チップ２が搭載
されるリードフレーム１ａには、半導体チップ２を取り
囲む枠状の突起７が形成されている。この突起７の高さ
は、半導体チップ２の高さが約１２０μｍ程度の場合に
おいて、約５μｍ〜２０μｍ程度、好ましくは約１０μ
ｍ程度とすることを例示できる。リードフレーム１ａと
半導体チップ２とは、Ａｕ−Ｓｉ供晶層からなる蝋材８
により接着されているが、その突起７を設けることによ
り、リードフレーム１ａと半導体チップ２との接着部か
ら蝋材８が流れ出してしまうことを防ぐことができる。
その結果、リードフレーム１と半導体チップ２との接着
強度を向上することが可能となる。As shown in FIG. 2, a frame-shaped projection 7 surrounding the semiconductor chip 2 is formed on the lead frame 1a on which the semiconductor chip 2 is mounted. The height of the protrusion 7 is about 5 μm to 20 μm, preferably about 10 μm when the height of the semiconductor chip 2 is about 120 μm.
m can be exemplified. The lead frame 1a and the semiconductor chip 2 are made of a brazing material 8 made of an Au-Si crystal layer.
By providing the projections 7, it is possible to prevent the wax material 8 from flowing out from the bonding portion between the lead frame 1a and the semiconductor chip 2.
As a result, the bonding strength between the lead frame 1 and the semiconductor chip 2 can be improved.

【００３８】図２に示した突起７の代わりに、図３
（ａ）、（ｂ）に示すような凹部９を形成してもよい。
この時、凹部９の深さは、上記した突起７の高さの場合
と同様に、半導体チップ２の高さが約１２０μｍ程度の
場合において、約５μｍ〜２０μｍ程度、好ましくは約
１０μｍ程度とすることを例示できる。凹部９を設ける
ことにより、突起７を設けた場合と同様に、リードフレ
ーム１ａと半導体チップ２との接着部から蝋材８が流れ
出してしまうことを防ぐことができる。その結果、リー
ドフレーム１ａと半導体チップ２との接着強度を向上す
ることが可能となる。Instead of the projection 7 shown in FIG.
A concave portion 9 as shown in (a) and (b) may be formed.
At this time, the depth of the recess 9 is about 5 μm to 20 μm, preferably about 10 μm when the height of the semiconductor chip 2 is about 120 μm, as in the case of the height of the projection 7 described above. This can be exemplified. By providing the concave portion 9, it is possible to prevent the wax material 8 from flowing out from the bonding portion between the lead frame 1 a and the semiconductor chip 2, similarly to the case where the projection 7 is provided. As a result, the bonding strength between the lead frame 1a and the semiconductor chip 2 can be improved.

【００３９】なお、上記した突起７および凹部９は、リ
ードフレーム１ａの製造（加工）時において、プレス機
で押すことにより形成することができる。The above-mentioned projections 7 and recesses 9 can be formed by pressing with a press during the manufacture (working) of the lead frame 1a.

【００４０】また、リードフレーム１ａ、１ｂの表面に
は、突起７または凹部９とは別個に凹凸をつけた形状と
してもよい。リードフレーム１ａ、１ｂの表面に凹凸を
つけた形状とすることにより、リードフレーム１ａ、１
ｂの表面積が増加する。リードフレーム１ａ、１ｂの表
面積が増加することに伴って、リードフレーム１ａ、１
ｂとレジン５との接触面積も増加する。その結果、リー
ドフレーム１ａ、１ｂとレジン５との密着性を向上する
ことができる。The surfaces of the lead frames 1a and 1b may be provided with irregularities separately from the projections 7 or the recesses 9. By making the surfaces of the lead frames 1a and 1b uneven, the lead frames 1a and 1b
The surface area of b increases. As the surface area of the lead frames 1a, 1b increases, the lead frames 1a, 1b
The contact area between b and the resin 5 also increases. As a result, the adhesion between the lead frames 1a and 1b and the resin 5 can be improved.

【００４１】次に、図４〜図６に従って、本実施の形態
１の半導体装置であるレジンパッケージの製造方法を、
その工程順に説明する。Next, referring to FIGS. 4 to 6, a method of manufacturing a resin package which is the semiconductor device of the first embodiment will be described.
The description will be made in the order of the steps.

【００４２】まず、図４に示すように、図２または図３
を用いて前述した突起７（図示は省略）または凹部９
（図示は省略）が、陽極側もしくは陰極側の一方に形成
されたストレートリードフレーム（リードフレーム１
ａ、１ｂ）を用意する。First, as shown in FIG. 4, FIG.
The protrusion 7 (not shown) or the concave portion 9 described above is used.
(Not shown) is a straight lead frame (lead frame 1) formed on one of the anode side and the cathode side.
a, 1b) are prepared.

【００４３】続いて、枠状の突起７の内側または凹部９
内に、Ａｕ−Ｓｉ供晶層からなる蝋材８（図示は省略）
によって半導体チップ２を接着することにより、リード
フレーム１ａとＡｕ系金属からなる半導体チップ２の裏
面電極（図示は省略）とを電気的に接続する。Subsequently, the inside of the frame-shaped projection 7 or the recess 9
Inside, a brazing material 8 composed of an Au-Si crystal layer (not shown)
By bonding the semiconductor chip 2 to the lead frame 1a, a back electrode (not shown) of the semiconductor chip 2 made of an Au-based metal is electrically connected.

【００４４】次に、図５に示すように、半導体チップ２
に形成された表面電極３と半導体チップ２が接着された
リードフレーム１ａの対極側のリードフレーム１ｂと
を、たとえばＡｕワイヤ４を介して電気的に接続する。Next, as shown in FIG.
Is electrically connected, for example, via an Au wire 4 to a lead frame 1b opposite to the lead frame 1a to which the semiconductor chip 2 is bonded.

【００４５】次に、図６に示すように、リードフレーム
１ａ、１ｂ、半導体チップ２およびＡｕワイヤ４を、た
とえばレジン５により封止することにより、リードフレ
ーム１ａ、１ｂの外端部を実装用に外部に露出させたレ
ジンパッケージを形成する。この時、レジン５の外周面
には、カラーバンド等の極性識別マーク（図示は省略）
が形成される。Next, as shown in FIG. 6, the lead frames 1a and 1b, the semiconductor chip 2 and the Au wires 4 are sealed with, for example, a resin 5 so that the outer ends of the lead frames 1a and 1b are mounted. Then, a resin package exposed to the outside is formed. At this time, a polarity identification mark such as a color band (not shown) is provided on the outer peripheral surface of the resin 5.
Is formed.

【００４６】続いて、上記したレジンパッケージの下面
に、たとえばポリイミドなどからなる絶縁層６を形成す
ることにより、図１に示した本実施の形態１のレジンパ
ッケージを製造する。絶縁層６の膜厚は、たとえば数μ
ｍ程度とすることを例示できる。なお、実装時におい
て、リードフレーム１ａ、１ｂの外端部にて実装基板と
のコンタクトを取らずに、リードフレーム１ａ、１ｂの
内端部の下面にて実装基板とのコンタクトを取る場合
や、実装基板の実装面に絶縁フィルムが形成されている
場合などには絶縁層８の形成を省略することができる。
また、絶縁層８を形成しない場合においては、本実施の
形態１のレジンパッケージの製造工程数を減少すること
ができる。Subsequently, an insulating layer 6 made of, for example, polyimide is formed on the lower surface of the above-mentioned resin package, thereby manufacturing the resin package of the first embodiment shown in FIG. The thickness of the insulating layer 6 is, for example, several μm.
m can be exemplified. When mounting, the outer frame of the lead frames 1a, 1b does not contact the mounting substrate, but the lower frame of the inner edge of the lead frame 1a, 1b contacts the mounting substrate. In the case where an insulating film is formed on the mounting surface of the mounting board, the formation of the insulating layer 8 can be omitted.
Further, when the insulating layer 8 is not formed, the number of manufacturing steps of the resin package of the first embodiment can be reduced.

【００４７】上記した本実施の形態１のレジンパッケー
ジの製造方法によれば、リードフレーム１ａ、１ｂの内
端部を持ち上げ、その持ち上げたリードフレーム１ａの
内端部上面に半導体チップ２を搭載した構造の場合のレ
ジンパッケージの製造時に用いられる製造方法および製
造装置をそのまま利用することができる。すなわち、新
たなレジンパッケージの製造方法または製造装置を導入
する必要がないので、本実施の形態１のレジンパッケー
ジの製造コストの上昇を抑制することが可能となる。According to the resin package manufacturing method of the first embodiment, the inner ends of the lead frames 1a and 1b are lifted, and the semiconductor chip 2 is mounted on the upper surface of the lifted inner end of the lead frame 1a. The manufacturing method and the manufacturing apparatus used when manufacturing the resin package having the structure can be used as they are. That is, since it is not necessary to introduce a new resin package manufacturing method or manufacturing apparatus, it is possible to suppress an increase in the manufacturing cost of the resin package of the first embodiment.

【００４８】ところで、上記したリードフレーム１ｂの
形状については、図７に示すように、その内端部を半導
体チップ２の上面と略同一高さまで持ち上げた構造とし
てもよい。それにより、本実施の形態１のレジンパッケ
ージを高さ方向で大きくすることなく、半導体チップ２
の表面電極３とリードフレーム１ｂの内端部とを電気的
に接続するＡｕワイヤ４を短くすることができる。Ａｕ
ワイヤ４を短くできることにより、本実施の形態１のレ
ジンパッケージの高周波特性などの電気的特性が劣化す
ることを防ぐことが可能となる。The shape of the lead frame 1b may be such that its inner end is raised to substantially the same height as the upper surface of the semiconductor chip 2, as shown in FIG. Thereby, the semiconductor chip 2 can be formed without increasing the resin package of the first embodiment in the height direction.
The Au wire 4 for electrically connecting the surface electrode 3 and the inner end of the lead frame 1b can be shortened. Au
Since the wire 4 can be shortened, it is possible to prevent the electrical characteristics such as the high-frequency characteristics of the resin package of the first embodiment from deteriorating.

【００４９】（実施の形態２）図８は、本実施の形態２
の半導体装置であるレジンパッケージの一例を示す断面
図である。(Embodiment 2) FIG. 8 shows Embodiment 2 of the present invention.
FIG. 3 is a cross-sectional view illustrating an example of a resin package as the semiconductor device of FIG.

【００５０】本実施の形態２のレジンパッケージは、前
記実施の形態１にて図１〜図３を用いて説明したリード
フレーム１ａ（第１リード部）、１ｂ（第２リード部）
の内端部を持ち上げ、リードフレーム１ａの内端部（第
１領域）の下面に半導体チップ２の裏面を接着し、半導
体チップ２の表面電極とリードフレーム１ｂの内端部
（第１領域）とをＡｕワイヤ４を介して電気的に接続し
た構造とすることによりレジンパッケージの高さ方向で
の薄型化を図ったものである。その他の部品の材質およ
び構造については前記実施の形態１のレジンパッケージ
と同一であるので、それら同一の材質および構造につい
ては説明を省略する。The resin package of the second embodiment has the lead frames 1a (first lead) and 1b (second lead) described in the first embodiment with reference to FIGS.
And the back surface of the semiconductor chip 2 is adhered to the lower surface of the inner end portion (first region) of the lead frame 1a, and the surface electrode of the semiconductor chip 2 and the inner end portion of the lead frame 1b (first region). Are electrically connected to each other through the Au wire 4 to reduce the thickness of the resin package in the height direction. Since the materials and structures of the other components are the same as those of the resin package of the first embodiment, the description of the same materials and structures will be omitted.

【００５１】図８に示すように、本実施の形態２のレジ
ンパッケージは、リードフレーム１ａ、１ｂの内端部が
レジンパッケージの上面１０（絶縁層６）まで持ち上が
り、リードフレーム１ａの内端部下面に半導体チップ２
を接着した構造となっている。そのため、本実施の形態
２のレジンパッケージは、リードフレーム１ａ、１ｂの
内端部を持ち上げ、その持ち上げた内端部上面に半導体
チップ２を接着した構造の場合よりも、レジンパッケー
ジをその高さ方向で薄型化することができる。本発明者
らの行った実験によれば、本実施の形態２のレジンパッ
ケージは、前記実施の形態１のレジンパッケージと同様
に、その高さが約４００μｍ〜４５０μｍ程度とするこ
とができ、リードフレーム１ａ、１ｂの内端部を持ち上
げ、その持ち上げた内端部上面に半導体チップ２を接着
した構造と比べて、約１００μｍ〜１５０μｍ程度薄型
化することができることがわかった。すなわち、本実施
の形態２のレジンパッケージを移動体通信分野にて用い
た場合には、前記実施の形態１のレジンパッケージを用
いた場合と同様に、通信機器の携帯性を向上することが
可能となる。As shown in FIG. 8, in the resin package according to the second embodiment, the inner ends of the lead frames 1a and 1b are lifted up to the upper surface 10 (insulating layer 6) of the resin package, and the inner end of the lead frame 1a is lifted. Semiconductor chip 2 on the bottom
Are bonded. Therefore, the resin package according to the second embodiment has a higher height than the resin package having a structure in which the inner ends of the lead frames 1a and 1b are lifted and the semiconductor chip 2 is bonded to the upper surface of the lifted inner ends. The thickness can be reduced in the direction. According to experiments performed by the present inventors, the resin package of the second embodiment can have a height of about 400 μm to 450 μm, similar to the resin package of the first embodiment, It has been found that the thickness can be reduced by about 100 μm to 150 μm as compared with a structure in which the inner ends of the frames 1 a and 1 b are lifted and the semiconductor chip 2 is bonded to the upper surface of the lifted inner ends. That is, when the resin package of the second embodiment is used in the mobile communication field, the portability of the communication device can be improved as in the case of using the resin package of the first embodiment. Becomes

【００５２】次に、図９〜図１１に従って、本実施の形
態１の半導体装置であるレジンパッケージの製造方法
を、その工程順に説明する。Next, a method of manufacturing a resin package which is a semiconductor device of the first embodiment will be described in the order of steps with reference to FIGS.

【００５３】まず、図９に示すように、陽極側と陰極側
とが対になったリードフレーム１ａ、１ｂを用意する。
このリードフレーム１ａ、１ｂは、図８を用いて説明し
たように、レジン５によって封止後には、その内端部が
レジンパッケージの上面に達するようにあらかじめ加工
されたものとする。また、リードフレーム１ａの内端部
下面には、前記実施の形態１において図２または図３を
用いて説明した突起７または凹部９と同様の枠状の突起
または凹部が形成されているものとする。この突起また
は凹部によって、次の工程においてリードフレーム１ａ
と半導体チップ２とを接着する蝋材が、その接着部から
流れ出してしまうことを防ぐことができる。First, as shown in FIG. 9, lead frames 1a and 1b having a pair of an anode and a cathode are prepared.
As described with reference to FIG. 8, the lead frames 1a and 1b are pre-processed such that the inner ends thereof reach the upper surface of the resin package after being sealed by the resin 5. Further, a frame-shaped projection or a recess similar to the projection 7 or the recess 9 described with reference to FIG. 2 or 3 in the first embodiment is formed on the lower surface of the inner end portion of the lead frame 1a. I do. In the next step, the lead frame 1a
It can be prevented that the brazing material for bonding the semiconductor chip 2 to the semiconductor chip 2 flows out from the bonding portion.

【００５４】続いて、上記した枠状の突起の内側または
凹部内に、前記実施の形態１において図２および図３を
用いて説明した、Ａｕ−Ｓｉ供晶層からなる蝋材８と同
様の蝋材によって半導体チップ２を接着することによ
り、リードフレーム１ａとＡｕ系金属からなる半導体チ
ップ２の裏面電極（図示は省略）とを電気的に接続す
る。Subsequently, the same as the brazing material 8 made of the Au-Si crystal layer described in the first embodiment with reference to FIGS. By bonding the semiconductor chip 2 with a brazing material, the lead frame 1a and the back electrode (not shown) of the semiconductor chip 2 made of Au-based metal are electrically connected.

【００５５】次に、図１０に示すように、半導体チップ
２に形成された表面電極（第３電極）３とリードフレー
ム１ｂの内端部下面とを、たとえばＡｕワイヤ４を介し
て電気的に接続する。Next, as shown in FIG. 10, the surface electrode (third electrode) 3 formed on the semiconductor chip 2 and the lower surface of the inner end of the lead frame 1b are electrically connected via, for example, Au wires 4. Connecting.

【００５６】次に、図１１に示すように、リードフレー
ム１ａ、１ｂ、半導体チップ２およびＡｕワイヤ（金属
線）４を、たとえばレジン（封止材）５により封止する
ことにより、リードフレーム１ａ、１ｂの外端部を実装
用に外部に露出させたレジンパッケージを形成する。こ
の時、リードフレーム１ａの内端部上面はレジン５から
露出し、レジン５の外周面には、カラーバンド等の極性
識別マーク（図示は省略）が形成される。Next, as shown in FIG. 11, the lead frame 1a, 1b, the semiconductor chip 2, and the Au wire (metal wire) 4 are sealed with, for example, a resin (sealing material) 5, so that the lead frame 1a 1b, a resin package having the outer end exposed outside for mounting. At this time, the upper surface of the inner end of the lead frame 1a is exposed from the resin 5, and a polarity identification mark (not shown) such as a color band is formed on the outer peripheral surface of the resin 5.

【００５７】続いて、上記したレジンパッケージの上面
に、たとえばポリイミドなどからなる絶縁層６を形成す
ることにより、図８に示した本実施の形態２のレジンパ
ッケージを製造する。絶縁層６の膜厚は、前記実施の形
態１における絶縁層６と同様に、たとえば数μｍ程度と
することを例示できる。本実施の形態２において、絶縁
層６は、前記実施の形態１における絶縁層６と同様に、
レジンパッケージの実装時においてリードフレーム１
ａ、１ｂからの電気の漏れを防ぐ目的で形成する。Subsequently, an insulating layer 6 made of, for example, polyimide or the like is formed on the upper surface of the resin package, thereby manufacturing the resin package of the second embodiment shown in FIG. As in the case of the insulating layer 6 in the first embodiment, the thickness of the insulating layer 6 may be, for example, about several μm. In the second embodiment, the insulating layer 6 is similar to the insulating layer 6 in the first embodiment.
Lead frame 1 when mounting resin package
It is formed for the purpose of preventing leakage of electricity from a and 1b.

【００５８】上記した本実施の形態２のレジンパッケー
ジの製造方法によれば、前記実施の形態１のレジンパッ
ケージの製造方法と同様に、リードフレーム１ａ、１ｂ
の内端部を持ち上げ、その持ち上げたリードフレーム１
ａの内端部上面に半導体チップ２を搭載した構造の場合
のレジンパッケージの製造時に用いられる製造方法およ
び製造装置をそのまま利用することができる。すなわ
ち、新たなレジンパッケージの製造方法または製造装置
を導入する必要がないので、前記実施の形態１と同様に
本実施の形態２のレジンパッケージの製造コストの上昇
を抑制することが可能となる。According to the resin package manufacturing method of the second embodiment, the lead frames 1a and 1b are similar to the resin package manufacturing method of the first embodiment.
Of the lead frame 1
The manufacturing method and the manufacturing apparatus used when manufacturing the resin package in the case of the structure in which the semiconductor chip 2 is mounted on the upper surface of the inner end of “a” can be used as they are. That is, since it is not necessary to introduce a new resin package manufacturing method or manufacturing apparatus, it is possible to suppress an increase in the manufacturing cost of the resin package of the second embodiment as in the first embodiment.

【００５９】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲で種々変更可能であることは言うまでも
ない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

【００６０】[0060]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば以
下の通りである。 （１）本発明によれば、レジンパッケージのリードフレ
ームとしてストレートリードフレームを用いるので、リ
ードフレームの内端部を持ち上げ、その持ち上げた内端
部上面に半導体チップを接着した構造の場合よりレジン
パッケージを高さ方向で薄型化することができる。 （２）本発明によれば、レジンパッケージのリードフレ
ームとしてストレートリードフレームを用いるので、リ
ードフレーム上に半導体チップを搭載する領域を十分に
確保することができる。 （３）本発明によれば、リードフレーム上に半導体チッ
プを搭載する領域を十分に確保することができるので、
半導体チップとリードフレームとが剥離することを防ぐ
ことができる。 （４）本発明によれば、リードフレームは半導体チップ
を取り囲む枠状の突起、または半導体チップとの接着部
における凹部を有するので、リードフレームと半導体チ
ップとを接着する蝋材が、その接着部より流れ出してし
まうことを防ぐことができる。 （５）本発明によれば、リードフレームと半導体チップ
とを接着する蝋材が、その接着部より流れ出してしまう
ことを防ぐことができるので、リードフレームと半導体
チップとの接着強度を向上することができる。 （６）本発明によれば、レジンパッケージのリードフレ
ームの内端部をレジンパッケージの上面まで持ち上げ、
リードフレームの内端部下面に半導体チップを接着する
ので、リードフレームの内端部を持ち上げ、その持ち上
げた内端部上面に半導体チップを接着した構造の場合よ
りレジンパッケージを高さ方向で薄型化することができ
る。 （７）本発明によれば、リードフレームの表面に凹凸を
つけ、リードフレームとレジンとの接触面積を増加させ
るので、リードフレームとレジンとの密着性を向上する
ことができる。The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) According to the present invention, since the straight lead frame is used as the lead frame of the resin package, the inner end of the lead frame is lifted, and the semiconductor package is bonded to the upper surface of the lifted inner end. Can be reduced in the height direction. (2) According to the present invention, since the straight lead frame is used as the lead frame of the resin package, a sufficient area for mounting the semiconductor chip on the lead frame can be secured. (3) According to the present invention, a sufficient area for mounting the semiconductor chip on the lead frame can be ensured.
Separation of the semiconductor chip and the lead frame can be prevented. (4) According to the present invention, since the lead frame has a frame-shaped projection surrounding the semiconductor chip or a concave portion in the bonding portion with the semiconductor chip, the brazing material for bonding the lead frame and the semiconductor chip has the bonding portion. It can be prevented from flowing out more. (5) According to the present invention, it is possible to prevent the brazing material for bonding the lead frame and the semiconductor chip from flowing out from the bonding portion, so that the bonding strength between the lead frame and the semiconductor chip is improved. Can be. (6) According to the present invention, the inner end of the lead frame of the resin package is lifted up to the upper surface of the resin package,
Since the semiconductor chip is bonded to the lower surface of the inner end of the lead frame, the inner end of the lead frame is lifted, and the resin package is thinner in the height direction than in the structure where the semiconductor chip is bonded to the upper surface of the lifted inner end. can do. (7) According to the present invention, since the surface of the lead frame is made uneven to increase the contact area between the lead frame and the resin, the adhesion between the lead frame and the resin can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態である半導体装置の一例
を示す要部断面図である。FIG. 1 is a fragmentary cross-sectional view showing an example of a semiconductor device according to an embodiment of the present invention.

【図２】（ａ）および（ｂ）は、図１に示した半導体装
置の構造の一例を示す要部平面図および要部断面図であ
る。FIGS. 2A and 2B are a main part plan view and a main part sectional view showing an example of the structure of the semiconductor device shown in FIG. 1;

【図３】（ａ）および（ｂ）は、図１に示した半導体装
置の構造の一例を示す要部平面図および要部断面図であ
る。FIGS. 3A and 3B are a main part plan view and a main part sectional view showing an example of the structure of the semiconductor device shown in FIG. 1;

【図４】図１に示した半導体装置の製造方法を示す要部
断面図である。FIG. 4 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1;

【図５】図４に続く半導体装置の製造工程中の要部断面
図である。5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4;

【図６】図５に続く半導体装置の製造工程中の要部断面
図である。6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5;

【図７】本発明の一実施の形態である半導体装置の一例
を示す要部断面図である。FIG. 7 is a fragmentary cross-sectional view showing one example of a semiconductor device according to an embodiment of the present invention;

【図８】本発明の一実施の形態である半導体装置の一例
を示す要部断面図である。FIG. 8 is a fragmentary cross-sectional view showing one example of a semiconductor device according to an embodiment of the present invention;

【図９】図８に示した半導体装置の製造方法を示す要部
断面図である。9 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor device shown in FIG.

【図１０】図９に続く半導体装置の製造工程中の要部断
面図である。10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;

【図１１】図１０に続く半導体装置の製造工程中の要部
断面図である。11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10;

【符号の説明】[Explanation of symbols]

１ａ リードフレーム（第１リード部） １ｂ リードフレーム（第２リード部） ２ 半導体チップ ３ 表面電極（第３電極） ４ Ａｕワイヤ（金属線） ５ レジン（封止材） ６ 絶縁層 ７ 突起 ８ 蝋材 ９ 凹部 １０ 上面 1a Lead frame (first lead) 1b Lead frame (second lead) 2 Semiconductor chip 3 Surface electrode (third electrode) 4 Au wire (metal wire) 5 Resin (sealing material) 6 Insulating layer 7 Projection 8 Wax Material 9 Recess 10 Upper surface

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 （ａ）第１電極と第２電極との対である
第１リード部および第２リード部を有し、前記第１リー
ド部および前記第２リード部の少なくとも一方は水平状
に延在するリードフレームを用意する工程、（ｂ）その
主面上に半導体素子および第３電極が形成された半導体
チップを前記第１リード部の第１領域の上面に接着する
工程、（ｃ）前記第３電極と前記第２リード部の第１領
域とを金属線により電気的に接続する工程、（ｄ）前記
第１リード部、前記第２リード部、前記半導体チップお
よび前記金属線を封止材により封止する工程、を含むこ
とを特徴とする半導体装置の製造方法。(A) A first lead portion and a second lead portion which are a pair of a first electrode and a second electrode are provided, and at least one of the first lead portion and the second lead portion is horizontal. (B) bonding a semiconductor chip having a semiconductor element and a third electrode formed on a main surface thereof to an upper surface of a first region of the first lead portion; A) electrically connecting the third electrode and the first region of the second lead portion with a metal wire; and (d) connecting the first lead portion, the second lead portion, the semiconductor chip and the metal wire. A method of manufacturing a semiconductor device, comprising a step of sealing with a sealing material. 【請求項２】 （ａ）第１電極と第２電極との対である
第１リード部および第２リード部を有し、前記第１リー
ド部および前記第２リード部が有する第１領域が所定の
高さまで持ち上がったリードフレームを用意する工程、
（ｂ）その主面上に半導体素子および第３電極が形成さ
れた半導体チップを前記第１リード部の前記第１領域の
下面に接着する工程、（ｃ）前記第３電極と前記第２リ
ード部の前記第１領域の下面とを金属線により電気的に
接続する工程、（ｄ）前記第１リード部、前記第２リー
ド部、前記半導体チップおよび前記金属線を封止材によ
り封止する工程、を含むことを特徴とする半導体装置の
製造方法。And (a) a first lead portion and a second lead portion, which are pairs of a first electrode and a second electrode, wherein a first region of the first lead portion and the second lead portion is A process of preparing a lead frame lifted to a predetermined height,
(B) a step of bonding a semiconductor chip having a semiconductor element and a third electrode formed on its main surface to a lower surface of the first region of the first lead portion; and (c) a step of bonding the third electrode and the second lead. Electrically connecting a lower surface of the first region of the portion with a metal wire, and (d) sealing the first lead portion, the second lead portion, the semiconductor chip, and the metal wire with a sealing material. A method for manufacturing a semiconductor device, comprising: 【請求項３】 （ａ）第１電極と第２電極との対である
第１リード部および第２リード部を有し、前記第１リー
ド部および前記第２リード部の少なくとも一方は水平状
に延在するリードフレームを用意する工程、（ｂ）その
主面上に半導体素子および第３電極が形成された半導体
チップを前記第１リード部の第１領域の上面に接着する
工程、（ｃ）前記第３電極と前記第２リード部の第１領
域とを金属線により電気的に接続する工程、（ｄ）前記
第１リード部、前記第２リード部、前記半導体チップお
よび前記金属線を封止材により封止する工程、を含み、
前記第１リード部の前記第１領域の上面は前記半導体チ
ップを取り囲む突起または前記半導体チップとの接着部
における凹部を有することを特徴とする半導体装置の製
造方法。And (a) a first lead portion and a second lead portion, which are pairs of a first electrode and a second electrode, wherein at least one of the first lead portion and the second lead portion is horizontal. (B) bonding a semiconductor chip having a semiconductor element and a third electrode formed on a main surface thereof to an upper surface of a first region of the first lead portion; A) electrically connecting the third electrode and the first region of the second lead portion with a metal wire; and (d) connecting the first lead portion, the second lead portion, the semiconductor chip and the metal wire. Including a step of sealing with a sealing material,
The method of manufacturing a semiconductor device according to claim 1, wherein an upper surface of the first region of the first lead portion has a protrusion surrounding the semiconductor chip or a concave portion in a bonding portion with the semiconductor chip. 【請求項４】 第１電極と第２電極との対であり、少な
くとも一方は水平状に延在する第１リード部および第２
リード部と、その主面上に半導体素子および第３電極が
形成され、前記第１リード部の第１領域の上面に搭載さ
れた半導体チップと、前記第３電極と前記第２リード部
の第１領域とを電気的に接続する金属線とを有し、前記
第１リード部、前記第２リード部、前記半導体チップお
よび前記金属線は封止材により封止されていることを特
徴とする半導体装置。4. A pair of a first electrode and a second electrode, at least one of which is a first lead part and a second lead part extending horizontally.
A lead portion, a semiconductor element and a third electrode formed on the main surface thereof, and a semiconductor chip mounted on the upper surface of the first region of the first lead portion; And a metal wire for electrically connecting the first region and the first region, wherein the first lead portion, the second lead portion, the semiconductor chip, and the metal wire are sealed with a sealing material. Semiconductor device. 【請求項５】 第１電極と第２電極との対であり、第１
領域が所定の高さまで持ち上がった第１リード部および
第２リード部と、その主面上に半導体素子および第３電
極が形成され、前記第１リード部の前記第１領域の下面
に接着された半導体チップと、前記第３電極と前記第２
リード部の前記第１領域の下面とを電気的に接続する金
属線とを有し、前記第１リード部、前記第２リード部、
前記半導体チップおよび前記金属線は封止材により封止
されていることを特徴とする半導体装置。5. A pair of a first electrode and a second electrode,
A first lead portion and a second lead portion whose regions have been raised to a predetermined height, a semiconductor element and a third electrode are formed on the main surface thereof, and are adhered to the lower surface of the first region of the first lead portion. A semiconductor chip, the third electrode, and the second
A metal wire for electrically connecting a lower surface of the first region of the lead portion to the first region, the first lead portion, the second lead portion,
The semiconductor device, wherein the semiconductor chip and the metal wire are sealed with a sealing material.
JP2000353064A 2000-11-20 2000-11-20 Semiconductor device and manufacturing method thereof Pending JP2002158323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000353064A JP2002158323A (en) 2000-11-20 2000-11-20 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000353064A JP2002158323A (en) 2000-11-20 2000-11-20 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2002158323A true JP2002158323A (en) 2002-05-31
JP2002158323A5 JP2002158323A5 (en) 2005-07-21

Family

ID=18825882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000353064A Pending JP2002158323A (en) 2000-11-20 2000-11-20 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2002158323A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014896A (en) * 2002-06-10 2004-01-15 Fuji Electric Holdings Co Ltd Resin sealed semiconductor device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014896A (en) * 2002-06-10 2004-01-15 Fuji Electric Holdings Co Ltd Resin sealed semiconductor device and its manufacturing method

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