JP2002158236A - Method for manufacturing semiconductor device and field-effect transistor manufactured thereby - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing capable of stably forming a structure having an overlapping size of the gate of about 0.1 μm or less. SOLUTION: The method for manufacturing a semiconductor device comprises a step of removing a prescribed part of an amorphous film by etching with a resist film 18 formed on the amorphous film 17 as a mask, a step of removing the prescribed part of a second n-type GaAs layer 16 by wet etching with the amorphous film as a mask by an etchant containing a tartaric acid and an H2O of a ratio of 100:1 to 5:1 with the finger direction of the gate 4 set parallel to a crystal orientation [011], a step of selectively removing only the second n-type GaAs layer 16 by an etchant having high selectivity and anisotropy, and a step of vapor-depositing the gate metal 4 around a removed part of a non-doped or an n-type GaAs layer 14 and a peripheral edge and lifting-off the resist layer 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a field effect transistor (hereinafter referred to as an FET) manufactured by the method, and more particularly to a GaAs FET having a recess structure.

[0002]

2. Description of the Related Art FIG. 7 is a schematic sectional view showing a recess type structure generally used in a GaAs FET. In this figure, 2 is an n-type GaAs substrate, 3 is a recess formed in the main surface of the substrate 2, 4 is a gate provided in the recess 3, 5 and 6 are on the substrate 2 on both sides of the gate 4, respectively. A source and a drain provided. It is known that the FET having such a configuration is easily affected by irregularities due to the semiconductor surface, particularly the recess 3, and has a problem such as a pulse delay. In this type of FET, in order to reduce the influence of the semiconductor surface, it is ideal to set the distance 3A between the gate 4 and the recess 3 in FIG. However, when the gate 4 is formed by vapor deposition, since the vapor deposition source is not provided at infinity with respect to the wafer, the gate vapor deposition is shifted depending on the position of the element in the wafer.

That is, when the element is located at the center of the wafer, the metal deposited on the gate 4 adheres to the recess 3 from almost directly above as shown by an arrow 7 in FIG. As shown in FIG. 9A, the gate 4 is formed in the recess 3 with the above-mentioned interval 3A being 0 according to the dimension set by the mask 8, but the element is located at the center of the wafer. 9A, the metal deposited on the gate 4 adheres at an angle to the recess 3 of the element, as shown by an arrow 7A in FIG. A recess width 3B occurs. The size of the recess width 3B varies depending on the distance of the element position from the center of the wafer, as can be seen from the characteristic diagram showing the relationship between the separation distance and the offset of the deposition in FIG. For example, when the element is at a position 45 mm from the center of the wafer, the size of 3B is about 0.05 μm. Therefore, it is difficult to realize the structure shown in FIG. 8 for all the elements in the wafer plane.

[0004]

Since the conventional method of manufacturing a semiconductor device has faced the above-described problems, one of the measures is to change the structure of the gate 4 from the recess 3 as shown in FIG. It has been practiced to have an overlapping structure that protrudes to cover the peripheral edge. In this case, if the overlap dimension 4A of the element located at the center of the wafer is 0.05 μm, all the elements located within a range of 45 mm from the center of the wafer should have the bottom surface of the recess 3 covered with the gate metal 4. is there. However, in practice, the formation of the overlap is performed by a photo alignment method in which a gate resist pattern is formed independently after the formation of an inner recess as shown in, for example, Japanese Patent Application Laid-Open No. 8-330329. In addition, the gap between the inner recess dimension and the gate electrode easily occurs, and the variation is large. In order to absorb this shift, the size of the overlap is likely to be as large as about 0.2 μm from a process margin or the like. However, as can be seen from the characteristic diagram showing the relationship between the overlap dimension and the gain in FIG. 11, an increase in the overlap dimension tends to cause a decrease in gain and a deterioration in device characteristics.

SUMMARY OF THE INVENTION The present invention has been made to address the above-described problem, and has an overlap dimension of 0.1 μm.
The present invention provides a self-aligned manufacturing method capable of stably forming a structure having a thickness of about 0.1 μm or less. An object is to provide a transistor.

[0006]

According to a method of manufacturing a semiconductor device according to the present invention, a first n-type Ga is formed on a semi-insulating GaAs substrate.
As layer, first AlGaAs layer, non-doped or n-type GaAs
A step of sequentially forming a layer, a second AlGaAs layer, a second n-type GaAs layer of a predetermined thickness and an amorphous film, and patterning a resist layer formed on the amorphous film to determine a gate length. Forming a portion and etching using the resist layer as a mask to remove a predetermined portion of the amorphous film; and making the finger direction of the gate parallel to the crystal orientation [011] to form tartaric acid and H ₂ O.
Wet etching using an etchant having a ratio of ₂ : 1 to 100: 1 to 5: 1 using the amorphous film as a mask to remove a predetermined portion of the second n-type GaAs layer;
A step of side-etching the amorphous film with an F-based etchant, a step of selectively removing only the second n-type GaAs layer with a highly selective and anisotropic etchant, and a second step of using a tartaric acid-based etchant. After removing a predetermined portion of the AlGaAs layer, selectively removing the second n-type GaAs layer and the non-doped or n-type GaAs layer with a highly selective and anisotropic etchant; Alternatively, a step of depositing a gate metal on the removed portion of the n-type GaAs layer and the periphery thereof and lifting off the resist layer is provided.

A method for manufacturing a semiconductor device according to the present invention
In addition, a step of sequentially forming an n-type GaAs layer and an amorphous film on a semi-insulating GaAs substrate, and a patterning for determining a gate length in a resist layer formed on the amorphous film are performed to form an opening. A step of performing etching using the resist layer as a mask to remove a predetermined portion of the amorphous film; and making the finger direction of the gate parallel to the crystal orientation [011], and setting the ratio of tartaric acid to H ₂ O ₂ to 100: 1. Wet etching is performed by using an amorphous film as a mask with an etchant of about 5: 1, and n-type Ga
A step of removing a predetermined portion of the As layer to a predetermined depth, a step of side-etching the amorphous film with an HF-based etchant, and selecting only an n-type GaAs layer with a highly selective and anisotropic etchant To remove n
Forming a two-step recess in the type GaAs layer, and using a resist layer as a mask, depositing a gate metal in an inner recess of the two-step recess and an outer recess around the periphery thereof, and lifting off the resist layer. .

A method for manufacturing a semiconductor device according to the present invention comprises:
Further, a non-doped GaAs layer or a non-doped InGaAs layer, a first AlGaAs layer, a non-doped or n-type GaAs layer, a second AlGaAs layer, a predetermined thickness of n on a semi-insulating GaAs substrate.
Forming a type GaAs layer and an amorphous film sequentially;
Patterning a resist layer formed on the amorphous film to determine a gate length, forming an opening, performing etching using the resist layer as a mask, and removing a predetermined portion of the amorphous film; With the finger direction parallel to the crystal orientation [011], wet etching is performed using an amorphous film as a mask with an etchant in which the ratio of tartaric acid and H ₂ O ₂ is set to 100: 1 to 5: 1. A step of removing a predetermined portion of the GaAs layer, a step of side-etching the amorphous film with an HF-based etchant, and a selective removal of only the n-type GaAs layer of a predetermined thickness with a highly selective and anisotropic etchant. And removing a predetermined portion of the second AlGaAs layer with a tartaric acid-based etchant, and then forming a highly selective and anisotropic etchant. n-type Ga of predetermined thickness by
A step of selectively removing the As layer and the non-doped or n-type GaAs layer; a step of depositing a gate metal on a removed portion of the non-doped or n-type GaAs layer and a periphery thereof using the resist layer as a mask; and a step of lifting off the resist layer. It has.

A method for manufacturing a semiconductor device according to the present invention comprises:
Also, a first n-type GaAs layer on a semi-insulating GaAs substrate,
AlGaAs layer, non-doped or n-type GaAs layer, second Al
A step of sequentially forming a GaAs layer, a second n-type GaAs layer of a predetermined thickness and an amorphous film, and performing patterning for determining a gate length on a resist layer formed on the amorphous film to form an opening, Etching using the resist layer as a mask to remove a predetermined portion of the amorphous film; and making the finger direction of the gate parallel to the crystal orientation [0-11], and adjusting the ratio of tartaric acid to H ₂ O _2.
Perform wet etching using an amorphous film as a mask with an etchant having a ratio of 1:10 to 1:50 to obtain a second n-type.
A step of removing a predetermined portion of the GaAs layer, a step of side-etching the amorphous film with an HF-based etchant, and a second step of using a highly selective and anisotropic etchant.
Selectively removing only the n-type GaAs layer, and removing a predetermined portion of the second AlGaAs layer with a tartaric acid-based etchant, and then removing the second n-type GaAs layer with a highly selective and anisotropic etchant. A step of selectively removing the layer and the non-doped or n-type GaAs layer; and a step of depositing a gate metal on a removed portion of the non-doped or n-type GaAs layer and a periphery thereof using the resist layer as a mask, and lifting off the resist layer. Have

A method for manufacturing a semiconductor device according to the present invention comprises:
In addition, a step of sequentially forming an n-type GaAs layer and an amorphous film on a semi-insulating GaAs substrate, and a patterning for determining a gate length in a resist layer formed on the amorphous film are performed to form an opening. Etching using the resist layer as a mask to remove a predetermined portion of the amorphous film, and making the finger direction of the gate parallel to the crystal orientation [0-11] to set the ratio between tartaric acid and H ₂ O ₂ to 1 : Perform wet etching using an amorphous film as a mask with an etchant having a ratio of 10 to 1:50 to obtain n-type Ga.
A step of removing a predetermined portion of the As layer to a predetermined depth, a step of side-etching the amorphous film with an HF-based etchant, and selecting only an n-type GaAs layer with a highly selective and anisotropic etchant To remove n
Forming a two-step recess in the type GaAs layer, and using a resist layer as a mask, depositing a gate metal in an inner recess of the two-step recess and an outer recess around the periphery thereof, and lifting off the resist layer. .

A method for manufacturing a semiconductor device according to the present invention
Further, a non-doped GaAs layer or a non-doped InGaAs layer, a first AlGaAs layer, a non-doped or n-type GaAs layer, a second AlGaAs layer, a predetermined thickness of n on a semi-insulating GaAs substrate.
Forming a type GaAs layer and an amorphous film sequentially;
Patterning a resist layer formed on the amorphous film to determine a gate length, forming an opening, performing etching using the resist layer as a mask, and removing a predetermined portion of the amorphous film; With the finger direction parallel to the crystal orientation [0-11], wet etching is performed using an amorphous film as a mask with an etchant in which the ratio of tartaric acid to H ₂ O ₂ is 1:10 to 1:50, and a predetermined thickness is obtained. a step of removing a predetermined portion of the n-type GaAs layer, a step of side-etching the amorphous film with an HF-based etchant, and a method of selectively selecting only the n-type GaAs layer having a predetermined thickness with a highly selective and anisotropic etchant. And removing a predetermined portion of the second AlGaAs layer with a tartaric acid-based etchant, and then forming a highly selective and anisotropic etchant. n-type Ga of predetermined thickness by
A step of selectively removing the As layer and the non-doped or n-type GaAs layer; a step of depositing a gate metal on a removed portion of the non-doped or n-type GaAs layer and a periphery thereof using the resist layer as a mask; and a step of lifting off the resist layer. It has.

A field-effect transistor according to the present invention comprises:
In the semiconductor device manufactured by any of the manufacturing methods described above, a source and a drain are provided in a gate formation layer on both sides of a gate.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a process chart showing a manufacturing method according to the first embodiment. In this figure, reference numeral 11 denotes a semi-insulating GaAs substrate, and 12 denotes a first n-type GaAs layer formed on the GaAs substrate 1, for example, having a doping concentration of about 1E17 to 5E17 cm ^-3 and a thickness of 100 to 200 nm. ing. Reference numeral 13 denotes a first n-type GaAs layer 12 formed on the first
In the AlGaAs layer, the molar ratio of Al is about 0.15 to 0.4, and the thickness is 5 to 1
It is 0 nm. Reference numeral 14 denotes a non-doped layer formed on the first AlGaAs layer 13 or a doping concentration of 1E17 cm ^-3.
The following n-type GaAs layer, 15 is a non-doped layer or n-type Ga
A second AlGaAs layer formed on the As layer 14;
It has the same configuration as the As layer.

A second n-type GaAs layer 16 is formed on the second AlGaAs layer 15 and has a doping concentration of 1E18 to 4E18 cm ^-3.
And the thickness is about 200 to 400 nm. Also, 17
Is formed on the second n-type GaAs layer 16 and has a thickness of 2 to 10 nm.
Is an amorphous film such as SiN or SiO. After the formation of the semiconductor layer having such a structure, a resist layer 18 shown in FIG. 1A is provided on the amorphous film 17, and patterning for determining a gate length is performed to form an opening 18A having a dimension A.
Is formed, dry or wet etching is performed using the resist layer 18 as a mask to remove a portion corresponding to the dimension A of the amorphous film 17 as shown in the figure.

Next, as shown in FIG. 1B, by wet etching using the amorphous film 17 as a mask,
A recess 16A is formed in the second n-type GaAs layer 16. In this case, the dimension B of the bottom of the recess and the opening 18A of the resist layer are formed.
Is required to satisfy 0.1 ≦ AB ≦ 0.2 μm. This is because the thickness of the second n-type GaAs layer 16 is 200 to 400 nm and the finger direction of the gate is Can be realized by using an etchant in which the ratio between tartaric acid and H ₂ O ₂ is set to 100: 1 to 5: 1 while the crystal orientation is parallel to the crystal orientation [011]. Further, it can also be realized by using an etchant in which the finger direction of the gate is parallel to the crystal orientation [0-11] and the ratio of tartaric acid to H ₂ O ₂ is 1:10 to 1:50.

Next, using an HF-based etchant, FIG.
As shown in (c), the amorphous film 17 is formed to a thickness of 0.3 to 1 μm.
m side etching. Then, using a highly selective anisotropic etchant such as citric acid, etc., as shown in FIG.
As shown in (d), only the second n-type GaAs layer 16 is selectively removed. In this case, the relationship of 0.1 ≦ AB ≦ 0.2 μm is maintained by anisotropic etching with an etchant. Next, using a tartaric acid-based etchant, FIG.
As shown in FIG. 1E, after a predetermined portion of the second AlGaAs layer 15 is removed, the non-doped layer or the n-type GaAs layer 14 is removed by the citric acid-based etchant used in the step of FIG. As shown in FIG. afterwards,
Using the resist layer 18 as a mask, the gate 4 is formed by vapor deposition so as to overlap the inner recess and the periphery thereof, and the resist layer 18 is lifted off to form the resist layer 18.
The structure shown in FIG. 1F is obtained by removing the metal film deposited thereon. According to this method, as described above, the overlap dimension of the gate 4 can be formed to 0.1 μm or less.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows Embodiment 2
FIG. 4 is a process chart showing a method for manufacturing the same. In this figure, FIG.
The same or corresponding parts are denoted by the same reference numerals and description thereof is omitted. The difference from FIG. 1 is that the first and second AlGaAs layers 13 and 15 and the second n-type GaAs layer 16 are removed, and the recess formed in the step of FIG. The point is that it is formed on the n-type GaAs layer 12. Therefore,
The recess 16A in FIG. 1B is shown as 12A in this embodiment.

The processing in the steps of FIGS. 2A, 2B, and 2C is the same as the processing in the steps of FIGS. 1A, 1B, and 1C, and a description thereof will not be repeated. The step of FIG.
In the step of FIG. 1D, a process of selectively removing only the second n-type GaAs layer 16 using a highly selective and anisotropic etchant such as a citric acid-based process is referred to as a first process. n-type Ga
As shown in FIG.
In (d), the depth to be removed is set to be 200 to 400 nm. As a result, the recess formed in FIG. 2D has the same size as that shown in FIG. 1E, and the same process as in FIG. 1F is performed in FIG. 4 can be made the same as FIG. 1 (f).

Embodiment 3 Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows a third embodiment.
FIG. 4 is a process chart showing a method for manufacturing the same. In this figure, FIG.
The same or corresponding parts are denoted by the same reference numerals and description thereof is omitted. The difference from FIG. 1 is that the first n-type Ga in FIG.
The point is that a non-doped GaAs layer or a non-doped InGaAs layer 19 is provided in place of the As layer 12 to realize a so-called HEMT structure. That is, in FIG. 3, reference numeral 19 denotes a non-doped GaAs layer or a non-doped InGaAs layer. It is also possible to adopt a structure in which an AlGaAs layer is further provided below this layer 19. The processing contents in each step shown in FIGS. 3A to 3F are the same as the processing contents in each step shown in FIGS.

Embodiment 4 Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows a fourth embodiment.
FIG. 2 is a schematic cross-sectional view showing the configuration of FIG. 1, showing a field-effect transistor manufactured by the manufacturing method of the first embodiment shown in FIG. A two-step recess called a two-step recess is formed on the semiconductor surface, the outer recess 16A has a depth of 200 to 400 nm, and the inner recess 14A has a depth of 30 to 100 n.
m. The gate 4 completely covers the bottom surface of the inner recess 14A and overlaps a part of the outer recess 16A on the periphery thereof, and the overlap dimension 4A is 0.1 μm or less as described above. Therefore, it is possible to suppress pulse delay and the like, which have been a problem in the conventional field effect transistor, and also to suppress deterioration in characteristics due to an increase in gate length.

Embodiment 5 Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 5 shows a fifth embodiment.
FIG. 4 is a schematic cross-sectional view showing the configuration of the first embodiment, and shows a field-effect transistor manufactured by the manufacturing method of the second embodiment shown in FIG. Compared to FIG. 4, the first and second AlGaAs
The functions and effects are almost the same except that the layers 13 and 15 are removed and the gate forming layer is the first n-type GaAs layer 12, and the description of the other parts is omitted.

Embodiment 6 FIG. Next, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows Embodiment 6.
FIG. 4 is a schematic cross-sectional view showing the configuration of the third embodiment, and shows a field-effect transistor manufactured by the manufacturing method of the third embodiment shown in FIG. Compared to FIG. 1, the first n-type GaAs layer 12 is replaced with a non-doped GaAs layer or a non-doped InGa
The only difference is that an As layer 19 is provided and a so-called HEMT structure is provided, so that the description of the other parts is omitted. In addition, below the GaAs layer or the InGaAs layer 19, an AlGa
Even if an As layer is provided, the same function and effect can be expected.

[0023]

The method for manufacturing a semiconductor device and the field-effect transistor according to the present invention are configured as described above, so that pulse delay and the like can be suppressed, and characteristic deterioration due to an increase in gate length can be prevented. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a process chart showing a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a manufacturing method according to a second embodiment of the present invention.

FIG. 3 is a process chart showing a manufacturing method according to a third embodiment of the present invention.

FIG. 4 is a schematic sectional view showing a configuration of a fourth embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a configuration of a fifth embodiment of the present invention.

FIG. 6 is a schematic sectional view showing a configuration of a sixth embodiment of the present invention.

FIG. 7 is a schematic sectional view showing a configuration of a conventional field-effect transistor.

FIG. 8 is a schematic cross-sectional view showing an ideal configuration of a field-effect transistor having a recess structure.

FIGS. 9A and 9B are explanatory diagrams showing a state of offset when forming a gate by vapor deposition, where FIG. 9A shows a state in which an element is located at the center of a wafer, and FIG. (C) is a characteristic diagram showing the relationship between the position of the element and the offset of the deposited metal.

FIG. 10 is a schematic sectional view showing a gate having a conventional overlap structure.

FIG. 11 is a characteristic diagram showing a relationship between an overlap size and a gain.

[Description of Signs] 4 gates, 11 GaAs substrate, 12 first n-type Ga
As layer, 13 first AlGaAs layer, 14 non-doped layer or n-type GaAs layer, 15 second AlGaAs layer, 16
2nd n-type GaAs layer, 16A recess, 17 amorphous film, 18 resist layer, 18A opening,
19 Non-doped GaAs layer or non-doped InGaAs
layer.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F043 AA14 AA31 AA35 BB07 BB22 BB23 FF02 FF03 5F102 GB01 GC01 GD01 GJ05 GK04 GK05 GL05 GM06 GN05 GR01 GR04 GS04 GV07 GV08 HC11 HC16 HC17 HC19

Claims (7)

[Claims] 1. A first n-type GaAs on a semi-insulating GaAs substrate.
Layer, a first AlGaAs layer, a non-doped or n-type GaAs layer,
A step of sequentially forming a second AlGaAs layer, a second n-type GaAs layer of a predetermined thickness and an amorphous film, and patterning for determining a gate length on the resist layer formed on the amorphous film to form an opening. And etching using the resist layer as a mask to remove a predetermined portion of the amorphous film; and making the finger direction of the gate parallel to the crystal orientation [011] to form tartaric acid and H ₂ O ₂ . A wet etching using the amorphous film as a mask with an etchant having a ratio of 100: 1 to 5: 1 to remove a predetermined portion of the second n-type GaAs layer; and an HF-based etchant. And a step of selectively removing only the second n-type GaAs layer with an etchant having high selectivity and anisotropy. After removing a predetermined portion of the second AlGaAs layer with a tartaric acid-based etchant, the second n-type GaAs layer and the non-doped or n-type GaAs layer are selectively removed with the highly selective and anisotropic etchant. And a step of depositing a gate metal on a portion where the non-doped or n-type GaAs layer is removed and a periphery thereof using the resist layer as a mask, and lifting off the resist layer. 2. A step of sequentially forming an n-type GaAs layer and an amorphous film on a semi-insulating GaAs substrate, and patterning a resist layer formed on the amorphous film to determine a gate length. Together with
Etching using the resist layer as a mask to remove a predetermined portion of the amorphous film, and making the finger direction of the gate parallel to the crystal orientation [011], and setting the ratio of tartaric acid to H ₂ O ₂ to 100: A step of performing wet etching using the amorphous film as a mask with an etchant of 1 to 5: 1 to remove a predetermined portion of the n-type GaAs layer so as to have a predetermined depth, and removing the amorphous film with an HF-based etchant. A side etching step, a step of selectively removing only the n-type GaAs layer with an etchant having high selectivity and anisotropy to form a two-step recess in the n-type GaAs layer, and a step of masking the resist layer. Depositing a gate metal on an inner recess of the two-step recess and an outer recess around the periphery thereof, and lifting off the resist layer; Method of manufacturing a semiconductor device with. 3. A non-doped Ga on a semi-insulating GaAs substrate.
As layer or undoped InGaAs layer, first AlGaAs layer,
A step of sequentially forming a non-doped or n-type GaAs layer, a second AlGaAs layer, an n-type GaAs layer of a predetermined thickness and an amorphous film, and patterning for determining a gate length on the resist layer formed on the amorphous film. Forming an opening, etching using the resist layer as a mask to remove a predetermined portion of the amorphous film, and setting the finger direction of the gate parallel to the crystal orientation [011] to form tartaric acid and H 100: 1 to ₂ O ₂ ratio
A step of performing wet etching using the amorphous film as a mask with a 5: 1 etchant to remove a predetermined portion of the n-type GaAs layer having the predetermined thickness, and a step of side-etching the amorphous film with an HF-based etchant. A step of selectively removing only the n-type GaAs layer having the predetermined thickness with a highly selective and anisotropic etchant; and a second AlGaAs layer with a tartaric acid-based etchant.
After removing a predetermined portion of the layer, selectively removing the n-type GaAs layer and the non-doped or n-type GaAs layer having the predetermined thickness with the highly selective anisotropic etchant; Depositing a gate metal on a portion where the non-doped or n-type GaAs layer is removed and a peripheral edge thereof as a mask, and lifting off the resist layer. 4. A first n-type GaAs on a semi-insulating GaAs substrate.
Layer, a first AlGaAs layer, a non-doped or n-type GaAs layer,
A step of sequentially forming a second AlGaAs layer, a second n-type GaAs layer of a predetermined thickness and an amorphous film, and patterning for determining a gate length on the resist layer formed on the amorphous film to form an opening. And etching using the resist layer as a mask to remove a predetermined portion of the amorphous film; and making the finger direction of the gate parallel to the crystal orientation [0-11] to form tartaric acid and H ₂ O. A step of performing wet etching using the amorphous film as a mask with an etchant having a ratio of ₂ to 1:10 to 1:50 to remove a predetermined portion of the second n-type GaAs layer; A step of side-etching the amorphous film, and a step of selectively removing only the second n-type GaAs layer with an etchant having high selectivity and anisotropy. After removing a predetermined portion of the second AlGaAs layer with a tartaric acid-based etchant, the second n-type GaAs layer and the non-doped or n-type GaAs layer are selectively selected with the highly selective and anisotropic etchant. A method of manufacturing a semiconductor device, comprising: a step of removing; and, using the resist layer as a mask, a step of depositing a gate metal on a portion where the non-doped or n-type GaAs layer is removed and a periphery thereof, and lifting off the resist layer. 5. A step of sequentially forming an n-type GaAs layer and an amorphous film on a semi-insulating GaAs substrate, and patterning a resist layer formed on the amorphous film to determine a gate length. Together with
Etching using the resist layer as a mask to remove a predetermined portion of the amorphous film; and making the finger direction of the gate parallel to the crystal orientation [0-11] to reduce the ratio of tartaric acid to H ₂ O _2. A step of performing wet etching using the amorphous film as a mask with an etchant having a ratio of 1:10 to 1:50 to remove a predetermined portion of the n-type GaAs layer to a predetermined depth, and a step of removing the amorphous portion by using an HF-based etchant. A step of side-etching the film, a step of selectively removing only the n-type GaAs layer with a highly selective and anisotropic etchant to form a two-step recess in the n-type GaAs layer, Depositing a gate metal on the inner recess of the two-step recess and the outer recess on the periphery thereof using a mask as a mask, and lifting off the resist layer; A method for manufacturing a semiconductor device having: 6. A non-doped Ga on a semi-insulating GaAs substrate.
As layer or undoped InGaAs layer, first AlGaAs layer,
A step of sequentially forming a non-doped or n-type GaAs layer, a second AlGaAs layer, an n-type GaAs layer of a predetermined thickness and an amorphous film, and patterning for determining a gate length on the resist layer formed on the amorphous film. Forming an opening, etching using the resist layer as a mask to remove a predetermined portion of the amorphous film, and setting the finger direction of the gate parallel to the crystal orientation [0-11] to form tartaric acid. the ratio of the H ₂ O ₂ 1: 10~
A step of performing wet etching using the amorphous film as a mask with a 1:50 etchant to remove a predetermined portion of the n-type GaAs layer having the predetermined thickness, and a step of side-etching the amorphous film with an HF-based etchant. A step of selectively removing only the n-type GaAs layer having the predetermined thickness with a highly selective and anisotropic etchant; and a second AlGaAs layer with a tartaric acid-based etchant.
After removing a predetermined portion of the layer, selectively removing the n-type GaAs layer and the non-doped or n-type GaAs layer having the predetermined thickness with the highly selective anisotropic etchant; Depositing a gate metal on a portion where the non-doped or n-type GaAs layer is removed and a peripheral edge thereof as a mask, and lifting off the resist layer. 7. A semiconductor device manufactured by the manufacturing method according to claim 1, wherein a source and a drain are provided in a gate formation layer on both sides of the gate. Transistor.