JP2002152313A - Multichannel digital circuit terminal system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time up to start of circuit terminating on startup. SOLUTION: Communication channel modules 11 and 12 are respectively provided with circuit terminating parts 111 and 112 to terminate the circuits of communication data on the basis of clocks CK31 and CK32, synchronous clock generating parts 112 and 122 to respectively generate clocks CK1 and CK2 synchronizing with the frame of data signals from ISDN exchanges 61 and 62, and clock selection parts 113 and 123 which respectively receive the clocks CK1 and CK2, select respectively either of them and output it as a clock CK31 or a clock 32 respectively. The clock selection part monitors a synchronous clock of own communication channel module as well as one of the other communication channel module, and selects one that is first detected. Then, when the synchronous clock of the own communication channel module is detected, the clock selection part selects it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel digital line termination unit (DSU: Digit11 Service U) which is installed between a digital circuit exchange and a user terminal and performs line termination processing such as signal format conversion.
nit).

[0002]

2. Description of the Related Art Signal speeds transmitted to digital communication lines such as ISDN are 3.2 kbit / s and 6.4 kbit.
/ S, 12.8 kbit / s, and 64 kbit / s are standardized. Therefore, it is necessary to convert a signal transmitted from a user terminal device to a digital communication line so as to conform to any of the above. In addition, signals to be sent to the digital network switch and the user terminal device need to match the phase of the frame of the digital communication line. For this reason, a digital circuit terminating device (DSU: Digit 11 S) is provided between the digital circuit exchange and the user terminal device.
service unit) and performs line termination processing (transmission service) such as signal format conversion.

FIG. 5 is a block diagram showing an example of a conventional multi-channel digital line termination device, and shows a two-channel digital line termination device (hereinafter referred to as a DSU).

In FIG. 5, a DSU comprises a communication channel module 51 for performing a line termination process between an ISDN exchange 61 of a first communication channel and a user terminal 71, and an ISDN exchange 62 and a user terminal 72 of a second communication channel.
And a communication channel module 52 for performing line termination processing.

[0005] Each communication channel module 51, 52 comprises:
Synchronous clock generators 112 and 122 for generating a clock synchronized with the frame of the ISDN line, and a synchronous clock C generated by the synchronous clock generators 112 and 122
Line termination processing units 111 and 121 for performing line termination processing of communication data between the ISDN exchanges 61 and 62 and the user terminals 71 and 72 based on K1 and CK2, respectively.

Further, synchronous clock generators 112 and 122
Are synchronous timing extracting circuits 113 and 123 for extracting synchronous timing signals synchronized with frames in the data signals transmitted from the ISDN exchanges 61 and 62, and clocks CK1 and CK1 synchronized with the line based on the synchronous timing signals.
CK2 is generated and the line termination processing units 111 and 12 are generated.
1 and clock generation circuits 114 and 124 for supplying the clock generation circuits 1 and 2, respectively. The clock generation circuits 114 and 124
LL.

[0007]

As described above, in the conventional multi-channel digital line termination unit (DSU), the communication channel modules provided for each communication channel independently synchronize with the frame of the ISDN line. And performs line termination processing.

That is, when each communication channel module is activated, each communication channel module receives a data signal supplied from each ISDN exchange, generates a synchronization timing signal synchronized with the frame, and generates a synchronization timing signal based on the synchronization timing signal. The PLL performs a synchronization pull-in operation to generate a synchronization clock, and starts line termination processing based on the synchronization clock. However, since it takes time to generate a synchronization timing signal, perform a synchronization pull-in operation, and generate a synchronization clock, there is a problem that the start of line termination processing is delayed.

An object of the present invention is to provide a multi-channel digital line termination device which can generate a synchronous clock at an early stage at the time of start-up and reduce the time required for starting line termination processing.

[0010]

SUMMARY OF THE INVENTION A multi-channel digital line termination device according to the present invention is installed between a plurality of digital line switches and a plurality of user terminals to generate a clock synchronized with the digital line and terminate the line. A multi-channel digital line termination device including a plurality of communication channel modules each performing a process, wherein the plurality of communication channel modules have means for sharing the clock generated by each.

According to a first aspect of the present invention, a first communication channel module for performing a line termination process between an exchange of a first communication channel and a user terminal, and a line termination process between an exchange of a second communication channel and a user terminal are provided. And a second communication channel module, wherein the first (second) communication channel module includes a first communication channel module synchronized with the first (second) communication channel.
A first (second) synchronous clock generator for generating a (second) clock, and receiving one of the first (second) synchronous clock and the second (first) clock, respectively, A first (second) clock selection unit to be selected; and a first (second) line termination processing unit for performing a line termination process based on the clock selected by the first (second) clock selection unit. The first (second) clock selection unit monitors the first and second clocks at the time of startup and selects the previously detected synchronous clock, and the second (first) clock at the time of startup.
Is selected, then the first (second)
When the first clock is detected, the first (second) clock is selected.

According to a second aspect of the present invention, there is provided a first line termination processing unit for performing a line termination process between an exchange of a first communication channel and a user terminal, and a first synchronous clock synchronized with the first communication channel. A first communication channel module having a first synchronous clock generation unit, a second line termination processing unit for performing a line termination process between a switch of a second communication channel and a user terminal, and the second communication channel. A second communication channel module having a second synchronous clock generation unit for generating a synchronized second synchronous clock, and a common module for receiving and selecting one of the first and second clocks as a common clock and outputting one of them. A clock selection unit, wherein the first and second line termination processing units perform a line termination process based on the shared clock.

The shared clock selection unit monitors the first and second clocks and selects the previously detected synchronous clock. Thereafter, when the selected clock is cut off, the other clock is selected. If the clock can be detected, the other clock is selected.

According to a third aspect of the present invention, a clock is provided between a plurality of exchanges of each communication channel of a digital line and a user terminal, and a clock synchronized with the digital line is generated, and a line termination process of each communication channel is performed. A plurality of communication channel modules to perform, and a shared clock generating unit that receives the clocks respectively generated by the plurality of communication channel modules and generates a shared clock corrected to an average value of a phase difference between the respective clocks, The plurality of communication channel modules are configured to perform line termination processing based on the shared clock.

[0015] The shared clock generation unit may include a reference clock selection circuit that selects one of clocks generated by the plurality of communication channel modules as a reference clock in a predetermined priority order, A phase difference detection circuit that detects a phase difference between the clock signal and another clock, a phase difference averaging circuit that calculates an average value of the detected phase differences, and corrects the phase of the reference clock by the average value of the phase differences. And a phase correction circuit for outputting the common clock.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and shows a digital line termination device (hereinafter, referred to as a DSU) of two communication channels. The same components as those of the conventional example shown in FIG. 5 are denoted by the same reference numerals.

In FIG. 1, the DSU includes a communication channel module 11 for a first communication channel for performing a line termination process between the ISDN exchange 61 and the user terminal 71, and an ISD.
A communication channel module 12 for a second communication channel for performing a line termination process between the N exchange 62 and the user terminal 72 is provided.

The communication channel modules 11 and 12 perform line termination processing on communication data based on the synchronous clocks CK31 and CK32, respectively.
1, synchronous clock generators 112 and 122 for generating clocks CK1 and CK2 synchronized with the frames of the data signals from the ISDN exchanges 61 and 62, respectively, and receive and select one of the synchronous clocks CK1 and CK2 to synchronize. Clock selectors 113 and 123 that output clocks CK31 and CK32, respectively, are provided.

The synchronous clock generators 112 and 122 extract a synchronous timing signal synchronized with the frame in the data signals transmitted from the ISDN exchanges 61 and 62, similarly to the synchronous clock generator shown in FIG. Clocks CK1 and C synchronized with the line based on the synchronization timing signal
K2 is generated.

If the frame phase difference between the communication data of the digital line connected to the ISDN exchange 61 and the communication data of the digital line connected to the ISDN exchange 62 is within the standard, the communication channel modules 11 and 12 are used.
Synchronous clocks CK1, CK respectively generated in
2 can be shared with each other. That is, even if the communication channel module 11 performs the line termination processing based on the synchronization clock CK2 of the communication channel module 12, the communication channel module 12 performs the line termination processing based on the synchronization clock CK1 of the communication channel module 11. Also, it is possible to perform processing without any trouble as communication data of the digital line.

According to the present invention, when starting each communication channel module, one of a plurality of synchronous clocks generated by each communication channel module is selected and used, thereby shortening the time until the start of the line termination processing. The configuration is as follows.

As shown in FIG. 1, the clock selectors 113 and 123 monitor the synchronous clocks CK1 and CK2 generated by the synchronous clock generators 112 and 122 of the communication channel modules 11 and 12, respectively, and perform one of them. Clock selection circuits 114 and 124 for selecting one
And one of the synchronous clocks CK1 and CK2 is selected according to the selection result of the clock selecting circuits 114 and 124, and is used as the synchronous clocks CK31 and CK32.
Clock switching circuit 11 for outputting to clocks 11 and 121, respectively
5,125.

The clock selection circuit 11 of the clock selection unit
4 and 124 monitor the synchronization clock of the own communication channel module and the synchronization clock of the other communication channel module, and select the synchronization clock that can be detected earlier at the time of startup. Then, when the synchronous clock of the other communication channel module is selected at the time of startup, and thereafter, when the synchronous clock of the own communication channel module is detected, the synchronous clock of the own communication channel module is selected.

If the synchronous clock is interrupted while the synchronous clock of the own communication channel module is selected, if the synchronous clock of the other communication channel module can be detected, the other synchronous clock is selected. I do.

When the synchronous clock of the own communication channel module and the synchronous clock of the other communication channel module are simultaneously detected at the time of activation, the synchronous clock of the own communication channel module is selected with priority.

As described above, by selecting one of the synchronous clocks CK1 and CK2 and performing the line termination processing, for example, when the communication channel module 11 is activated, the other communication channel module 12 causes the synchronous clock CK2
Is generated, the communication channel module 11 can immediately start the line termination process using the synchronization clock CK2 before the synchronization clock CK1 of the own communication channel module 11 is generated.

After that, when the synchronous clock CK1 of the own communication channel module 11 is detected, this synchronous clock CK1 is selected to continue the line termination processing irrespective of the operation of the other communication channel module 12. Can be.

Further, when a failure occurs and the synchronous clock CK1 is cut off while the synchronous clock CK1 of the own communication channel module 11 is selected and operating, the synchronous clock CK1 of the other communication channel module 12 is disconnected. CK2
Can be detected, the operation can be continued without stopping the line termination processing by selecting the other synchronous clock CK2.

FIG. 2 is a block diagram showing a second embodiment.

The difference from the one shown in FIG. 1 is that the clock selection units of the respective communication channel modules in FIG. Thus, the circuit configuration can be simplified by sharing the clock selection unit. The same components as those shown in FIG. 1 are denoted by the same reference numerals.

The communication channel modules 21 and 22 are respectively provided with line termination processors 111 and 121 for performing line termination processing of communication data based on the shared synchronous clock CK3, and I
Synchronous clock generators 112 and 122 for generating clocks CK1 and CK2 synchronized with the frames of the data signals from the SDN switches 61 and 62, respectively.

The common clock selecting section 3 has the same configuration as the clock selecting sections 113 and 123 shown in FIG. That is, a clock selection circuit 31 that receives the synchronization clocks CK1 and CK2 generated by the synchronization clock generation units 112 and 122 of the communication channel modules 11 and 12, respectively, and selects one of them, and a selection result of the clock selection circuit 31 Clocks CK1 and CK2
And a clock switching circuit 32 for selecting one of them and outputting it as a shared synchronous clock CK3.

The clock selection circuit 31 of the shared clock selection unit 3 is configured to output the synchronous clock C of the communication channel module 21.
K1 and the synchronous clock CK2 of the other communication channel module 22 are constantly monitored, and the synchronous clock detected earlier is selected.

When the selected synchronous clock is cut off, if the synchronous clock of the other communication channel module can be detected, the other synchronous clock is selected.

When the synchronous clock of the own communication channel module and the synchronous clock of the other communication channel module are detected at the same time at the time of activation, the synchronous clock is selected according to a preset priority.

By selecting a synchronous clock in this way, for example, when the communication channel module 21 is activated, if the other communication channel module 22 has previously generated the synchronous clock CK2, the communication channel module 11 is shared. The line termination processing can be started early using the synchronous clock CK3, that is, the synchronous clock CK2.

When a synchronous clock generation unit of one communication channel module fails and the synchronous clock is cut off, if the synchronous clock of the other communication channel module can be detected, the other synchronous clock is used. Thus, the operation can be continued without stopping the line termination processing.

FIG. 3 is a block diagram showing a third embodiment.

A multi-channel DSU for performing line termination processing for a plurality of n communication channels is shown. Here, the plurality of communication channel modules 21, 22,..., 2n have the same configuration as the communication channel modules 21, 22 shown in FIG.

.., 7n based on the shared synchronous clock CK4, and a line termination processing unit for performing line termination processing of communication data between the user terminals 71, 72,. Exchange 6
., CKn synchronized with the frames of the data signals from 1, 62,..., 6n. Here, illustration is omitted.

The synchronous clocks CK1, CK2,.
, CKn are within the standard of the frame phase difference of the communication data of the digital line to which each ISDN exchange is connected.

The main difference from the one shown in FIG. 2 is that a shared clock generator 4 for newly generating a highly accurate shared synchronous clock based on synchronous clocks generated in a plurality of communication channel modules is provided. Is a point.

As shown in FIG. 4, the shared clock generator 4 includes a plurality of communication channel modules 21, 22,.
2n, the synchronous clocks CK1,
CKn, and receives one of the synchronous clocks in accordance with a predetermined priority order.
a reference clock selection circuit 41 selected as s, a phase difference detection circuit 42 for detecting a phase difference between the reference clock CKs and another synchronous clock, and a phase difference averaging circuit 43 for calculating an average value of the detected phase differences. , Reference clock CK
and a phase correction circuit 44 that corrects the phase of s by the average value of the phase difference and outputs the same as the shared synchronous clock CK4.

By generating the common synchronous clock in this way, if at least one of the plurality of communication channel modules generates the synchronous clock, the other communication channel modules use the common synchronous clock. Immediately, the line termination processing can be started.

Further, the accuracy of the shared synchronous clock CK4 can be improved by correcting the average value of the phase difference between the plurality of synchronous clocks.

[0047]

As described above, according to the present invention, when each communication channel module is activated, the synchronous clock generated by each of the plurality of communication channel modules is used, so that the time until the start of the line termination processing is obtained. Can be reduced, and the reliability of the synchronous clock can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a shared clock generation unit 4 shown in FIG.

FIG. 5 is a block diagram showing an example of a conventional multi-channel digital line termination device.

[Explanation of symbols]

 11, 12 Communication channel module 111, 121 Line termination processing unit 112, 122 Synchronous clock generation unit 113, 123 Clock selection unit 114, 124 Clock selection circuit 115, 125 Clock switching circuit 21, 22, ..., 2n Communication channel module 3 Shared clock selection unit 31 Clock selection circuit 32 Clock switching circuit 4 Shared clock generation unit 41 Reference clock selection circuit 42 Phase difference detection circuit 43 Phase difference averaging circuit 44 Phase correction circuit

Claims (7)

[Claims] 1. A multi-channel digital line provided between a plurality of digital line switches and a plurality of user terminals and comprising a plurality of communication channel modules for generating clocks synchronized with the digital lines and performing line termination processing, respectively. A terminating device, wherein the plurality of communication channel modules have means for sharing the clock generated by each of the plurality of communication channel modules. 2. A first communication channel module for performing a line termination process between an exchange of a first communication channel and a user terminal, and a second communication terminal for performing a line termination process between an exchange of a second communication channel and a user terminal. A multi-channel digital line termination device comprising: a communication channel module, wherein the first (second) communication channel module comprises:
A first (second) synchronous clock generator for generating a first (second) clock synchronized with the (second) communication channel, the first (second) synchronous clock, and the second (second) synchronous clock;
A first (second) clock selection unit that receives one of the (first) clocks and selects one of them, and performs a line termination process based on the clock selected by the first (second) clock selection unit. A multi-channel digital line termination device, comprising: a first (second) line termination processing unit. 3. The first (second) clock selecting unit,
When the first and second clocks are monitored at the time of startup and the previously detected synchronous clock is selected, and when the second (first) clock is selected at the time of startup, the first (second) clock is thereafter selected. 3. The multi-channel digital line terminal according to claim 2, wherein the first (second) clock is selected when a clock is detected. 4. A first line termination processing unit for performing a line termination process between an exchange of a first communication channel and a user terminal, and a first circuit for generating a first synchronization clock synchronized with the first communication channel. First having a synchronous clock generator
A communication channel module, a second line termination processing unit for performing a line termination process between the exchange of the second communication channel and the user terminal, and a second line for generating a second synchronous clock synchronized with the second communication channel. A second communication channel module having a synchronous clock generator of
And a shared clock selecting unit for receiving and selecting one of them as a shared clock in response to the second clock, and wherein the first and second line termination processing units perform line termination processing based on the shared clock. It is characterized by performing a multi-channel digital line termination. 5. The shared clock selecting section monitors the first and second clocks and selects a previously detected synchronous clock, and thereafter, when the selected clock is cut off, the other of the two. 5. The multi-channel digital line termination according to claim 4, wherein the other clock is selected if a clock can be detected. 6. A plurality of communications which are respectively installed between a plurality of exchanges of each communication channel of a digital line and a user terminal and generate clocks synchronized with the digital line and respectively perform line termination processing of each communication channel. A channel module; and a shared clock generating unit configured to receive the clocks generated by the plurality of communication channel modules and generate a shared clock corrected to an average value of a phase difference between the clocks. A multi-channel digital line termination device, wherein each module performs a line termination process based on the shared clock. 7. The reference clock selection circuit, wherein the common clock generation unit selects one of clocks respectively generated by the plurality of communication channel modules as a reference clock in a predetermined priority order, and A phase difference detection circuit that detects a phase difference between the clock signal and another clock, a phase difference averaging circuit that calculates an average value of the detected phase differences, and corrects the phase of the reference clock by the average value of the phase differences. And a phase correction circuit for outputting the common clock as the common clock.
A multi-channel digital line termination device as described.