JP2002152201A - Packet detection display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet detection display device of a simple configuration that is used to confirm a data rate of a packet signal with a packet structure, such as a TS signal and the presence/absence of the packet signal. SOLUTION: A TV broadcast receiver receives a TS signal 101 from an external device. An input buffer 101 gives the TS signal 101 to a synchronization signal generating circuit 2 and a data processing circuit 6. When the synchronization signal generating circuit 2 detects a SYNC value included in a header part of the TS signal 101, the generating circuit 2 generates a synchronizing signal 102. A frequency divider circuit 3 applies 1/N frequency division to the synchronizing signal 102 and generates a frequency division signal 103. A light- emitting element control circuit 4 displays an input state of the TS signal 101 on a light-emitting element section 5, on the basis of the frequency division signal 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet detection and display device, and more particularly, to a packet detection and display device for use in the production, adjustment, and design of digital broadcasting equipment, and a TS (Transport and Display) device.
The present invention relates to a TS signal generator for inputting / outputting an “rt Stream” signal, a TS signal analyzer, and a packet detection / display device mounted on a TS signal interface / data rate converter.

[0002]

2. Description of the Related Art TV broadcasting will be replaced by BS broadcasting during this fiscal year and terrestrial broadcasting by 2010 in place of the current analog system.
It will transition to a digital format by the year and all will be digitized in a few years. The TS signal is a signal in which transmission information such as an image, a sound, and data is digitized and multiplexed. In digital broadcasting, a broadcast wave in which a TS signal is modulated is transmitted to a user at each home.

[0003] When developing a set-top box (digital BS tuner) or the like, a manufacturer uses a TS signal from a TS signal generator as a reference signal or a TS signal containing an error to transmit transmission information. Check whether the output is correct or not. A packet detection display device is used to confirm that a packet signal such as a TS signal is correctly transmitted or received.

FIG. 3 is a block diagram of a conventional packet detection and display device. FIG. 2A shows a T signal for receiving a TS signal.
This is an example of application to a V broadcast receiving device. The packet detection display device inputs the TS signal 101 input from the outside to the data processing circuit 22 via the input buffer 21. The data processing circuit 22 performs data analysis, data rate and synchronization signal detection of the TS signal, and other error analysis, and inputs an analysis signal 104 as an analysis result to the display device control circuit 23. The display device control circuit 23 inputs data corresponding to the display method to the display device 24 based on the analysis signal 104. The display device 24 displays the input state of the TS signal 101 by a display method such as a data rate method, a progress bar method, or a counter method.

The data processing circuit 22 performs interface conversion, data rate conversion, and the like, and outputs the converted signal to the outside. Some TV broadcast receivers only perform interface conversion and data rate conversion of TS signals and do not require the display device control circuit 23 and the display device 24.

FIG. 1B shows an example of application to a TV broadcast transmitting apparatus for transmitting a TS signal. The data output circuit 25
A TS signal 101 is generated and output to the outside via the output buffer 26. The packet detection display device uses the display device control circuit 23 and the display device 24 to display the output state of the TS signal to be output to the outside, similarly to the TV broadcast receiving device. The packet detection display device includes a data output circuit 2
When inputting the TS signal 101 from No. 5 to the display device control circuit 23, there are two methods indicated by a solid line and a broken line.

In the first method shown by the solid line, the data output circuit 25 stores all the generated TS signals 101,
It is input to the display device control circuit 23 as the entire TS signal 105. In the TV broadcast transmitting apparatus, unless all the TS signals from the data output circuit 25 are analyzed,
It cannot be confirmed whether all data of the signal 101 is correct.

In the second system shown by the broken line, the data output circuit 25 inputs the generated TS signal 101 to the data processing circuit 22. The data processing circuit 22 performs data analysis and error analysis, and inputs the data analysis signal 104 to the display device control circuit 23 as an analysis signal 104. In the TV broadcast transmitting apparatus, the output state of the TS signal 101 from the data output circuit 25 is displayed in real time, and the user can confirm whether or not the content of the output TS signal 101 is correct.

[0009]

In the above-described conventional packet detection display device, the input state or the output state of the TS signal 101 is displayed by using the data processing circuit 22, the display device control circuit 23, the display device 24 and the like. . Here, since the data processing circuit 22 performs data analysis and error analysis,
It requires a data rate analysis circuit, a synchronization signal generation circuit, and the like, and the circuit configuration is complicated. Further, the display device control circuit 23 and the display device 24 are expensive because they correspond to the display of the data rate, the display of the synchronization detection result, and the like.

In the case of a TV broadcast receiving apparatus, there is an apparatus that displays only the result of synchronization detection without displaying the data rate, but the result of synchronization detection is irrelevant to the data rate.
It is difficult for the user to accurately grasp the input state of the TS signal.

In the case of the TV broadcast transmitting apparatus, according to the first method, the amount of data stored in the TS signal 101 is about several gigabytes, and a large storage capacity is required. It is the same as the device. Some devices do not have the display device 24, but it is difficult for the user to grasp the output state of the TS signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art.
An object of the present invention is to provide a packet detection and display device which is used to check the data rate of a packet signal having a packet structure such as a signal and the presence / absence of the packet signal and has a simple configuration.

[0013]

In order to achieve the above object, a packet detection and display device according to the present invention comprises: a synchronization signal generating circuit for generating a synchronization signal based on a bit string for synchronization of a packet signal; A frequency dividing circuit for dividing the signal at a predetermined ratio to generate a frequency-divided signal; and display means for displaying the frequency-divided signal, and displaying an input / output state of the packet signal based on the frequency-divided signal. It is characterized by doing.

In the packet detecting and displaying apparatus according to the present invention, the synchronizing signal generating circuit generates a synchronizing signal based on a bit string for synchronizing the packet signal having the packet structure, and the display means generates a synchronizing signal by dividing the frequency-divided signal. Since the occurrence state is displayed, the circuit configuration for confirming the data rate of the packet signal and the input / output state of presence / absence of the packet signal is simplified.

[0015] In the packet detection display device of the present invention, it is preferable that the display means includes a light emitting element and visually displays the input / output state. In this case, since a small-sized and low-cost LED can be adopted as the display means, the configuration is easy and the cost is low.

It is a preferable aspect of the present invention that the synchronizing signal generating circuit generates the synchronizing signal when detecting a synchronizing bit string from a predetermined area of the packet signal. In this case, it is possible to prevent erroneous detection occurring in a bit string included in an area other than the predetermined area of the packet signal.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a packet detecting and displaying apparatus according to the present invention. FIG. 1 is a block diagram of a packet detection display device according to the first embodiment of the present invention.

The packet detection display device of this embodiment is
For example, it is mounted on a device to which a TS signal is input from the outside or a device that outputs a generated TS signal to the outside. T
Devices to which the S signal is input from the outside include a TV broadcast receiver, a TS signal analyzer, a TS signal interface / data rate converter, and the like. A device for outputting the generated TS signal to the outside includes a TV broadcast transmitting device and a TS broadcast device.
There is a signal generator and the like.

FIG. 1A shows an example of application to a TV broadcast receiving apparatus. The packet detection display device has an input buffer 1,
It comprises a synchronization signal generating circuit 2, a frequency dividing circuit 3, a light emitting element control circuit 4, a light emitting element section 5, and a data processing circuit 6. The light emitting element section 5 is configured by a small light emitting element such as an LED. The light emitting element control circuit 4 and the light emitting element section 5 constitute a display unit.

The packet detection and display device includes an input buffer 1
, The TS signal 101 input from the outside is input to the synchronization signal generation circuit 2 and the data processing circuit 6. The data processing circuit 6 performs data analysis and error analysis,
It performs interface conversion and data rate conversion.
The data processing circuit 6 can input the analyzed or converted signal to another circuit and use the analyzed or converted signal. However, if only the input state indicating the data rate and the presence or absence of the TS signal 101 is checked, It can be omitted.

FIG. 2 shows the packet structure of the TS signal.
The TS signal includes a plurality of TSs each having a fixed length of 188 bytes.
Consists of packets. The TS packet includes a 4-byte header section and a 184-byte data section. The data section stores transmission information such as images, sounds, and data.

The header section includes an 8-bit synchronization section, a 3-bit indication section, a 13-bit PID section, a 4-bit control section, and a 4-bit counter section. A SYNC value of 0x47 (47 in hexadecimal) is assigned to the synchronization unit in advance as a synchronization bit string.

The synchronizing signal generating circuit 2 has a period counter, a coincidence comparing circuit, a SYNC detecting circuit, and an erroneous detection preventing circuit. The period counter, the match comparison circuit, the SYNC detection circuit, and the erroneous detection prevention circuit operate in synchronization with a clock generated for each byte of the TS packet. SYNC
The detection circuit converts the TS packet of the TS signal 101 into SYN
When the C value is detected, a detection pulse is generated. When recognizing the detection pulse, the cycle counter starts counting from 0. The cycle counter increments the count value by one for each byte of the TS packet, and the count value becomes 188.
When (the number of bytes of the TS packet), a count pulse is generated. The coincidence comparison circuit generates a synchronization signal 102 when the detection pulse and the count pulse are simultaneously generated. As a result, the synchronization signal generation circuit 2 outputs the TS signal 10
The synchronization signal 102 of one pulse is generated for every 188 bytes.

The SYNC detection circuit also generates a detection pulse when the value of the bit string stored in the data portion of the TS packet matches the SYNC value. The false detection prevention circuit
The SYNC detection circuit is controlled for the bit string in the data section, and the generation of the detection pulse is stopped. In addition, an erroneous detection pulse occurs with a probability of 1/256, the erroneous detection pulse has little effect on the display state of the light emitting element unit 5, and the erroneous detection may not occur due to the function of another circuit. So
The false detection prevention circuit can be omitted.

The synchronization signal generator 2 inputs the synchronization signal 102 to the frequency divider 3. The dividing circuit 3 outputs the synchronization signal 102
Is divided into 1 / N, and is input to the light emitting element control circuit 4 as a divided signal 103. The light emitting element control circuit 4 outputs the divided signal 1
A blink signal for driving the light emitting element is input to the light emitting element section 5 in synchronization with the pulse of 03. The light emitting element unit 5 emits light based on the blink signal, and the blink interval of the light emission changes in proportion to the data rate of the TS signal 101.

FIG. 1B shows an example of application to a TV broadcast transmitting apparatus. The packet detection display device includes a synchronization signal generating circuit 2, a frequency dividing circuit 3, a light emitting element control circuit 4, a light emitting element section 5,
It comprises a data output circuit 7 and an output buffer 8. The data output circuit 7 generates a TS signal 101 and inputs it to the output buffer 8 and the synchronization signal generation circuit 2. TS
The signal 101 has a data portion having a predetermined content. The output buffer 8 amplifies the TS signal 101 and outputs it to the outside of the packet detection display device.

The synchronizing signal generating circuit 2, the frequency dividing circuit 3, the light emitting element control circuit 4, and the light emitting element section 5 operate in the same manner as in the example applied to the TV broadcast receiving apparatus. The synchronization signal generating circuit 2
The generated synchronization signal 102 is input to the frequency dividing circuit 3 based on the signal 101. The frequency dividing circuit 3 divides the frequency-divided signal 103 based on the synchronization signal 102 into a light-emitting element control circuit 4.
To enter. The light emitting element control circuit 4 displays the output state of the TS signal 101 on the light emitting element section 5.

Here, the contents that can be confirmed by the user with the packet detection display device will be described. TS signal 101
Is used at a transmission rate of about 1 Mbit / s to 80 Mbit / s. Since the frequency dividing ratio N of the frequency dividing circuit 3 is set to a predetermined value, the blinking interval of the light emitting element unit 5 based on the frequency divided signal 103 can be visually recognized. Even if the user is not familiar with the TS signal, by seeing the light-emitting element unit 5 blinking,
The presence / absence of the TS signal can be determined, and by checking the blinking interval of the light emitting element unit 5 several times, it can be determined whether or not the same as the always used TS signal.

According to the above embodiment, the synchronization signal generation circuit generates the synchronization signal based on the synchronization bit string of the packet signal having the packet structure, and the display means generates the divided signal obtained by dividing the synchronization signal. Since the status is displayed, the circuit configuration for checking the data rate of the packet signal and the input / output status of the presence / absence of the packet signal is simplified.

Although the apparatus for inputting / outputting a TS signal has been described in the above embodiment, the same effect can be obtained for an apparatus for inputting / outputting a packet signal having a fixed-length packet structure having a bit string for synchronization allocated in advance. Is obtained.

As the display means, in addition to the visual method, an auditory method using sound can be adopted.

Although the present invention has been described based on the preferred embodiment, the packet detection and display device of the present invention comprises:
The present invention is not limited only to the configuration of the above-described embodiment, and includes packet detection and display devices obtained by making various modifications and changes from the configuration of the above-described embodiment.

[0033]

As described above, in the packet detecting and displaying apparatus of the present invention, the synchronizing signal generation circuit generates a synchronizing signal based on the synchronizing bit string of the packet signal having the packet structure, and the display means displays the synchronizing signal. Since the generation state of the frequency-divided signal obtained by dividing the frequency is displayed, the circuit configuration for checking the data rate of the packet signal and the input / output state of the presence / absence of the signal is simplified.

Further, since the device equipped with the packet detection display device employs a small and low-cost LED as the display means, the configuration is easy and inexpensive. Since it can be used as an additional function for easily checking the input / output state of the packet signal, the convenience is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a packet detection display device according to a first embodiment of the present invention.

FIG. 2 shows a packet structure of a TS signal.

FIG. 3 is a block diagram of a conventional packet detection display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 21 Input buffer 2 Synchronization signal generation circuit 3 Divider circuit 4 Light emitting element control circuit 5 Light emitting element part 6, 22 Data processing circuit 7, 25 Data output circuit 8, 26 Output buffer 23 Display control circuit 24 Display device 101 TS Signal 102 Synchronization signal 103 Divided signal 104 Analysis signal 105 All TS signal

Claims (3)

[Claims] 1. A synchronizing signal generating circuit for generating a synchronizing signal based on a bit string for synchronizing a packet signal, and a frequency dividing circuit for dividing the synchronizing signal at a predetermined ratio to generate a frequency-divided signal. And a display means for displaying the frequency-divided signal, and displaying the input / output state of the packet signal based on the frequency-divided signal. 2. The packet detection display device according to claim 1, wherein said display means includes a light emitting element and visually displays said input / output state. 3. The packet detection display device according to claim 1, wherein the synchronization signal generation circuit generates the synchronization signal when detecting a synchronization bit string from a predetermined area of the packet signal.