JP2002152041A - Feedback control circuit and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for unnecessary charges to an integration element so as to suppress a converging time of a feedback control system from being increased even when the feedback control system becomes open in excess of a dynamic range. SOLUTION: An output limiter 8 is provided to a compensation filter 7 of a feedback control loop, when a filter output exceeds the limit value, the output limiter 8 activates an integration element limiter 9 so as to stop the operation of an integration element of the filter 7 thereby holding the state of the integration element. Thus, even when a large error in excess of the dynamic range is detected, unnecessary charge to the integration element is eliminated so as to prevent the converging time of the control system from being increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a feedback control circuit and a PLL (Phase Locked Loop) circuit, and more particularly to a feedback control circuit suitable for use in a PLL circuit for clock recovery in a digital signal processing device.

[0002]

2. Description of the Related Art As one of apparatuses for digitizing a video signal and performing various processing, there is, for example, a direct super apparatus. This direct super apparatus is an apparatus for switching a plurality of input digital serial video signals (a plurality of video materials) into TS (time sharing), and has an outline shown in FIG. .

[0005] Referring to FIG. 5, there are two input sources, and digital serial inputs A and B are supplied to the apparatus 10. First, an S / P (serial / parallel) converter 11 performs parallel conversion, and in response to a switching signal supplied from outside, a data selector 12.
, And is supplied to the data processing unit 13. The data processing unit 13 temporarily stores the input data in a buffer memory and performs necessary digital data processing. Thereafter, the data is output to the outside as serial data via a P / S (parallel / serial) converter 14. It is supposed to be.

The data processing unit 13 and the P / S converter 14
The operation is performed by the clock signal generated by the LL circuit 16, and the reference clock input to the PLL circuit 16 is also switched by the switch unit 15 in response to the switching timing of the data selector 12. The reference clock, which is an input to the PLL circuit 16, is reproduced from the data string of the digital data input A or B, and the reproduction section is not shown particularly in FIG.

Here, the data rates of the input materials (serial data) A and B have a deviation of about ± 30 ppm, and the phase relationship between them is completely arbitrary.
Under such conditions, the material and the clock are switched. The switching is performed without using the PLL circuit 16 as shown in FIG. 5 and the switching is performed using the PLL circuit 16. Input clocks A,
FIG. 6 shows the relationship between B and the output clock after switching.
FIG. 6A shows the case without the PLL circuit, and FIG.
Is the case with the PLL circuit. The clock is represented as an impulse train for simplicity.

Here, clock A indicates a clock synchronized with the material A, clock B indicates a clock synchronized with the material B, TA and TB indicate the periods of the clocks A and B, and T1 and T2.
, T3 denote the output clock cycle before clock switching, the output clock cycle immediately after switching, and the clock cycle after switching, respectively.

When the PLL circuit shown in FIG. 6A is not used, the period T1 before switching of the output clock is T1 = TA.
And the cycle T3 after the switching is T3 = TB. However, the period T2 immediately after the switching may be T2 << TB depending on the switching timing and the input clocks A and B as shown in FIG.
And the circuit operation of the P / S converter 14 and the like cannot follow, causing a problem that the seamless switching between the materials, which is the basis of the operation of the direct super apparatus, cannot be performed.

[0008] Therefore, as shown in FIG.
The use of No. 6 causes the PLL output clock to follow while gradually adjusting the clock cycle before and after the switching, as shown in FIG. 6B, so that the above-described problem does not occur.

[0009]

In an actual direct super apparatus, as shown in FIG. 7, the apparatus 10 shown in FIG. 5 is connected in cascade (10-1, 10-2) to switch the material. Sometimes it is heavy. In such a case, if the pull-in operation of the PLL circuit 16 is oscillatory, the next-stage device (10
-2) adversely affects the operation of the PLL circuit.

That is, by cascade connection of PLL circuits,
The jitter of individual PLL circuits accumulates and poses a serious problem. In order to suppress the accumulation of the jitter, there is a method of setting a large damping constant (attenuation constant) similarly to a general feedback control system. However, when the damping constant is increased, there is a problem that the convergence time of the control system is lengthened.

In order to solve this problem, a method of setting a large system gain of the control system can be considered. However, the control system has a finite dynamic range, and when the dynamic range is exceeded, an integral element is generated. A new problem arises that the convergence time of the control system is increased by the integral value that does not contribute to the control operation.

An object of the present invention is to provide a feedback system capable of suppressing an increase in convergence time of a control system by eliminating unnecessary charge to an integral element even when the control system is opened beyond a dynamic range. Control circuit and PLL
Is to provide a circuit.

[0013]

According to the present invention, a deviation between an input reference signal and a controlled signal is detected, and a control signal corresponding to the deviation is generated through a compensation filter of a feedback loop. A feedback control circuit for correcting a deviation of the controlled signal from the reference signal by the control signal, wherein a filter stop control means for stopping the operation of the compensation filter when the control signal exceeds a predetermined value. Is obtained.

The filter stop control means includes a comparison means for comparing the control signal with the predetermined value, and an integration element stop control means for stopping and controlling the operation of the integration element of the compensation filter according to the comparison result. And characterized in that:

The integral element stop control means is configured to stop supplying electric charge to the integral element when the control signal exceeds a predetermined value, and the control signal is controlled to a predetermined value. , The time constant of the compensation filter is set to be larger than that in the normal operation.

According to the present invention, a phase difference between an input reference clock signal and an oscillation clock of a voltage controlled oscillator is detected, and a voltage control signal corresponding to the phase difference is generated through a loop filter to generate the voltage control signal. And a filter stop control means for stopping the operation of the loop filter when the voltage control signal exceeds a predetermined value. Is obtained.

[0017] The filter stop control means includes a comparison means for comparing the voltage control signal with the predetermined value;
And an integral element stop control means for stopping and controlling the operation of the integral element of the loop filter according to the comparison result.

The integral element stop control means stops the supply of electric charge to the integral element when the voltage control signal exceeds a predetermined value,
Further, when the control signal exceeds a predetermined value, the time constant of the loop filter is set to be larger than that in the normal operation.

The operation of the present invention will be described. An output limiter is provided in the compensation filter and the loop filter of the feedback control loop, and when the filter output exceeds the limiter value, the operation of the integration element of the filter is stopped to maintain the state of the integration element. It is. As a result, even if a large error amount exceeding the dynamic range is detected, unnecessary charging of the integration element is eliminated, and an increase in the convergence time of the control system can be suppressed.

Therefore, even when a plurality of PLL circuits, which are feedback control circuits, are cascade-connected as in the above-described direct super apparatus, a seamless switching operation of the materials can be performed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, a reference signal 1 and a controlled signal 2 are input to an error comparator 3 to detect an error amount (deviation amount) between the two signals. Is entered. Compensation filter unit 6
In the compensation filter 7, the signal indicating the error amount is subjected to the reduction gain compensation. The output of the compensating filter 7 is input to the gain amplifier 4 via the output limiter 8 to provide the necessary amplification for the feedback control system.

The output of the gain amplifier 4 is input to the control amplifier 5 as a control signal, and the amount of error of the controlled signal 2 with respect to the reference signal 1 is controlled according to the control signal. Thus, a feedback control system is formed.

The output limiter 8 of the compensating filter section 6 detects that the output of the compensating filter 7 has exceeded the dynamic range (predetermined value), and operates the integral element limiter 9. That is, when the output of the compensation filter 7 exceeds the dynamic range and the control system is opened,
The integration element limiter 9 operates to stop the operation of the integration element of the compensation filter 7 (that is, stop the integration operation).

Accordingly, when the error amount by the error comparator 3 becomes large and the control system is opened beyond the dynamic range, unnecessary charge to the integral element can be eliminated, and the convergence time of the control system can be reduced. The increase is suppressed.

FIG. 2 is a view showing an embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2, the feedback control circuit is a PLL circuit. In FIG. 2, a reference clock 1 and a controlled clock 2 which is an oscillation output of a VCO (voltage controlled oscillator) 5 are input to a phase comparator 3 and a phase difference between the two is detected. This phase difference signal is input to a compensation filter unit 6 as a PLL loop filter.

The phase difference signal is reduced and gain-compensated by the compensation filter 7 of the compensation filter section 6, and the output limiter 8
Is supplied to the gain amplifier 4 via the. Gain amplifier 4
In the above, the amplification degree required for the control system is provided. The output of the gain amplifier 4 becomes a voltage control signal of the VCO 5,
The controlled clock 2 output from the VCO 5 is output as a clock whose frequency and phase are controlled in accordance with the voltage control signal.

In this way, the phases of the reference clock 1 and the controlled clock 2, which is the output of the VCO, match. Therefore,
This VCO output clock can be supplied as an operation clock of the data processing unit 13 and the like as an output clock of the PLL 16 in FIG.

Output limiter 8 in compensation filter section 6
Detects that the output of the compensation filter 7 exceeds a predetermined limit value (reference value), limits the output of the compensation filter 7 to this limit value, and simultaneously outputs a limiter operation signal. Upon receiving the limiter operation signal, the integral element limiter 9 disconnects the capacitor as an integral element in the compensation filter 7 from the circuit to stop the integral operation.

A more specific operation will be described. In FIG. 2, a phase comparator 3 detects a phase difference between a controlled clock and a reference clock 1 and outputs a phase error signal. That is, when the phase of the controlled clock lags behind the reference clock, a positive voltage is output in proportion to the delay amount. If it is advanced, a negative voltage is output in proportion to the amount of advance.

The compensating filter 7 receives the output of the phase comparator 3 and emphasizes the low frequency range of the signal and outputs the signal. The output limiter 8 is supplied with a predetermined limit reference value, and when the output of the compensation filter exceeds the limit reference value,
The output of the compensation filter 7 is fixed at this limit value. The output limiter 8 performs a limit operation and outputs a limit operation signal indicating that the limit operation is being performed. The integral element limiter 9 receives the limit operation signal and disconnects the integral element in the compensation filter 7 from the circuit.

The output of the output limiter 8 becomes a voltage control signal of the VCO 5 via the gain amplifier 4,
Is controlled.

FIG. 3 is a circuit diagram showing a specific example of the block shown in FIG. 2, and the same parts as those in FIG. 2 are denoted by the same reference numerals.
3, the compensation filter 7 includes operational amplifiers 71 and 72.
And a capacitor 73, which is an integral element, and resistors 74 to 76.
And an adder 77.

The output limiter 8 comprises an operational amplifier 81, a diode 82, and a resistor 83. When the output of the compensation filter 7 exceeds the limit reference value, the diode 82 provided at the output of the operational amplifier 81 is turned on, and the compensation is performed. The output of the filter 7 is limited to a voltage value determined by the ON voltage of the ON diode.

At the same time, a signal indicating that the limit operation is being performed is supplied from the output of the operational amplifier 81 to the switch 9 (which is normally off), the switch 9 is turned on, and the integrator including the operational amplifier 7 and the capacitor 73 is provided. Input is ground. As a result, the operation of the integrator stops, and the capacitor 73 is no longer charged.
The state immediately before is maintained.

FIG. 4 is a circuit diagram showing another specific example of the block in FIG. 2, and the same parts as those in FIGS. Only the portions different from FIG. 3 will be described.
A switch 9 operated by a signal indicating that the output limiter 8 is performing a limit operation operates so as to switch the integration time constant of the compensation filter 7.

That is, at the time of normal operation, the switch 9 is turned on, so that the resistor 78 is inserted in parallel with the resistor 74, so that the time constant of the integrating circuit is small. However, when the output limiter 8 operates,
The switch 9 is turned off, so that the resistor 78 is disconnected, and the integration time constant becomes larger. As a result, the operation of the integration circuit can be regarded as equivalently stopped, and the same effect as that of the circuit of FIG. 3 can be obtained.

[0037]

As described above, according to the present invention, when an operation exceeding the dynamic range of the control system occurs, the operation of the integration element in the compensation filter is stopped. The state of the element is maintained at the state immediately before exceeding the dynamic range, so that when the control system exceeds the dynamic range and returns to the dynamic range again, the control system starts operating from the state immediately before. As a result, there is an effect that extension of the convergence operation time is suppressed. That is, there is an effect that the extension of the convergence time of the control system due to the integral value not contributing to the control operation during the period exceeding the dynamic range is eliminated.

Further, the feedback control system P
In a device that uses LL circuits connected in cascade in multiple stages,
In particular, since the convergence time is not extended, even if the reference input clock signal is frequently switched, the phase of the PLL output clock accurately follows the switched clock, so that the operation of the digital processing device using the clock can be accurately performed. This has the effect that signal quality degradation can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a specific circuit of FIG. 2;

FIG. 4 is a diagram showing another example of the specific circuit of FIG. 2;

FIG. 5 is a diagram schematically illustrating a direct super apparatus using a PLL circuit.

6 is a diagram showing an operation state of a PLL circuit in the device of FIG.

FIG. 7 is a diagram showing an example of use of the device of FIG. 5;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reference signal 2 controlled signal 3 error comparator (phase comparator) 4 gain amplifier 5 control amplifier (VCO) 6 compensation filter unit 7 compensation filter 8 output limiter 9 integration element limiter

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H04N 5/12 H03L 7/08 E

Claims (8)

[Claims] An amount of deviation between an input reference signal and a controlled signal is detected, a control signal corresponding to the amount of deviation is generated through a compensation filter of a feedback loop, and the control signal is used to generate the control signal. A feedback control circuit configured to correct a deviation from a reference signal, comprising: a filter stop control unit that stops the operation of the compensation filter when the control signal exceeds a predetermined value. . 2. The filter stop control unit includes: a comparison unit that compares the control signal with the predetermined value; and an integration element stop control unit that stops and controls the operation of the integration element of the compensation filter according to a result of the comparison. The feedback control circuit according to claim 1, comprising: 3. The feedback control circuit according to claim 2, wherein said integration element stop control means stops supply of electric charge to said integration element when said control signal exceeds a predetermined value. . 4. The system according to claim 1, wherein said integral element stop control means sets a time constant of said compensation filter to be larger than that in a normal operation when said control signal exceeds a predetermined value. Item 3. The feedback control circuit according to Item 2. 5. A phase difference between an input reference clock signal and an oscillation clock of a voltage controlled oscillator is detected, a voltage control signal corresponding to the phase difference is generated through a loop filter, and the voltage control signal is generated by the voltage control signal. A PLL circuit for controlling an oscillator, comprising: filter stop control means for stopping the operation of the loop filter when the voltage control signal exceeds a predetermined value. 6. A filter stop control means for comparing the voltage control signal with the predetermined value, and an integral element stop control for stopping the operation of the integral element of the loop filter in accordance with a result of the comparison. 6. The PLL circuit according to claim 5, further comprising means. 7. The PLL circuit according to claim 5, wherein said integration element stop control means stops supply of electric charge to said integration element when said voltage control signal exceeds a predetermined value. . 8. The apparatus according to claim 1, wherein said integral element stop control means sets a time constant of said loop filter to be larger than that in a normal operation when said control signal exceeds a predetermined value. Item 7. The PLL circuit according to Item 6.