JP2002151683A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a stable cobalt silicide film. SOLUTION: A gate electrode 4 is formed on a semiconductor substrate 1 through a gate oxide film 3, and a side wall insulating film 8 is so formed as to cover the side wall of the gate electrode 4 and also to comprise a step at a corner of a substrate surface. Due to the step, no excessive cobalt film (cobalt atom) is required to be supplied at the part, and abnormal growth of a cobalt silicide film 11B is suppressed under the side wall insulating film 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique for forming a silicide film in a silicide process of a semiconductor device.

[0002]

2. Description of the Related Art In a recent semiconductor device, a high melting point metal silicide film is formed selectively and self-aligned on a gate electrode made of a polysilicon film of a MOS transistor and a surface layer of a source / drain region formed on a silicon substrate. so,
The wiring resistance of the gate electrode and the parasitic resistance of the source / drain regions are reduced, thereby suppressing wiring delay and deterioration of conductance.

A typical example of the refractory metal silicide film is a titanium silicide film (TiSi ₂ film).
It has been known.

In recent years, a cobalt silicide film (CoSi ₂ film) process has been attracting attention instead of the titanium silicide film process in which a rise in resistance in a thin wire portion is a problem.

Hereinafter, a general process of forming a CoSi ₂ film will be described with reference to the drawings.

First, as shown in FIG. 14, an element isolation film 52 is formed on a semiconductor substrate 51 of one conductivity type, for example, a P type, and a gate oxide film 5 is formed on an active region defined by the element isolation film.
3, a gate electrode 54 is formed, and this gate electrode 5
A source / drain region 55 of a low concentration of the opposite conductivity type (N type) is formed in the surface layer of the substrate so as to be adjacent to the region 4. Subsequently, after forming a side wall insulating film 56 on the side wall of the gate electrode 54, a high concentration source / drain region 57 of a reverse conductivity type (N type) is formed on the surface of the substrate so as to be adjacent to the side wall insulating film 56.
To form Then, a cobalt film (Co film) is formed on the entire surface of the substrate.
58 is formed by sputtering.

Subsequently, as shown in FIG. 15, the cobalt film 58 is subjected to a heat treatment (rapid thermal annealing, hereinafter referred to as RTA) to form the gate electrode 54 and a source electrode.
By selectively silicifying the surface layer of the drain region 57 in a self-aligned manner, cobalt silicide (CoSi ₂ )
A film 59 is formed.

Then, although not shown, after forming an interlayer insulating film on the entire surface, a contact hole is formed on the source / drain region 57 (via the cobalt silicide film 59), and the source / drain region 57 is formed.
A metal wiring is formed thereon via a barrier metal film.

[0009]

As a problem of the above-described cobalt silicide film process, there is an abnormal growth (crawling phenomenon) of the cobalt silicide film 59A under the sidewall insulating film 56 as shown in FIG.

[0010] For this reason, a junction leak and a leak at a channel portion occur. Note that this is because the cobalt film enters the silicon as a reaction as shown in FIG. 17 (cobalt atoms shown by black circles in the figure cannot enter the side wall insulating film 56 side), and thus the vicinity of the side wall insulating film 56 As a result, the supply amount of the cobalt film increases, and the cobalt silicide film grows abnormally under the sidewall insulating film 56.

This abnormal growth causes fatal leakage when the design rule is reduced and the junction depth becomes shallow, thereby deteriorating the device characteristics.

Accordingly, an object of the present invention is to provide a technique for forming a stable cobalt silicide film.

[0013]

SUMMARY OF THE INVENTION In view of the above problems, a semiconductor device and a method of manufacturing the same of the present invention have a gate electrode formed on a semiconductor substrate via a gate oxide film and cover the side wall of the gate electrode. Then, a sidewall insulating film is formed so as to have a step at a corner with respect to the substrate surface. Then, due to the presence of the step, the supply of the cobalt film (cobalt atoms) more than necessary at this portion is stopped, and the abnormal growth of the cobalt silicide film under the sidewall insulating film is suppressed.

The semiconductor device and the method of manufacturing the same according to the present invention are also applicable to a nonvolatile semiconductor memory device having a floating gate and a control gate on a semiconductor substrate.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described with reference to the drawings.

First, as shown in FIG. 1, one conductivity type, for example,
An element isolation film 2 is formed on a P-type semiconductor substrate 1.
Approximately 10 nm film on the active region determined by the separation film 2
Approximately 200 nm to 300 nm through the thick gate oxide film 3
A gate electrode 4 having a thickness of nm is formed. In addition, the game
A reverse conductivity type on the surface of the substrate so as to be adjacent to the
Phosphorus ions, which are N-type impurities, have a dose of about 1.0 to
2.0 × 10¹³/ Cm ^TwoWith an accelerating voltage of 35 to 45 KeV
By implanting and annealing under implantation conditions, low concentration
Source / drain regions 5 are formed. In addition, ion implantation
Arsenic ions or the like may be used as the N-type impurities to be formed.
No.

Subsequently, as shown in FIG. 2, a silicon oxide film 6A (for example, TEOS (Tetra Et
hylOrtho Silicate) film, and then a silicon nitride film 7A having a thickness of about 10 nm is formed by the CVD method.

Next, as shown in FIG. 3, the silicon nitride film 7A and the silicon oxide film 6A are anisotropically etched to form a double side wall insulating film 8A composed of the silicon oxide film 6 and the silicon nitride film 7. I do. Then, an N-type impurity such as arsenic ion is added to the surface layer of the substrate so as to be adjacent to the side wall insulating film 8A at a dose of about 1.0 to 2.0 × 10 ¹³ /.
A high concentration source / drain region 9 is formed by implanting and annealing under implantation conditions of cm ² and an acceleration voltage of 35 to 45 KeV. As a double-layered side wall insulating film,
It may be composed of a silicon nitride film and a silicon oxide film whose film forming order is reversed. In addition, the ion-implanted N
Phosphorus ions or the like may be used as the type impurity.

Next, as shown in FIG. 4, as a pre-sputtering process for a cobalt film, which will be described later, the lower silicon oxide film 6 constituting the side wall insulating film 8A is partially removed with hydrofluoric acid (HF) to remove the gate electrode 4. Steps (recesses) are formed in two places, a place in contact with the upper part and a place in contact with the substrate surface. When a side wall insulating film made of a silicon nitride film and a silicon oxide film whose film forming order is opposite to that of the side wall insulating film 8A is used,
The underlying silicon nitride film is partially removed by phosphoric acid (H ₃ PO ₃ ) to form a depression in the same manner. As described above, the side wall insulating film 8 having a step (recess) is formed by utilizing the etching rate difference between the silicon oxide film and the silicon nitride film.

Subsequently, as shown in FIG. 5, a film to be silicided, for example, a cobalt film (Co film) 10 is formed on the entire surface by about 1 μm.
Sputtering is performed with a thickness of 0 nm, and heat treatment (rapid thermal annealing, hereinafter referred to as RTA) is applied to achieve silicidation. At this time, the cobalt film 10 loses continuity due to insufficient coverage at least at a corner formed by the sidewall insulating film 8 and the substrate surface, reflecting the shape of the sidewall insulating film 8. Therefore, the supply of the cobalt film (cobalt atoms) more than necessary in this portion is eliminated, and the abnormal growth of the cobalt silicide (CoSi ₂ ) film under the sidewall insulating film 8 is eliminated. The height of the step (the height from the substrate surface to the bottom of the side wall insulating film 8) is set to 20 because the thickness of the cobalt film 10 to be formed by sputtering is 10 nm.
nm is sufficient. Furthermore, when forming a cobalt film by sputtering, an ion metal plasma (IMP) method having a high directivity or a long throw sputtering (LTS) method is used.
It is preferable to apply a sputtering method such as a sputtering method.

Then, by removing the unreacted cobalt film 10 and the cobalt reactant (CoN film) remaining on the element isolation film 2 and the side wall insulating film 8, the upper surface of the gate electrode 4 is removed as shown in FIG. Cobalt silicide (CoSi ₂ )
A film 11A is formed, and a cobalt silicide (CoSi ₂ ) film 11B is formed on the surface of the source / drain region 9.
To form

The RTA process is performed in two steps so that excessive silicidation does not proceed. That is, the first RTA treatment is performed at about 450 ° C. to 600 ° C. for 10 to
After performing about 45 seconds to remove the unreacted cobalt film 10 and the cobalt reactant (CoN film), a second RTA treatment is performed at approximately 750 ° C. to 850 ° C. for 10 to 45 seconds.
Going about a second.

As described above, in the present invention, the structure of the side wall insulating film 8 formed on the side wall of the gate electrode 4 has a step (dent) at least at a corner formed by the side wall insulating film 8 and the substrate surface. In this case, the continuity of the cobalt film 10 is lost due to lack of coverage in this portion, the supply of unnecessary cobalt film (cobalt atoms) in this portion is eliminated, and the cobalt silicide near the side wall insulating film as in the related art is eliminated. The creeping phenomenon of the film can be suppressed, the junction leak and the leak at the channel portion can be suppressed, and the process margin for forming the cobalt silicide film can be increased.

In this embodiment, the process of forming the cobalt silicide film in the gate electrode portion (near the side wall insulating film) has been described as an example. However, the present invention is not limited to this. For example, the so-called shallow trench method (STI) Law)
The present invention can also be applied to a device that suppresses abnormal growth of a cobalt silicide film near the element isolation film formed by the method described above.

Although illustration is omitted, an interlayer insulating film made of a BPSG film having a thickness of about 600 nm is formed on the entire surface, and then formed on the source / drain region 9 (via the cobalt silicide film 11B). A) forming a contact hole for contact; Then, a contact plug (for example, made of a tungsten film) is formed in the contact hole via a barrier metal film (for example, a laminated film of a titanium film and a titanium nitride (TiN) film),
A metal film (for example, an Al film, A
An l-Si film, an Al-Cu film, and an Al-Si-Cu film are formed to form a metal wiring. Note that, for example, an Al film, an Al-Si film, an Al-C
A metal wiring composed of a u film and an Al—Si—Cu film may be formed. Finally, a jacket film is formed on the entire surface to complete the semiconductor device.

Hereinafter, another embodiment in which the present invention is applied to a nonvolatile semiconductor memory device having a floating gate and a control gate and a method of manufacturing the same will be described with reference to the drawings.

First, as shown in FIG. 7, after a device isolation film (not shown) is formed in a predetermined region of a P-type semiconductor substrate 21, a gate oxide film 22 is formed on a surface layer other than the device isolation film to a thickness of about 7 nm. It is formed to a thickness of 15 nm. Then, a polysilicon film is formed on the gate oxide film 22 by about 100 n.
A silicon nitride film 24 having an opening is formed on the conductive film 23 formed to a thickness of m to 200 nm and doped with phosphorus in the polysilicon film.

Subsequently, using the silicon nitride film 24 as a mask, the conductive film 23 is formed by LOCOS (Local Oxidation Of S
A selective oxidation film 25 is formed by selective oxidation by the silicon (ilicon) method.

Next, as shown in FIG. 8, the conductive film 23 is anisotropically etched using the selective oxide film 25 as a mask to form a floating gate (F) under the selective oxide film 25.
G) Form 26. At this time, a sharp corner is formed above the floating gate 26, reflecting the shape of the selective oxide film 25. At the time of an erasing operation in which electrons (charges) stored in the floating gate 26 are drawn out to the control gate through a tunnel oxide film 28 to be described later, an electric field is concentrated on this corner, and the corner is moved from the floating gate 26 to the control gate. This facilitates the movement of electrons (charges) and improves the erasing efficiency. In the anisotropic etching process described above, the gate oxide film 22 except for the portion under the selective oxide film 25 may be removed by etching, but in the present embodiment, a predetermined amount of the remaining film (oxide film 22A) is left.

Further, as shown in FIG. 9, a portion where a drain region is to be formed is covered with a resist film (not shown), and using this resist film as a mask, an N-type impurity, for example, phosphorus ions, is applied to the surface layer of the substrate at a dose of about 4.5. ~ 5.0 × 10 ¹⁵ / c
The source region 27 is formed by being implanted under an implantation condition of m ² and an accelerating voltage of 50 to 70 KeV, and is diffused by annealing. Note that arsenic ions or the like may be used as the N-type impurities to be ion-implanted.

Subsequently, the gate oxide film 2 is formed so as to cover the floating gate 26 as shown in FIG.
About 20 nm to 40 n formed integrally with 2A
An insulating film (hereinafter, referred to as a tunnel oxide film 28) is formed. The tunnel oxide film 28 is formed on the oxide film 22A and the floating gate 26 by a CVD method using a CVD oxide film, for example, a CoSi2 film 11 or HTO (High Tempe).
It is formed by forming a film and the like and then thermally oxidizing it.

Next, a polysilicon film having a thickness of, for example, about 200 nm to 300 nm is formed on the tunnel oxide film 28, and the polysilicon film is doped with phosphorus using POCl ₃ as a diffusion source. Then, a resist film (not shown) is formed, and the polysilicon film is patterned using the resist film as a mask.
A control gate (CG) 29 is formed on one end side of the device so as to extend from the upper portion to the side wall portion.

Further, a silicon oxide film (for example, about 10 nm thick) is formed on the entire surface of the substrate 21 by CVD.
A TEOS (Tetra Ethyl Ortho Silicate) film is formed, a silicon nitride film having a thickness of about 10 nm is formed by CVD, and the silicon nitride film and the silicon oxide film are anisotropically etched to form a silicon oxide film 30. Double-layered sidewall insulating film 32 composed of silicon and silicon nitride film 31
Form A. Then, while the source region 27 is masked with a resist film (not shown), an N-type impurity, for example, phosphorus ions, is implanted into a portion where a drain region is to be formed at a dose of about 1.0 to 2.0 × 10 ¹³ / cm ^{2 at} an accelerating voltage. 35-45
The drain region 33 is formed in the surface layer of the substrate so as to be adjacent to the side wall insulating film 32A by performing an implantation process and an annealing process under the implantation condition of KeV. Note that arsenic ions or the like may be used as the N-type impurities to be ion-implanted. Note that the double-layered sidewall insulating film may be formed of a silicon nitride film and a silicon oxide film whose film forming order is reversed.

Next, as shown in FIG. 12, as a pre-sputtering process for the cobalt film described later, the lower silicon oxide film 30 constituting the side wall insulating film 32A is partially removed by hydrofluoric acid (HF) to remove the control gate 29. Steps (recesses) are formed in two places, a place in contact with the upper part and a place in contact with the substrate surface. When a side wall insulating film composed of a silicon nitride film and a silicon oxide film whose film formation order is opposite to that of the side wall insulating film 8A is used, the lower silicon nitride film is formed by phosphoric acid (H ₃ PO ₃ ). By removing the part, a step (dent) is similarly formed. As described above, the sidewall insulating film 32 having a step (recess) is formed by utilizing the etching rate difference between the silicon oxide film and the silicon nitride film. FIG. 12 (FIG. 13 described later)
Is an enlarged view of only the drain region, and the features of the present invention will be described with reference to these drawings. The same applies to the source region side.

Subsequently, as shown in FIG. 12, a film to be silicided, for example, a cobalt film (Co film) 34 is sputtered to a thickness of about 10 nm on the entire surface and heat-treated (rapid thermal annealing, hereinafter referred to as RTA). To achieve silicidation. At this time, the cobalt film 34
Indicates the shape of the sidewall insulating film 32 and reflects the shape of the sidewall insulating film 3.
The continuity is lost due to insufficient coverage at the corner formed by the surface 2 and the substrate surface. Therefore, the supply of the cobalt film (cobalt atoms) more than necessary in this portion is eliminated, and the abnormal growth of the cobalt silicide (CoSi ₂ ) film under the sidewall insulating film 32 is eliminated. The height of the step (the height from the surface of the substrate to the bottom of the side wall insulating film 8) is 20 n because the thickness of the cobalt film 10 to be formed by sputtering is 10 nm.
m is enough. Furthermore, when forming a cobalt film by sputtering, an ion metal plasma (I
It is preferable to apply a sputtering method such as an MP) method or a long throw sputtering (LTS) method.

Then, by removing the unreacted cobalt film 34 and the cobalt reactant (CoN film) remaining on the element isolation film and the side wall insulating film 32, the cobalt is deposited on the upper surface of the control gate 29 as shown in FIG. A silicide (CoSi ₂ ) film 35A is formed, and a cobalt silicide (CoSi ₂ ) film 35B is formed on the surface layer of the source / drain regions 27 and 33.

The RTA process is performed in two steps so that excessive silicidation does not proceed. That is, the first RTA treatment is performed at about 450 ° C. to 600 ° C. for 10 to
After removing the unreacted cobalt film 34 and the cobalt reactant (CoN film) for about 45 seconds, a second RTA process is performed at approximately 750 ° C. to 850 ° C. for 10 to 45 seconds.
Going about a second.

As described above, according to the present invention, the side wall insulating film 32 formed on the side wall of the control gate 29 is formed.
By providing a step (dent) at least at a corner formed by the side wall insulating film 32 and the substrate surface, the lack of coverage at this portion eliminates the continuity of the cobalt film 34, and this structure is more than necessary. Supply of the cobalt film (cobalt atoms) of the above, the phenomenon of creeping down of the cobalt silicide film near the side wall insulating film as in the prior art can be suppressed, junction leakage and leakage at the channel portion are suppressed, and formation of the cobalt silicide film The process margin can be increased.

Although not shown, approximately 60
After forming an interlayer insulating film made of a BPSG film having a thickness of 0 nm, a contact hole is formed on the source / drain regions 27 and 33 (via a cobalt silicide film 35B). Then, a contact plug (for example, composed of a tungsten film) is formed in the contact hole via a barrier metal film (for example, a laminated film of a titanium film and a titanium nitride (TiN) film), and a metal is formed on the contact plug. Film (for example, Al film, Al-S
i film, Al-Cu film, Al-Si-Cu film) to form metal wiring. Note that, for example, an Al film, an Al—Si film, an Al—Cu film,
A metal wiring formed of an Al-Si-Cu film may be formed. Finally, a jacket film is formed on the entire surface to complete the semiconductor device.

[0040]

According to the present invention, the abnormal growth of the cobalt silicide film under the side wall insulating film formed on the side wall of the gate electrode can be suppressed, so that the occurrence of junction leak can be suppressed. The margin of the process for forming the cobalt silicide film can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 10 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 11 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 12 is a sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 15 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 16 is a diagram for explaining a conventional problem.

FIG. 17 is a diagram for explaining a conventional problem.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 27/115 H01L 29/78 371 29/788 29/792 F term (Reference) 4M104 AA01 BB01 BB14 BB20 CC01 CC05 DD04 DD19 DD26 DD29 DD37 DD79 DD80 DD84 EE05 EE08 EE09 EE17 FF06 FF13 FF14 FF17 FF18 FF22 GG09 GG16 HH04 HH16 5F001 AA21 AA22 AA33 AA63 AB03 AB04 AC20 AF25 AG28 AG30 5F040 DA14 EA08 EC01 EC02 EC07 EP13 FA02 FA02 GA06 GA27 GA30 JA02 JA32 JA35 JA36 JA39 JA40 JA53 JA56 PR05 PR12 PR21 PR22 PR34 PR36 5F101 BA03 BA04 BA15 BA36 BB04 BB08 BC03 BF09 BH13 BH16

Claims (8)

[Claims] A gate electrode formed on a semiconductor substrate via a gate oxide film, a side wall insulating film formed on a side wall of the gate electrode, and a surface layer of the substrate adjacent to the side wall insulating film. In a semiconductor device having a formed source / drain region and a cobalt silicide film formed on the source / drain region, the sidewall insulating film is formed so as to have a step at least at a corner portion with the substrate surface. A semiconductor device characterized by being performed. 2. A semiconductor device having a floating gate formed on a semiconductor substrate via a gate oxide film and a region overlapping the floating gate via an insulating film formed so as to cover the floating gate. A control gate, a side wall insulating film formed so as to cover at least the floating gate or the side wall of the control gate, and an impurity diffusion region formed in the surface layer of the substrate adjacent to the side wall insulating film. A semiconductor device comprising: a cobalt silicide film formed on the impurity diffusion region; wherein the side wall insulating film is formed so as to have a step at least at a corner with the substrate surface. apparatus. 3. The semiconductor device according to claim 1, wherein the side wall insulating film has a double structure including a silicon oxide film and a silicon nitride film. 4. A gate electrode formed on a semiconductor substrate via a gate oxide film, a side wall insulating film formed on a side wall portion of the gate electrode, and a surface layer of the substrate adjacent to the side wall insulating film. A method for manufacturing a semiconductor device having the source / drain regions formed, wherein a step is formed at least at a corner of the sidewall insulating film with respect to the substrate surface; and a heat treatment is performed after forming a cobalt film over the entire substrate. Forming a cobalt silicide film on the gate electrode and the source / drain regions. 5. A semiconductor device having a floating gate formed on a semiconductor substrate via a gate oxide film and a region overlapping the floating gate via an insulating film formed to cover the floating gate. A control gate, a side wall insulating film formed so as to cover at least the floating gate or the side wall of the control gate, and an impurity diffusion region formed in the surface layer of the substrate adjacent to the side wall insulating film. A method of manufacturing a semiconductor device comprising: a cobalt silicide film formed on the impurity diffusion region; a step of forming a step at least at a corner of the side wall insulating film with the substrate surface; The gate electrode and the source / drain are formed by heat treatment after forming a film. Method of manufacturing a semiconductor device characterized by being a step of forming a cobalt silicide film on the region. 6. A gate electrode formed on a semiconductor substrate via a gate oxide film, a side wall insulating film formed on a side wall of the gate electrode, and a surface layer of the substrate adjacent to the side wall insulating film. In the method for manufacturing a semiconductor device having the formed source / drain regions, the side wall insulating film is composed of a plurality of insulating films made of different materials, and a difference in an etching rate between these insulating films is used.
Forming a step at least at a corner of the side wall insulating film with the substrate surface, and forming a cobalt film on the entire surface of the substrate and then performing a heat treatment to form a cobalt silicide film on the gate electrode and the source / drain regions. Forming a semiconductor device. 7. A semiconductor device having a floating gate formed on a semiconductor substrate via a gate oxide film and a region overlapping the floating gate via an insulating film formed to cover the floating gate. A control gate, a side wall insulating film formed so as to cover at least the floating gate or the side wall of the control gate, and an impurity diffusion region formed in the surface layer of the substrate adjacent to the side wall insulating film. A method of manufacturing a semiconductor device having a cobalt silicide film formed on the impurity diffusion region, wherein the side wall insulating film is composed of a plurality of insulating films of different materials, and a difference in etching rate between these insulating films is used. do it,
Forming a step at least at a corner of the side wall insulating film with the substrate surface, and forming a cobalt film on the entire surface of the substrate and then performing a heat treatment to form a cobalt silicide film on the gate electrode and the source / drain regions. Forming a semiconductor device. 8. The semiconductor according to claim 4, wherein said side wall insulating film has a double structure comprising a silicon oxide film and a silicon nitride film. Device manufacturing method.