JP2002149620A - Processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize synchronous burst read by a processor in a distributed and shared memory system for communicating data between plural processors via a shared memory. SOLUTION: An asynchronous access area A and a synchronous burst access area B are arranged in the memory space of the processors so that at least a part of these areas A and B may be mapped to the same shared memory area. Write to this area is performed asynchronously from a memory space A so as to avoid the increase of bus contention between distributed shared memories. Read is performed by synchronous burst access from a memory space B to realize fast read to a buffer within the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor system including a plurality of processors, and more particularly to a processor system in which information is exchanged between processors using a shared memory system.

[0002]

2. Description of the Related Art In a system in which information is exchanged between processors using a shared memory system, distributed information is distributed to each processor (or each processor group) in order to reduce contention for access to the shared memory from each processor. There is a type called a local shared memory or a distributed shared memory in which shared memories are arranged and connected by a shared bus system. In this system, when the contents of a local shared memory of one processor are changed by a write access, the contents are broadcasted via a shared bus system and written to another local shared memory to write the contents of each local shared memory. To match.
On the other hand, reading of data from the shared memory system is performed in parallel for each processor with respect to the local shared memory distributed in each processor. Therefore,
On the shared bus system, only a data write cycle to the local shared memory is generated, and no access conflict occurs to the shared memory during the read cycle of each processor, so that the throughput can be improved.

Further, in the shared memory system disclosed in Japanese Patent Application Laid-Open No. 9-62563, a memory having two independently accessible read ports and write ports is used as each local shared memory. The contention between the read cycle of the local shared memory from the processor and the write access from the shared bus system can be reduced.

[0004]

Recent processors have a high-speed buffer, and may transfer a large amount of data to and from a memory. In order to use a plurality of such processors and realize information exchange between the processors by the local shared memory system, it is desirable to have a function of enabling the processor to access the local shared memory in a burst mode. However, the above-mentioned known technique does not disclose a technique for speeding up access to a shared memory by burst transfer.

An object of the present invention is to provide a processor system capable of further improving communication throughput between processors by making a shared memory system burst accessible.

[0006]

SUMMARY OF THE INVENTION The present invention provides a memory system, one or more processors, and a control provided for each processor for controlling access to the memory system by each processor. And a plurality of processing units each including a circuit, and when a processor in the processing unit writes data to a memory system of one processing unit, the write data is written to a memory system in all other processing units. Processor system having a bus mechanism operable to copy to at least one processing unit.
One processor has a first memory space for accessing a memory system in the processing unit in an asynchronous mode, and a second memory space for accessing a memory system in the processing unit in a synchronous burst mode. The control circuit supports access in the asynchronous mode when the processor accesses the first memory space, and supports access in the synchronous burst mode when the processor accesses the second memory space. And a function of mapping at least a partial area of the memory system and at least a partial area of the second memory space to the same address area on the memory system.

[0007] The present invention further provides a memory system,
A plurality of processing units each including one or a plurality of processors and a control circuit corresponding to each processor for controlling access to the memory system of each of the processors; A processor system having a bus mechanism operable to copy the write data to the memory system in all other processing units when a write is performed from the processor in the processing unit to the memory system of the other processor unit. One processor in the processing unit has a first memory space for performing write access to the memory system in the processing unit in the asynchronous mode and reading access to the memory system in the processing unit in the synchronous burst mode. The control circuit of the There supports access by asynchronous mode when a write access to the first memory space, when the read access discloses a processor system, characterized in that it has the ability to support access by synchronous burst mode.

Further, according to the present invention, in the above processor system, the processor having the first memory space also has a second memory space for accessing in an asynchronous mode for both writing and reading, and a control circuit corresponding to the processor includes: When accessing the second memory space, it supports access in an asynchronous mode,
At least a part of the first memory space and the second memory space;
A processor system having a function of mapping at least a partial area in a memory space to the same address area in the memory system is disclosed.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a configuration example of a processor system according to the present invention. The processor system includes three processing units 109 to 111, and each processing unit includes one processor. The processing unit 109 includes a processor 100, a control circuit 103, and a shared memory system 106. Similarly, processing unit 1
10 includes a processor 101, a control circuit 104, and a shared memory system 107, and a processing unit 111 includes a processor 102, a control circuit 105, and a shared memory system 108.
Is provided. Each of the shared memory systems 106 to 108 is connected to each other by a shared bus system 112.

Hereinafter, the processing unit 109 will be mainly described, but the same applies to the other processing units 110 and 111. In the processing unit 109, the shared memory system 106 includes a two-port memory having a read port and a write port that can be accessed simultaneously, and a shared memory control device. Here, the shared memory control device reads the data in the two-port memory from the read port when the processor 100 performs the read from the shared memory system 106, and reads the data in the two-port memory when the processor 100 writes to the shared memory system 106. By writing data from the write port to the two-port memory and broadcasting the contents through the shared bus system 112, the contents of the shared memory systems 107 and 108 of the other processing units 110 and 111 are similarly changed. Here, the shared memory control devices in the shared memory systems 107 and 108 that have received the broadcast from the shared memory system 106
From the write port of the 2-port memory in 7, 108 each 2
Write to port memory. The shared memory control device also performs arbitration of the shared bus system 112.

The read port and the write port in the shared memory system 106 can operate independently, and even if the other processors 101 and 102 perform read access to the respective shared memory systems 107 and 108,
Even in the write access, the processor 100 can read-access the shared memory system 106 in parallel with this. On the other hand, when the processor 100 performs the write access to the shared memory system 106, the other processors 101 or 102
If write access is made to 07 or 108, contention may occur. In this case, the shared memory control device generates a signal for extending the bus cycle without terminating the write access bus cycle of the processor 100.

FIG. 1 shows a processor 1 according to the present invention.
This shows an example of a memory map of 00, which can be used by switching between an access mode for performing synchronous burst read / write and an access mode for performing asynchronous read / write depending on the address space. Area A is an asynchronous access area, area B is a synchronous burst access area, and areas a (addresses a _{0 to} a ₁ ) and area B in area A
The area b (addresses b _{0 to} b ₁ ) is mapped to the shared memory of the shared memory system 106 by the control circuit 103 as described below. If the area A-a (the area excluding the area a from the area A) is not empty, the area A-a is mapped to the local memory for asynchronous access of the processor 100, and similarly, the area B-b (the area B-a). Is not empty, the area Bb is mapped to the local memory of the processor 100 for synchronous access.

When the processor 100 accesses the area a, the control circuit 103 generates a control signal 116 and an address signal 117 for the shared memory system 106 from the control signal 113 and the address signal 114 from the processor 100, and performs read access. , The shared memory system 1
Data 118 read from 06 is output to the processor 100 as data 115, and in the case of a write access, the data 115 output by the processor 100 is written to the shared memory system 106 as data 118. Further, a control signal to the processor 100 is generated from the control signal 116 of the shared memory system 106, and the access cycle is completed. The processor 100 performs this access by asynchronous access. Here, the shared memory system 1
When a write occurs in the shared memory system 107, the content of the shared memory system 107, 10
8 is also reflected.

The control circuit 103 includes the processor 10
When 0 accesses the area b, the processor 10
From the control signal 113 and the address signal 114 from 0, a control signal 116 and an address signal 117 are generated and supplied to the shared memory system 106 to cause the shared memory system 106 to output data 118 corresponding to the synchronous burst read. This is synchronously burst-read as data 115.

Here, the access addresses from the processor 100 to the areas a and b are _denoted by a _n and b _n , _{respectively.}
Then, the control circuit 103

(Equation 1) With respect to the addresses a _n and b _{n having the} relationship of (1), the address 117 is generated so that the same (physical) address in the shared memory system 106 is accessed.

Thus, when the processor 100 having the memory map of FIG. 1 performs read access to the shared memory system 106, the other processors 101 and 102 perform read access to the respective shared memory systems 107 and 108. Even if you have write access,
The processor 100 operates in parallel with the shared memory system 1.
Since the read access to the shared memory system 06 is possible, the processor 100 can perform the burst read to the shared memory system 106 regardless of the access state of the other processors 101 and 102 to the shared memory systems 107 and 108. Thus, for example, consecutive addresses _{a n ~a n + k-1} (a 0 ≦ a n <a n + k-1 ≦ a 1) k pieces of data in the shared in memory system 106 written to access, processor 100 can be synchronized burst read by the read access address b _n ~b _n + k-1 continuous, it can be read at high speed in comparison with the case of performing asynchronous read. Where a _n , b _n
Satisfies the relationship of (Equation 1). The speeding up of the read access has the effect of improving the communication throughput between processors.

Further, the processor 100 stores the address a _n
For k pieces of data in the shared in memory written by accessing the ~a _n + k-1, the address a _n ~a _n + k-1
Asynchronous read can also be performed by read-accessing Therefore, the same address data in the shared memory system 106 can be accessed by both the asynchronous read and the synchronous burst read, and there is an effect that the access method can be selectively used as needed.

In the example of the memory map shown in FIG. 1, it is assumed that the area a and the area b on the shared memory system 106 are one area of continuous addresses, and they are completely overlapped on the shared memory system 106. , The area a and the area b are each composed of a plurality of small areas having continuous addresses, and only need to correspond to each of the small areas. in this case,
If the corresponding small areas are overlapped on the shared memory system 106, the read access can be executed in the burst mode. Also, regardless of whether the area a and the area b are divided into a single continuous address area or a plurality of small areas as described above, only a part of the areas a and b, but not the entire area, has the same address on the shared memory. In such a case, the speed can be increased by the synchronous burst read as described above for the same mapping area.

FIG. 3 shows a modification of the memory map of the processor 100 shown in FIG.
Is such that a synchronous burst access is performed at the time of reading from the area B, and an asynchronous access is performed at the time of writing. In the area A, as in FIG. 1, both read and write are asynchronous accesses. Areas a and b in the area A and the area B have addresses (a _{0 to} a ₁ ) and addresses (b ₀ to
b ₁ ), each of which has a control circuit 1
03 is mapped to the memory of the shared memory system 106. Areas A-a and B-b are mapped to local memory as in FIG. 1 if they are not empty.

When the processor 100 makes a write access to the area b, the control circuit 103 converts the control signal 113 and the address signal 114 from the processor 100 to the control signal 116 to the shared memory system 106 and the address signal 1.
17 and the data 11 output by the processor 100.
5 is written to the shared memory system 106 as data 118. Further, a control signal to the processor 100 is generated from the control signal 116 from the shared memory system 106, and the access cycle is ended. This access is performed by asynchronous access. Shared memory system 106
The contents written to the shared memory system 107 and 108 are also reflected through the shared bus system 112.

The control circuit 103 includes the processor 10
When 0 accesses the area b, the processor 10
From the control signal 113 and the address signal 114 from 0, a control signal 116 and an address signal 117 are generated and supplied to the shared memory system 106 to cause the shared memory system 106 to output data 118 corresponding to the synchronous burst read. This is synchronously burst-read as data 115. Thereby, the processor 100
Can perform synchronous burst read of data on the area b, and can read data at a higher speed than in the case of performing asynchronous read. Therefore, there is an effect that the communication throughput between the processors can be improved.

When the processor 100 having the memory map shown in FIG. 3 performs a read / write access to the area A, it performs an asynchronous access as in the case of FIG. The area a (addresses a _{0 to} a ₁ ) and the area b (addresses b ₀ to b ₁ )
If b ₁ ) is mapped to the same address on the shared memory system, as in FIG.
Both asynchronous read and synchronous burst read can be accessed for continuous area data on the shared memory system 106, and the access mode can be used as needed. In the case of the memory map of FIG. 3, the areas a and b may be divided into a plurality of corresponding small areas, and the areas mapped to the same address on the shared memory system are each of the areas a and b. May be a partial area.

In the case of the memory map shown in FIG. 3, all or a part of the area a and the area b may not necessarily be mapped to the same address of the shared memory system. In the case of FIG. 1, access to the area b is performed in the synchronous burst mode for both reading and writing. However, if writing is performed in the burst mode, problems such as bus contention may occur, which is not preferable. Therefore, the asynchronous write is preferably performed in the area where the synchronous burst read is performed, and at least this area is preferably written from the area a. For this purpose, areas a and b need to have a portion mapped to the same address on the shared memory system. But,
In the case of the memory map of FIG. 3, since the writing of the area b is performed by the asynchronous access, even if the area b is completely mapped to the address of the shared memory system different from the area a, the asynchronous burst read area is Write by access is possible.

In the above, the configuration of the processing unit 109, particularly, an example of a memory map of the processor 100 has been described with reference to FIGS. 1 to 3, but the same applies to the processing units 110 and 111.

Next, a processor system in which one processing unit includes a plurality of processors will be described. FIG.
This shows a configuration example of this multiprocessor system,
Each of the two processing units 430 and 440 includes four processors. The processing unit 430 includes processors 400 to 403, control circuits 410 to 413, and a shared memory system 420. Although the internal structure of the processor system 440 is not shown, it is the same as the processor system 430. The shared memory system 420 in the processor system 430 and the shared memory system in the processor system 440 are connected to each other by a shared bus system 450. Hereinafter, the processor system 430 will be mainly described.
The other processor system 440 is also the processor system 4
Same as 30.

The shared memory system 420 includes a 5-port memory having four read ports (first to fourth read ports) and one write port, and a shared memory controller. Here, when the processor 400 reads from the shared memory system 420, the shared memory control device reads the data in the 5-port memory from the first read port, and the processor 401
When reading from 0, the data in the 5-port memory is read from the second read port. When the processor 402 reads from the shared memory system 420, the data in the 5-port memory is read from the third read port.
When the processor 403 reads from the shared memory system 420, data in the 5-port memory is read from the fourth read port. Also, the shared memory system 420
When any of the processors 400 to 403 writes data into the shared memory system 420, the data is written from the write port to the 5-port memory and the contents are broadcast via the shared bus system 450. Processing unit 440 receiving this broadcast
The shared memory control device in the shared memory system writes data from the write port of the 5-port memory in the shared memory system to the 5-port memory. The shared memory control device in each of the processing units 430 and 440 also arbitrates the shared bus system 450.

Each of the read ports and the write ports in the shared memory system 420 can operate independently of each other.
In the case of performing read access to 0, the processing unit 430
Even if the other processors 401, 402, and 403 have read access to the shared memory system 420,
Even if write access is performed, the other processing unit 44
Regardless of whether the processor in 0 is performing read access or write access to the shared memory system in the processing unit 440, the processor 400 can perform read access to the shared memory system 420 in parallel with this.

On the other hand, when the processor 400 performs the write access to the shared memory system 420, the other processors 401, 402, and 403 in the processing unit 430 may perform the write access to the shared memory system 420, Contention may occur when the processor in the processing unit 440 has write access to the shared memory system in the processing unit 440. In this case, the shared memory controller ends the write access bus cycle of the processor 400. Instead, it generates a signal that extends the bus cycle. The above is the processor 401
403 and the processor in the processing unit 440 are the same as the processor 400.

Here, it is assumed that the processor in the processing unit 430 has the memory map shown in FIG. 1 or FIG. 3, and the control circuits 410 to 413 are shown in FIG.
Assume that it has the same mapping function as shown in. Then, read access from each processor can be performed independently in the burst mode, and high-speed read can be performed. In the configuration of FIG. 4, the four processors 400 to 40
3 for one (local) shared memory system 42
0, the load of the shared bus system 450 per processor can be reduced.
Thereby, the communication throughput between the processors can be further improved.

Although FIG. 4 shows a system having two processing units, a system other than two can be similarly constructed. In addition, although an example in which the number of processors in one processing unit is four has been described, the same configuration can be made when the number of processors is other than four. Generally, when the number of processors in one processing unit is N, the configuration is the same as that of FIG. 4 except that the number of read ports and the number of write ports of the multiport memory provided in the shared memory system in the unit are N. I just need.

[0031]

According to the present invention, in inter-processor communication using a shared memory, the processor can perform a synchronous burst read of the shared memory, thereby improving the communication throughput between the processors. Also, the same address data in the shared memory system can be accessed by both asynchronous read and synchronous burst read, and there is also an effect that the access method can be properly used as needed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a memory map of a processor in a processor system of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a processor system according to the present invention.

FIG. 3 is a diagram showing another example of a memory map of a processor in the processor system of the present invention.

FIG. 4 is a block diagram showing another configuration example of the processor system according to the present invention.

[Explanation of symbols]

 100 to 102 Processor 103 to 105 Control circuit 106 to 108 Shared memory system 109 to 111 Processing unit 112 Shared bus system 400 to 403 Processor 430, 440 Processing unit 410 to 413 Control circuit 420 Shared memory system 450 Shared bus system

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 15/177 682 G06F 15/177 682J (72) Inventor Terunobu Funatsu 502, Kandatecho, Tsuchiura-shi, Ibaraki Stock (72) Inventor Kotaro Shindo, 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Defense Systems Division, Hitachi Ltd. (72) Inventor Hiroshi Tanzawa 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address: Hitachi, Ltd., Defense System Division (72) Inventor Kazuo Ishikawa, 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Defense System Division (72) Inventor: Toshiya Masuda Totsuka, Yokohama-shi, Kanagawa 216 Totsuka-cho, Ward Hitachi, Ltd. Defen System business unit (72) inventor Takuya Okamura Kanagawa Prefecture, Totsuka-ku, Yokohama-shi Totsuka-cho, 216 address Co., Ltd. Hitachi, defense systems business unit within the F-term (reference) 5B045 BB28 BB29 BB32 BB47 DD05 DD13 EE03 5B060 KA02 KA09

Claims (3)

[Claims] 1. A process comprising one memory system, one or more processors, and a control circuit corresponding to a processor for controlling access of each of the processors to the memory system. A bus having a plurality of units and operating to copy the write data to the memory systems in all other processing units when a processor in the processing unit writes data to a memory system of one processing unit; A processor system with a mechanism, wherein one processor in at least one processing unit has a first memory space for accessing a memory system in the processing unit in an asynchronous mode, and a memory system in the processing unit in a synchronous burst mode. And a second memory space for accessing The control circuit corresponding to the processor supports access in the asynchronous mode when the processor accesses the first memory space, and supports access in the synchronous burst mode when the processor accesses the second memory space. A processor system having a function of mapping at least a partial area in one memory space and at least a partial area in the second memory space to the same address area in the memory system. 2. A process comprising one memory system, one or more processors, and a control circuit corresponding to a processor for controlling access of each of the processors to the memory system. A bus having a plurality of units and operating to copy the write data to the memory systems in all other processing units when a processor in the processing unit writes data to a memory system of one processing unit; In a processor system with a mechanism, one processor in at least one processing unit has write access to a memory system in the processing unit in an asynchronous mode and read access to a memory system in the processing unit in a synchronous burst mode. A first memory space; The control circuit corresponding to the processor has a function of supporting asynchronous mode access when the processor makes a write access to the first memory space, and having a function of supporting synchronous burst mode access when making a read access to the first memory space. Processor system. 3. The processor system according to claim 2, wherein the processor having the first memory space further includes a second memory space that accesses both write and read in an asynchronous mode, and the control circuit corresponding to the processor includes the processor. Supports access in the asynchronous mode when accessing the second memory space, and connects at least a partial area on the first memory space and at least a partial area on the second memory space on the memory system. A processor system having a function of mapping to the same address area.