JP2002141387A - Extraction method and extraction device for impurity density distribution within semiconductor substrate and extraction program recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily execute the extraction of impurity density distribution at a high speed from the electric characteristics of a MOS FET at the time of extracting the impurity density distribution in the horizontal direction of the channel surface of the MOS FET. SOLUTION: By using actually measured data for which thresholds to a plurality of the MOS FETs of different gate lengths manufactured under the same process condition are actually measured and the analysis model of the threshold of the MOS FET, the impurity density distribution within the substrate of the channel surface of the MOS FET is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for extracting an impurity concentration distribution near the surface of a semiconductor substrate, an extraction apparatus and an extraction program recording medium, and more particularly to a method for extracting a lateral impurity concentration distribution on a channel surface from the electrical characteristics of a MOS FET. Extraction method, apparatus and extraction program recording medium, for example, MOS FET device design, technology
Computer-aided design (TCAD) calibration,
This is used when extracting circuit model parameters.

[0002]

2. Description of the Related Art The impurity concentration distribution in a semiconductor substrate is based on MOS.
FET device design, TCAD calibration,
This is useful for extracting circuit model parameters.
Here, the TCAD calibration is to tune the parameter values in the physical model so that the physical model used in TCAD such as process / device simulation reproduces the actual measurement value.

Conventionally, a one-dimensional impurity profile in the depth direction in a substrate is obtained by SIMS analysis or gate capacitance / gate voltage (C
G-VG) There is known a method of obtaining from characteristics.

On the other hand, it is difficult to obtain the "impurity concentration distribution in the lateral direction on the substrate surface" which affects the threshold value Vth of the short channel MOS FET.

Recently, a technique called "inverse modeling" has been proposed as a method for obtaining a lateral impurity concentration distribution in a substrate. "Inverse modeling" is based on the fact that the change in the electrical characteristics due to the change in the bias applied to the MOS FET depends on the impurity concentration in the substrate. Is a technique for estimating

In this regard, N. Khalil et al., J. Vac.
chnol. B 14 (1), pp.224-230, Jan / Feb 1996 (Reference 1)
Discloses a method of estimating the impurity concentration distribution from the capacitance characteristics between the terminals of a MOS FET.Zachary K. Lee et al.
IEEE Trans. Electron Devices, Vol.46, pp.1640-164
9, August 1999 (Reference 2) discloses a method of estimating an impurity concentration distribution from a subthreshold current characteristic of a MOS FET.

In these methods, the impurity concentration distribution in the substrate is represented by a two-dimensional distribution function, and device simulation for the MOS FET is repeatedly executed while changing the values of the parameters in the distribution function. That
Determine the values of the parameters in the distribution function to reproduce the actual electrical characteristics of the MOS FET. As a result, a two-dimensional impurity concentration profile in the substrate can be obtained.

In these methods, two-dimensional impurity distribution can be accurately predicted by using device simulation. However, since the device simulation is repeatedly executed to determine optimal parameter values, a huge amount of calculation is required. take time.

[0009]

As described above, the conventional method for extracting the impurity concentration distribution in a semiconductor substrate is a MOS FET.
In order to accurately predict the two-dimensional impurity distribution in a semiconductor substrate from the electrical characteristics of a semiconductor device, it is necessary to repeatedly execute device simulations to determine the optimal parameter values, which requires a huge amount of calculation time. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for extracting an impurity concentration distribution in a lateral direction of a channel surface from a MOS FET in a high-speed and simple manner. An object of the present invention is to provide an extraction method of an impurity concentration distribution, an extraction device, and an extraction program recording medium.

[0011]

According to a first method of extracting an impurity concentration distribution in a semiconductor substrate according to the present invention, a plurality of MOS FETs having different gate lengths manufactured under the same process conditions as a MOS FET for which an impurity concentration distribution is to be obtained are provided. Using the measured data obtained by actually measuring the threshold value of the MOS FET and the analysis model in which the short channel effect and the reverse short channel effect of the threshold value of the MOS FET are modeled, the rough distribution of the impurity concentration in the substrate near the surface of the MOS FET channel is calculated. It is characterized in that it is calculated.

According to a second method of extracting an impurity concentration distribution in a semiconductor substrate according to the present invention, an MO for obtaining an impurity concentration distribution is used.
Threshold and gate capacitance CG for multiple MOS FETs with different gate lengths manufactured under the same process conditions as S FET
Using the measured data obtained by actually measuring the gate voltage VG characteristics and the analysis model in which the short channel effect and the reverse short channel effect of the threshold of the MOS FET are modeled,
A rough distribution of the impurity concentration in the substrate near the surface of the channel is calculated.

A third method of extracting an impurity concentration distribution in a semiconductor substrate according to the present invention is a method for obtaining an impurity concentration distribution in a lateral direction in a semiconductor substrate from electrical characteristics of a MOS FET. Multiple MOSs with different gate lengths manufactured under the same process conditions as the MOS FET
The stored data is read from the storage device that stores the measured data that measured the threshold value for the FET, and the analysis model in which the short channel effect and the inverse short channel effect of the MOS FET threshold value stored in advance in the storage device are modeled is referenced. A process for automatically calculating the impurity concentration distribution in the substrate on the channel surface of the MOS FET.

According to a first aspect of the present invention, there is provided an apparatus for extracting an impurity concentration distribution in a semiconductor substrate.
A storage device that stores the measured data of the thresholds measured for multiple MOS FETs with different gate lengths manufactured under the same process conditions as the SFET, and the short channel effect and inverse short channel effect of the MOS FET threshold are modeled. A storage device for storing the analysis model, a data reading unit for reading storage data of the storage device, and processing the data read by the data reading unit with reference to the analysis model stored in the storage device. And said
Calculating means for calculating the impurity concentration distribution in the substrate on the channel surface of the MOS FET.

According to a second aspect of the present invention, there is provided an apparatus for extracting an impurity concentration distribution in a semiconductor substrate.
Threshold and gate capacitance CG for multiple MOS FETs with different gate lengths manufactured under the same process conditions as S FET
A storage device for storing measured data obtained by actually measuring the gate voltage VG characteristic, a storage device for storing an analysis model in which a short channel effect and a reverse short channel effect of a threshold value of a MOS FET are modeled, A data reading unit for reading, and processing the data read by the data reading unit with reference to an analysis model stored in the storage device to calculate an impurity concentration distribution in the substrate on the surface of the channel of the MOS FET. And a calculating means.

A program recording medium for extracting an impurity concentration distribution in a semiconductor substrate according to the present invention is a medium on which a program for obtaining an impurity concentration distribution in a lateral direction in a semiconductor substrate from an electrical characteristic of a MOS FET is recorded. MOS FET for which the impurity concentration distribution is to be calculated
Read the measured data from the storage device that stores the measured data of the measured threshold values for multiple MOS FETs with different gate lengths manufactured under the same process conditions, and read the threshold values of the MOS FET threshold values stored in the storage device in advance. A program for calculating the impurity concentration distribution in the substrate on the surface of the channel of the MOS FET with reference to an analysis model in which the short channel effect and the reverse short channel effect are modeled is recorded.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an example of a block configuration of an apparatus for extracting an impurity concentration distribution in a semiconductor substrate according to a first embodiment of the present invention. The present apparatus is realized by a computer which reads a program recorded on a recording medium such as a magnetic disk and the operation of which is controlled by the program.

In FIG. 1, 1 is a computer,
A data reading unit 11 for reading storage data of the external storage device 2, a storage unit 13 for storing an analysis model of a threshold value of a MOS FET, and data read by the data reading unit 11 are stored in the storage unit 13. A calculation means (impurity concentration extraction unit 12) for processing with reference to the analysis model and calculating the impurity concentration distribution in the substrate on the MOS FET channel surface, and a result output unit 14 for displaying the extraction result and outputting it by printing or the like. Have.

The external storage device 2 has a threshold (MO) for a plurality of MOS FETs having different gate lengths manufactured under the same process conditions as the MOS FET whose impurity concentration distribution is to be obtained.
The measured data (CG-VG data) obtained by actually measuring the gate capacitance and gate voltage characteristics of a MOS FET having a sufficiently large gate length and gate width are stored. Things. In this case, the plurality of MOS FETs having different gate lengths include at least one long channel MOS FET and at least two short channel MOS FETs having different gate lengths. Includes tube threshold data.

FIG. 2 is a flowchart showing an example of a procedure for extracting an impurity concentration distribution in a semiconductor substrate using the apparatus shown in FIG.

FIG. 3 shows a MOS to be extracted according to the present invention.
FIG. 4 is a diagram showing correspondence between an impurity concentration in a substrate of a FET and various parameters. This example shows the case of an NMOS FET.

Where NCH is the channel concentration and NHAL
O and LHALO are the P-type impurity concentration and lateral length of the high impurity concentration region at the channel end formed by HALO implantation, respectively, and NDIFF and LDIFF are the N-type impurity concentration and gate of the source / drain diffusion layers, respectively. The length is below.

Next, an example of a procedure for extracting the impurity concentration distribution in the semiconductor substrate will be described with reference to FIGS.

First, in a first step STEP1, the data reading section 11 reads triode threshold data, pentode threshold data, and CG-VG data from the storage device 2. Here, the MOS FE for which the impurity concentration distribution is to be obtained is
For a plurality of MOS FETs with different gate lengths (for example, formed as test elements on a wafer) manufactured under the same process conditions as T, the threshold value when a low voltage of about 0.05 V is applied to the drain electrode Data is referred to as triode threshold data, and similarly, data when the voltage applied to the drain electrode is equal to the power supply voltage is referred to as pentode threshold data.

CG-VG data refers to the capacitance between the gate electrode and the substrate with respect to the gate voltage of a device having a sufficiently large gate length and gate width manufactured under the same process conditions as the MOS FET for which the impurity concentration distribution is to be obtained. It is a characteristic.

FIG. 4 conceptually shows the gate capacitance characteristic of the MOS FET to be extracted according to the present invention.
FIG. 4 conceptually shows the gate length dependence of the threshold value of the MOS FET to be extracted according to the present invention.

Next, in the second to fifth steps STEP2 to STEP5, the impurity concentration extraction unit 12 uses the read data and the analysis model of the threshold value prepared in the analysis model storage unit 13 to store the MOS FET substrate. Extract the impurity concentration inside.

Here, the threshold analysis model is a MOS FET
This is an analytical model for the threshold of, the reverse short channel effect by halo implant (pocket implant), the short channel effect by charge sharing, DIBL
(Drain Induced Barrier Lowering) is prepared by modeling each of the short channel effects based on semiconductor physics. That is, the analytic expression has the following format.

MOS FET threshold = (threshold in long channel) + (inverse short channel effect) − (short channel effect by charge sharing) − (short channel effect by DIBL) This embodiment satisfies this condition. As an analysis model,
BSI developed at the University of California, Berkeley
M3 (Berkeley Short-channel IGFET Model ver.3) is used. However, another analysis model may be used as long as the short channel effect and the inverse short channel effect are models based on semiconductor physics. BSIM
The analytical formula of the threshold model of 3 is shown below.

(Threshold in Long Channel) VTH0 VTH0 = VFB + φs + (2 * εsi * q * NCH * φs) ^1/2 / εox / Tox (1) where φs = 2 * (K * Temp) / Q) * ln (NCH / ni) (Inverse short channel effect) ΔVTH_RSCE ΔVTH_RSCE = (2 * εsi * q * NCH * φs) ^1/2 / (εox / Tox) * ((NCH * (L-2 * LDIFF -2 * LHALO) + NHALO * 2 * LHALO) / ((L-2 * LDIFF) * NCH)) ^1/2 -1)… (2) (Short channel effect by charge sharing)
ΔVTH_CS ΔVTH_CS = DVT0 * [exp {-DVT1 * (L-2 * LDIFF) / (2 * lt)} + 2 * exp {-DVTl * (L-2 * LDIFF) / lt)}] * (Vbi-φs )… (3) where lt = (εsi * Tox * Xdep / εox) ^1/2 Vbi = (k * Temp / q) * ln (NCH * NDIFF / ni ² ) Xdep = {2 * εsi * φs / (q * NCH)} ^1/2 DVT0 = 2.2 DVT1 = 0.53 (Short channel effect by DIBL) ΔVTH_DIBL ΔVTH_DIBL = [exp {-DSUB * (L-2 * LDIFF) / (2 * lt)} + 2 * exp {-DSUB * (L-2 * LDIFF) / lt}] * ETA0 * VDS (4) where DSUB = 0.53 ETA0 = 0.08 The meaning of each symbol in the equations (1) to (4) is as follows: It is on the street.

L: Gate length of MOSFET Tox; Gate oxide film thickness (generally, gate insulating film) VFB; Flat band voltage φs; Surface potential at the time of forming channel inversion layer εsi; Silicon (substrate under gate insulating film) Dielectric constant εox; Dielectric constant of gate oxide film (insulating film) q; Electric charge per electron k; Boltzmann constant Temp; Temperature at the time of electric characteristic measurement ni; Intrinsic carrier concentration Vbi; Source / drain diffusion layer Built-in potential of the PN junction between the substrate and the substrate. Xdep; Depletion layer depth of the channel portion when the channel inversion layer is formed. DVT0, DVT1, ETA0; BSIM3 parameters, default values are used.

In the above model equations (1) to (4), the MOS FET
Parameters VFB, Tox, NCH, LDIFF, LHALO, NHALO, ND for lateral impurity concentration distribution near the surface in the substrate
IFF is extracted by this method.

Specific MOS in the impurity concentration extraction unit 12
Procedure for extracting impurity concentration in FET substrate STEP2 to STEP5
Is as follows.

First, in STEP 2, VFB and Tox are extracted from the CG-VG data. In this case, as shown in FIG. 4, the VG at which CG starts to decrease as VG rises in the CG-VG characteristic is obtained as VFB. When VG is sufficiently low, CG divided by the product of gate length L and gate width W is Cox
And Tox is calculated by Tox = εox / Cox. Here, Cox is the gate-substrate capacitance per unit area.

Next, in step 3, the triode threshold data of the long channel and VFB and Tox extracted in step 2 are substituted into equation (1) to extract NcH.

Next, in STEP4, a line obtained by extrapolating, for example, triode threshold data of a relatively long channel of 1.0 μm, to VTH0 + ΔVTH_RSCE obtained by adding the equations (1) and (2), and VFB and Tox extracted in STEP2 And extracted in STEP3
Substitute NCH and extract NHLO, LHALO, and LDIFF.

Next, in STEP 5, VTH0 + ΔVT is obtained by adding equation (2) to equation (1) to reduce equations (3) and (4).
In H_RSCE-ΔVTH_CS- △ VTH_DIBL, triode threshold data and pentode threshold data, VFB extracted in STEP2, Tox
And NCH extracted in STEP3 and NHALO extracted in STEP4
, LHALO, and LDIFF, and extract NDIFF.

Further, by performing the tuning by repeatedly performing the procedures from STEP 2 to STEP 5, it becomes possible to increase the extraction accuracy.

Finally, in STEP 6, the result output unit 14 outputs the result of the extracted impurity distribution.

By the above procedure, the lateral impurity in the substrate such as the impurity concentration of the channel portion in the MOS FET substrate, the length and impurity concentration of the high impurity concentration region at the channel end, and the length and impurity concentration of the source / drain diffusion layers. Information on the concentration distribution can be obtained at high speed.

The parameter values relating to the impurity concentration on the channel surface extracted in this manner are used for the TCAD calibration, the extraction of the circuit parameters, the acquisition of the initial values of the circuit parameters, and the values of the circuit parameters reflecting the variation of the process parameters. It may be used for extracting variation, and enables highly accurate extraction.

That is, the feature of the above-described embodiment is that only the analytical expression of the MOS FET is used without using the device simulation, so that the impurity distribution in the substrate can be quickly predicted. As a result, the efficiency of TCAD calibration can be increased. As a result, the efficiency of MOS FET device design and TCAD calibration can be improved.

Incidentally, as the CG-VG data, data known by a method other than actual measurement can be used.
In addition, by using a model that considers the dependence of the applied bias on the substrate electrode of the MOS FET,
The impurity concentration distribution can be obtained with higher accuracy.

The method described in the above-described embodiment may be a program that can be executed by a computer such as a magnetic disk (floppy (registered trademark) disk, hard disk, etc.), an optical disk (CD
-ROM, DVD, etc.), and can be applied to various devices by writing to a recording medium such as a semiconductor memory or transmitted to a communication medium and applied to various devices. A computer that realizes the present apparatus reads the program recorded on the recording medium, and executes the above-described processing by controlling the operation of the program.

[0046]

As described above, according to the method for extracting impurity concentration distribution in a semiconductor substrate, the extraction apparatus, and the extraction program recording medium of the present invention, the extraction of impurity concentration distribution on the channel surface can be performed at high speed based on the electrical characteristics of the MOS FET. And it can be easily executed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an apparatus for extracting an impurity concentration distribution in a semiconductor substrate according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a procedure for extracting an impurity concentration distribution in a semiconductor substrate using the apparatus of FIG.

FIG. 3 is a diagram showing parameters relating to impurity concentration in a substrate of a MOS FET to be extracted according to the present invention.

FIG. 4 is a diagram conceptually showing a gate capacitance characteristic of a MOS FET to be extracted according to the present invention.

FIG. 5 is a diagram conceptually showing a gate length dependency of a threshold value of a MOS FET to be extracted according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Computer, 2 ... External storage device, 11 ... Data reading part, 12 ... Impurity concentration extraction part, 13 ... Analysis model storage part, 14 ... Result output part.

Claims (10)

[Claims] 1. A MOS for which an impurity concentration distribution is to be obtained.
Threshold data and MO for multiple MOS FETs with different gate lengths manufactured under the same process conditions as the FET.
Using an analysis model in which the short channel effect and the inverse short channel effect of the threshold of the S FET are modeled,
A method for extracting an impurity concentration distribution in a semiconductor substrate, comprising calculating a rough distribution of the impurity concentration in the substrate near the channel surface of the MOS FET. 2. A MOS for which an impurity concentration distribution is to be obtained.
Threshold data and gate capacitance / gate voltage characteristics of multiple MOS FETs with different gate lengths manufactured under the same process conditions as the FET are measured, and the short channel effect and reverse short channel effect of the MOS FET threshold are modeled. A method of extracting an impurity concentration distribution in a semiconductor substrate, comprising calculating a rough distribution of the impurity concentration in the substrate near a MOS FET channel surface using an analytical model. 3. A plurality of MOS FETs having different gate lengths
Are at least one long channel MOS FET and at least two short channel MOS FETs having different gate lengths.
3. The method for extracting an impurity concentration distribution in a semiconductor substrate according to claim 1, wherein T is included. 4. The impurity concentration distribution in a semiconductor substrate according to claim 1, wherein the analysis model considers the dependency of a bias applied to a substrate electrode of a MOS FET. Extraction method. 5. A method for determining an impurity concentration distribution in a lateral direction in a semiconductor substrate from an electrical characteristic of a MOS FET, wherein a gate length manufactured under the same process conditions as a MOS FET for which an impurity concentration distribution is to be determined. Multiple different MOS FETs
The stored data is read from the storage device that stores the measured data obtained by actually measuring the threshold with respect to the threshold value of the MOS FET stored in the storage device in advance. A method for extracting an impurity concentration distribution in a semiconductor substrate, wherein a process of calculating an impurity concentration distribution in the substrate on the channel surface of the MOS FET is automatically performed. 6. A series of processes from the reading of the stored data to the calculation of the impurity concentration distribution includes reading of triode threshold data, pentode threshold data, gate capacitance / gate voltage characteristic data stored in the storage device. A second step of extracting a flat band voltage VFB and a gate insulating film thickness Tox from the gate capacitance / gate voltage characteristic data, and a step of extracting VFB, Tox and a long voltage extracted in the second step. A third step of substituting the triode threshold data of the channel into the analytical expression of the threshold in the long channel of the MOS FET and extracting the channel concentration NcH; and the inverse short channel effect in the analytical expression of the threshold in the long channel of the MOS FET. Extrapolating the triode threshold data of the relatively long channel to the value obtained by adding the analytical expression of VFB, Tox and the previous value extracted in the second step. Substituting the NCH extracted in the third step with the NCH extracted, the P-type impurity concentration NHAL of the high impurity concentration region at the channel end formed by the HALO implanter
A fourth step of extracting O and the lateral length LHALO and the length LDIFF under the gate of the source / drain diffusion layer; and analyzing the inverse short channel effect in the analytical expression for the long channel of the MOS FET. Equations are added, and the analytical formula for the short channel effect due to charge sharing and DIBL
(Triode threshold data and pentode threshold data, VFB, Tox extracted in the second step, and extracted in the third step) to a value obtained by subtracting the analytical expression of the short channel effect by (Drain Induced Barrier Lowering). NCH
And NHALO, LHALO, extracted in the fourth step,
6. A method for extracting an impurity concentration distribution in a semiconductor substrate according to claim 5, further comprising a fifth step of extracting the N-type impurity concentration NDIFF of the source / drain diffusion layer by substituting LDIFF. 7. The method for extracting an impurity concentration distribution in a semiconductor substrate according to claim 6, wherein the tuning is performed by repeatedly performing the procedure from the second step to the fifth step. 8. A MOS for which an impurity concentration distribution is to be obtained.
A storage device that stores the measured data of the thresholds measured for multiple MOS FETs with different gate lengths manufactured under the same process conditions as the FETs, and an analysis that models the short-channel effect and reverse short-channel effect of the MOS FET threshold. A storage device for storing a model, a data reading unit for reading storage data of the storage device, and processing the data read by the data reading unit with reference to an analysis model stored in the storage device, Calculating means for calculating the impurity concentration distribution in the substrate on the surface of the channel of the MOS FET. 9. A MOS for which an impurity concentration distribution is to be obtained.
A storage device that stores the measured data of the threshold and gate capacitance / gate voltage characteristics of multiple MOS FETs manufactured under the same process conditions as the FET with different gate lengths, and the short channel effect of the MOS FET threshold and the reverse short channel. A storage device for storing an analysis model in which an effect is modeled; a data reading unit for reading storage data of the storage device; and an analysis model for storing data read by the data reading unit in the storage device. And a calculating means for calculating the impurity concentration distribution in the substrate on the surface of the channel of the MOS FET. 10. A medium in which a program for obtaining a lateral impurity concentration distribution in a semiconductor substrate from an electrical characteristic of a MOS FET is recorded. Read the measured data from the storage device that stores the measured data of the measured threshold values for multiple MOS FETs with different gate lengths manufactured under the same process conditions, and read the threshold values of the MOS FET threshold values stored in the storage device in advance. Extraction program recording of impurity concentration distribution in semiconductor substrate recording program for calculating impurity concentration distribution in substrate on channel surface of the MOS FET with reference to analysis model in which short channel effect and reverse short channel effect are modeled Medium.