JP2002141170A - Light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily provide multicolor light emitting device of an active matrix type. SOLUTION: This multicolor light emitting device of the active matrix type is provided by forming a multicolor display region by forming several types of EL(electroluminescent) layers according to pixel groups such as pixel lines, pixel columns, or multiple adjacent pixels. A preliminary region is provided so that the inferior formation of the EL layer caused by mask deviation can be prevented. The use of the EL layer composed of a triplet compound can save the electric power.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EL (El
The present invention relates to a light emitting device including an element (hereinafter, referred to as an EL element) sandwiching a thin film (hereinafter, referred to as an organic EL film) made of an organic compound capable of obtaining ectro luminescence.

[0002]

2. Description of the Related Art In recent years, the technology for forming a TFT on a substrate has been greatly advanced, and its application to an active matrix type display device (light emitting device) has been developed. In particular, a TFT using a polysilicon film has higher field-effect mobility (also referred to as mobility) than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. Therefore, the control of the pixel, which has been conventionally performed by the drive circuit outside the substrate, can be performed by the drive circuit formed on the same substrate as the pixel.

[0003] Such an active matrix type light-emitting device is manufactured by various circuits and elements on the same substrate to reduce manufacturing costs, downsize the electro-optical device, increase the yield, and reduce the throughput. Advantages are obtained.

Further, active matrix type light-emitting devices having an EL element as a self-luminous element have been actively studied.

An EL element has a structure in which an EL layer is sandwiched between a pair of electrodes (anode and cathode).
It has a laminated structure. Representatively, the “hole transport layer /” proposed by Tang et al. Of Kodak Eastman Company
Light-emitting layer / Electron transport layer ". This structure has a very high luminous efficiency, and most of the structures currently under research and development are adopting this structure.

In addition, a hole injection layer / hole transport layer / light-emitting layer / electron transport layer, or a hole injection layer / hole transport layer / light-emitting layer / electron transport layer / electron injection layer may be provided on the anode. A structure in which layers are sequentially stacked may be used. The light emitting layer may be doped with a fluorescent dye or the like.

In this specification, all layers provided between a cathode and an anode are collectively called an EL layer. Therefore, the above-described hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer, and the like are all included in the EL layer.

Then, a predetermined voltage is applied to the EL layer having the above structure from a pair of electrodes, whereby recombination of carriers occurs in the light emitting layer to emit light. In this specification, a light-emitting element formed of an anode, an EL layer, and a cathode is referred to as an EL element.
It is called an element.

The EL layer of the EL element has heat, light, moisture,
Since deterioration is promoted by oxygen or the like, an EL element is generally formed after a wiring or a TFT is formed in a pixel portion in manufacturing an active matrix light-emitting device.

[0010] Various methods have been proposed for forming (forming) the EL layer. For example, a vacuum deposition method, a sputtering method, a spin coating method, a roll coating method, a casting method, an LB method, an ion plating method, a dipping method, an ink jet method, a printing method and the like can be mentioned.

Furthermore, in order to realize colorization of the light emitting device, for example, as disclosed in Japanese Patent Application Laid-Open No. 10-012377, a technique of forming EL layers having different emission colors for each pixel using an ink jet method. Has been proposed.

[0012]

In order to achieve a high-definition display in a light emitting device, an active matrix type is preferable.
In the case of realizing the colorization, the formation of the EL layer may be defective due to the displacement of the metal mask due to the fine structure.

[0013]

In order to solve the above problems, in the present invention, a plurality of pixels arranged in one line in a pixel portion are called a pixel row, and a plurality of pixels arranged in one line in a pixel portion are called a pixel column.
Several types of EL layers are formed for each pixel group such as a pixel row, a pixel column, or a plurality of adjacent pixels to realize multi-color in an active matrix light-emitting device.

In the present invention, a first type of EL layer is formed in a plurality of pixel rows from the end among the pixel rows in the pixel portion. Then, after a row of pixels adjacent to the first type of EL layer is opened, a second type of EL layer is formed in a plurality of pixel rows adjacent thereto. Note that a pixel row provided between the first kind of EL layer and the second kind of EL layer is referred to as a spare area in this specification, and no EL layer is formed in this spare area.

The spare area is provided as a margin when a mask shift or the like occurs when the first type EL layer and the second type EL layer are formed. Since no signal is input to the pixel rows existing in the spare area, the first kind of EL layer or the second kind of EL
It does not matter if a layer is formed.

Further, after the second type of EL layer is formed, a spare area is provided again in an adjacent pixel row. That is,
As described above, the EL layer and the spare region are alternately provided to prevent a defect generated when the EL layer is formed in the pixel portion.

The spare area formed here is 1-5.
It is preferable to provide rows, that is, it is preferable to provide 2 to 6 types of EL layers depending on the spare area.

As a light emitting material for forming the EL layer, known materials can be used. However, in order to improve external quantum efficiency, at least one type of EL layer emits triplet excitation energy (phosphorus). It is necessary to use an organic compound (hereinafter, referred to as a triplet compound) that can be converted into light emission. Note that a material used for ordinary light emission is a singlet compound because it is a compound that can convert singlet excitation energy into light emission.

As the triplet compound, organic compounds described in the following articles are mentioned as typical materials. (1) T.Tsutsui, C.Adachi, S.Saito, Photochemical
Processes in OrganizedMolecular Systems, ed.K.Hond
a, (Elsevier Sci. Pub., Tokyo, 1991) p. 437. (2) MABaldo, DFO'Brien, Y. You, A. Shoustikov,
S. Sibley, METhompson, SRForrest, Nature 395
(1998) p.151. (3) MABaldo, S.Lamansky, PEBurrrows, METho
mpson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4. (4) T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura,
T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayag
uchi, Jpn. Appl. Phys., 38 (12B) (1999) L1502. The organic compounds disclosed in these articles are shown below.

[0020]

(Equation 1)

The above molecular formula is a metal complex having platinum, which is a third transition element, as a central metal (hereinafter referred to as a platinum complex).
It is.

[0022]

(Equation 2)

The above molecular formula is a metal complex having iridium as a central metal (hereinafter referred to as an iridium complex).

The triplet compound is not limited to these compounds, and it is also possible to use a compound having the above structure and having, as a central metal, an element belonging to groups 8 to 10 of the periodic table. .

The triplet compound has a higher luminous efficiency than the singlet compound, and the operating voltage (the voltage required for the EL element to emit light) can be lowered to obtain the same emission luminance.

In addition to forming an EL layer made of the same light emitting material for each of a plurality of pixel rows as described above,
It may have another shape including an EL layer formed using the same light emitting material for a plurality of pixel columns or a plurality of adjacent pixels.

Further, the first light emitting material 1
Types of EL layers are formed in the pixel portion.
A 90% area may be formed.

By forming an EL layer as described above, a multi-color light-emitting device with high definition and low power consumption can be formed.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a plurality of Es are provided in a pixel portion.
A method for forming the L layer will be described with reference to FIGS. However, here, a method of separately manufacturing only the light emitting layer in the EL layers, instead of separately manufacturing different EL layers, will be described. Note that in this specification, at least the same material used for a light-emitting layer in forming an EL layer is regarded as the same EL layer.

FIG. 1A shows a structure in which a source side driving circuit 102, a gate side driving circuit 103 and a pixel portion 10 are formed on a substrate 101.
It is the schematic which shows the mode that 4 was formed. Pixel section 104
Are formed by three types of EL layers. Note that the present invention relates to formation of a plurality of EL layers in the pixel portion 104 over a substrate, and FIG. 1B is an enlarged view of the pixel portion 104. FIG. 2 is a perspective view of an EL layer to be manufactured. 1 and 2 are denoted by the same reference numerals, and may be appropriately referred to.

In FIG. 1B, the pixel portion 104 includes:
A plurality of pixels 105 are formed vertically and horizontally.
Note that the pixel 105 includes a gate line (G1), a source line (S1), and a current supply line (V1) provided in the pixel portion.
Formed by In the pixel portion 104, the current supply lines (V1 to Vy) and the gate lines (G1 to Gy) are formed in parallel and alternately.

In the present embodiment, a pixel row having a gate line (G1), source lines (S1 to Sx) and a current supply line (V1) is called 11 (ell 1), and a gate line (G2) , A pixel row having a source line (S1 to Sx) and a current supply line (V2) is denoted by l2, and a gate line (G
y), source lines (S1 to Sx) and current supply lines (V
The pixel row having y) is referred to as ly.

Here, a method of forming an EL layer in a pixel portion where a TFT and a pixel electrode of an EL element are formed on a substrate will be described as an embodiment of the present invention.

First, as shown in FIG.
A hole injection layer (or hole injection layer) 202 is formed on the substrate 01. At this time, as a hole injection material, copper phthalocyanine (C) having a high adhesion to the anode and a low hole injection barrier is used.
It is preferable to use a substance such as u-Pc) or PEDOT.

Next, a hole transport layer (or hole transport layer) 203 is provided. As the hole transport material, aromatic amine α-NPD having a function of accelerating the movement of holes,
Materials such as 2Me-TPD, TPAC, or TAD having a spiro structure are suitable.

Then, the hole injection layer 202 and the hole transport layer 2
After forming 03, a light emitting layer is formed.

First, a light emitting layer a (106a) is formed on the pixel rows 11 and 12 in FIG. 1B. here,
A red light-emitting layer is formed, and as a material of the red light-emitting layer, a material obtained by doping aluminum quinolylate complex (Alq ₃ ) with DCM by about several percent is used. For the film formation, an evaporation method is used, and the film thickness is 1 to 60 nm (preferably 10 to 30 n
m). Note that the light emitting layer a in the pixel portion 104
The structure after forming (106a) is shown in the perspective view of FIG.

In the pixel row 13 adjacent to the light emitting layer a (106a), the spare area a (107) is formed without forming the light emitting layer.
a) is provided.

Next, the light emitting layer b (106b) is formed again in the pixel rows from l4 to ly-3. Here, a green light emitting layer is formed. For the green light-emitting layer, a CBP obtained by doping Ir (ppy) ₃ by about several percent as a triplet compound is used. As a specific method, it is manufactured by co-evaporating CBP and Ir (ppy) ₃ . The film thickness at this time is 1 to 60 nm (preferably 10 to 60 nm).
30 nm).

Further, the pixel row of ly-2 is replaced with the spare area b.
After (107b), the light emitting layer c (107c) is formed on the pixel rows of ly-1 and ly. Here, a blue light emitting layer is formed. For the blue light emitting layer, DPVBi which is a bisstyryl-based material was used. In addition, a light emitting material such as an azomethine zinc complex or a benzoxazole zinc complex (Zn (BOX) ₂ ) is preferably used for the blue light emitting layer. Further, a material obtained by doping these light-emitting materials with perylene by about several percent may be used. For the film formation, an evaporation method is used, and the film thickness is 1 to 60 nm (preferably 1 to 60 nm).
(0 to 30 nm).

When the above EL layer is formed, a structure as shown in FIG. 2B is obtained. That is, the preliminary area a (107a) is provided between the light emitting layer a (106a) and the light emitting layer b (106b).
Are provided, and the light emitting layer b (106b) and the light emitting layer c (1
06c) is provided with the spare area b (107b).

In this embodiment mode, an example is shown in which the EL layer is formed of three types of red, green, and blue light emitting layers. Just one. That is, the number of light emitting layers may be two or three or more. However, if too many light-emitting layers are formed, the production becomes difficult, which is contrary to the object of the present invention. Therefore, about six types are preferable.
In addition, it is preferable to provide 1 to 5 spare areas.

However, in consideration of low power consumption in the light emitting device, it is necessary to provide at least one light emitting layer made of a triplet compound. In addition, as a light emitting layer utilizing triplet excitation energy, octaethylporphyrin platinum complex (2,3,7,8,12,13,17,18-octaethy
There is an orange light emitting layer doped with l-21H, 23H-porphine platinum (PtOEP).

Furthermore, it is also possible to use colors of the light emitting layer other than the above three types. For example, as a light emitting layer,
A yellow light emitting layer can also be formed. As a light emitting material, a material in which Alq ₃ is doped with Nile Red, or a material in which BeBq 2 or TPD is doped with Rubrene may be used. The film thickness is 1 to 60 nm.
(Preferably 10 to 30 nm).

Further, it is possible to form a white light emitting layer. The white light emitting layer can be produced by doping a host light emitting layer with a light emitting dye. Alternatively, it may be manufactured by laminating a spiro-type DTVBi layer and a layer in which Alq3 is doped with DCM.
Note that the thickness of the light emitting layer formed by lamination is 1 to 30 nm.
(Preferably 10 to 20 nm), but may be adjusted according to the individual light emission intensity or the like.

Although low-molecular materials have been described as light-emitting materials, polyparaphenylenevinylene (PP
V), a polymer material such as polyparaphenylene, polyvinylcarbazole (PVK), polythiophene, or polyfluorene (PF) may be used. As a method for forming a polymer material, an inkjet method is preferable.

As the polyparaphenylenevinylene-based material, poly (2,5-dialkoxy-1,4-phenylenevinylene): RO-PPV can be used, and poly (2-methoxy-5- (2- Ethyl-hexoxy)-
Materials such as 1,4-phenylenevinylene: MEH-PPV and poly (2,5-dimethyloctylsilyl-1,4-phenylenevinylene): DMOS-PPV can be used.

As the polyparaphenylene-based material, poly (2,5-dialkoxy-1,4-phenylene): R
O-PPP can be used.

As the polythiophene-based material, poly (3-alkylthiophene): PAT can be used, and materials such as poly (3-hexylthiophene): PHT and poly (3-cyclohexylthiophene): PCHT can be used. it can. In addition, poly (3-cyclohexyl-4-methylthiophene): PCHMT, poly (3- [4-octylphenyl] -2,2′bithiophene): PTOP, poly (3- (4octylphenyl) -thiophene): POPT-1 or the like can also be used.

As the polyfluorene-based material, poly (dialkylfluorene): PDAF can be used. More specifically, poly (dioctylfluorene): PDO
A material such as F can be used.

As the polyacetylene-based material, materials such as polypropylphenylacetylene: PPA-iPr, polybutylphenylphenylacetylene: PDPA-nBu, and polyhexylphenylacetylene: PHPA can be used.

The solvents for these polymer materials include toluene, benzene, chlorobenzene, dichlorobenzene, chloroform, tetralin, xylene, anisole, dichloromethane, γ-butyl lactone, butyl cellosolve, cyclohexane, NMP (N-methyl- 2-pyrrolidone), dimethylsulfoxide, cyclohexanone, dioxane, or THF (tetrahydrofuran)
Etc. can be used.

Further, in addition to the above-mentioned materials, a polymer material having a hole injecting property, PEDOT (poly (3,4-ethylene dioxy)
thiophene)) and polyaniline (PA) can also be used. Note that these materials use water as a solvent.

These are examples of light emitting materials that can be used for the light emitting layer of the present invention, and there is no need to be limited to these, and known light emitting materials can be used freely.

After forming the plurality of light emitting layers as described above, the electron transport layer 205 and the electron injection layer 206 are formed. At this time, as the electron transport material, Alq ₃ , 1,
Materials having high hole blocking properties, such as 3,4-trioxazole derivatives and 1,2,4-triazole derivatives (TAZ), are preferable.

As a material for forming the electron injection layer 206, MgAg, LiF and Li (acac) are preferable. Further, Alq ₃ doped with an alkali metal may be used.

As described above, the EL shown in FIG.
Layer 204 can be formed. Note that in this embodiment mode, a method for forming the EL layer 204 having a structure including the hole injection layer 202, the hole transport layer 203, the light-emitting layers (106a to 106c), the electron transport layer 205, and the electron injection layer 206 is described. Although shown, layers other than the light emitting layer may be provided as needed.

Further, even if the light emitting materials are different, the hole injection layer,
The method of simultaneously forming the hole transport layer, the electron transport layer, and the electron injection layer using the same material has been described. However, the present invention is not limited thereto. Is also good.

In the present embodiment, the pixel unit 1
Although three types of light-emitting layers (light-emitting layer a, light-emitting layer b, and light-emitting layer c) and spare areas (spare area a and spare area b) are formed in 04, no source signal is input to the pixels serving as the spare areas. . However, a source signal is input to the pixel on which the light emitting layer is formed except for the spare area. In the present specification, a region including a plurality of pixels displayed by a source signal is referred to as a display region.

Since the display area displays a color corresponding to each light emitting layer, multi-color display on the same substrate becomes possible.

As described above, the division of the light emitting layer is shown in FIG.
It may be different from. FIG. 11 shows an example. In these, it is preferable that the current supply line in the pixel is arranged in accordance with the light emitting layer. When the light emitting layers are divided for each row, the current supply lines are arranged in parallel with the rows. When the light emitting layers are divided for each column, the current supply lines are arranged in parallel with the columns. Details will be described in the following embodiments.

[0062]

[Embodiment 1] In this embodiment, a pixel portion and a driving circuit TFT (an n-channel TFT and a p-channel TFT) provided around the pixel portion are simultaneously formed on the same substrate.
Further, FIG.
This will be described with reference to FIG.

First, in this embodiment, Corning # 70
A substrate 300 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that the substrate 300 is not limited as long as it is a light-transmitting substrate, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a base film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 300. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, SiH ₄ , N 2
The silicon oxynitride film 301a formed by using H ₃ and N ₂ O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 10 nm).
0 nm). In this embodiment, a 50 nm-thick silicon oxynitride film 301a (composition ratio: Si = 32%, O = 27%,
N = 24%, H = 17%). Next, as a second layer of the base film 301, a plasma CVD
A silicon oxynitride film 301b formed by using iH ₄ and N ₂ O as a reaction gas has a thickness of 50 to 200 nm (preferably 100 nm).
(About 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 301b (composition ratio Si =
32%, O = 59%, N = 7%, H = 2%).

Next, the semiconductor layer 302 is formed on the base film 301.
To 306 are formed. The semiconductor layers 302 to 306 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering, L
After forming a film by a PCVD method or a plasma CVD method, a known crystallization treatment (a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel).
Is performed and the crystalline semiconductor film obtained is patterned into a desired shape. The semiconductor layers 302 to 306 are formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). Although there is no limitation on the material of the crystalline semiconductor film,
Preferably silicon (silicon) or silicon germanium _{(Si X Ge 1-X (} X = 0.0001~0.02)) may be formed such as an alloy. In this embodiment, the plasma CV
After a 55-nm amorphous silicon film was formed by method D, a solution containing nickel was held on the amorphous silicon film. After dehydrogenation (500 ° C., 1 hour) of this amorphous silicon film, thermal crystallization (550 ° C., 4 hours) is performed, and further, a laser annealing process for improving crystallization is performed. Thus, a crystalline silicon film was formed. Then, the crystalline silicon film is patterned by a photolithography method.
The semiconductor layers 302 to 306 are formed.

After the formation of the semiconductor layers 302 to 306, a slight amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 4.
(Typically 200~300mJ / cm ²⁾ 00mJ / cm2 to.
When a YAG laser is used, it is preferable that the second harmonic is used, the pulse oscillation frequency is 30 to 300 Hz, and the laser energy density is 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). And width 100
A laser beam condensed linearly at ~ 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 50-9.
What is necessary is just to set it as 0%.

Next, a gate insulating film 307 covering the semiconductor layers 302 to 306 is formed. The gate insulating film 307 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is formed by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300 to
400 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured is thereafter
Good characteristics as a gate insulating film can be obtained by thermal annealing at up to 500 ° C.

Next, as shown in FIG. 3A, a first conductive film 308 having a thickness of 20 to 100 nm and a second conductive film 30 having a thickness of 100 to 400 nm are formed on the gate insulating film 307.
9 are laminated. In this embodiment, a 30 nm-thick T
a first conductive film 308 made of an aN film and a film thickness of 370 nm
A second conductive film 309 made of a W film was formed by lamination. T
The aN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D. In any case, it is necessary to lower the resistance in order to use it as a gate electrode,
It is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm can be realized.

In this embodiment, the first conductive film 308
Is TaN, and the second conductive film 309 is W. However, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, Ag,
An alloy made of Pd and Cu may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, and the first conductive film is formed of titanium nitride (T
iN) film, the second conductive film is a W film, the first conductive film is a tantalum nitride (TaN) film, and the second conductive film is an Al film. The conductive film may be formed using a tantalum nitride (TaN) film and the second conductive film may be formed using a Cu film.

Next, as shown in FIG.
A mask 310 made of a resist using a graphic method
314, and a first for forming electrodes and wiring.
Perform an etching process. In the first etching process, the first
And under the second etching condition. In this embodiment, the first
Etching conditions are ICP (Inductively Coupled).
Plasma: Inductively coupled plasma) etching method
CF for gas for etching _FourAnd Cl_TwoAnd O_TwoAnd use
The gas flow ratio is 25/25/10 (sccm),
At a pressure of 1 Pa, a coil-shaped electrode (diameter 25 cm)
Applying RF (13.56MHz) power of W to generate plasma
Etching. Here, Matsushita Electric Industrial Co., Ltd.
Dry Etching Equipment Using Model ICP (Model E
645- □ ICP). Substrate side (sample stage)
Also use an electrode with an electrode size of 12.5cm x 12.5cm
Input 150W RF (13.56MHz) power
, A negative self-bias voltage is applied. This first etch
Etching the W film in accordance with the
The part has a tapered shape. W under the first etching condition
Is 200.39 nm / min,
The etching rate for TaN is 80.32 nm / mi.
n and the selectivity ratio of W to TaN is about 2.5.
You. In addition, the first etching condition causes the W
The hyper angle is about 26 °.

[0073] Thereafter, changed to the second etching conditions without removing the masks 310 to 314 made of resist as shown in FIG. 3 (B), using CF ₄ and Cl ₂ as etching gas, respectively Gas flow ratio 30/30 (scc
m) and 500 W of R on the coil-type electrode at a pressure of 1 Pa
F (13.56 MHz) power is applied to generate plasma and about 3
Etching was performed for about 0 seconds. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / mi.
n, the etching rate for TaN is 66.43 nm /
min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees. Thus, the first shape conductive layers 315 to 319 (the first conductive layers 315 a to 319 a and the second conductive layer 315 b) including the first conductive layer and the second conductive layer are formed by the first etching process.
To 319b). Reference numeral 320 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 315 to 319 is etched by about 20 to 50 nm to form a thinned region.

Then, the resist mask is removed.
First doping process without adding n-type to the semiconductor layer.
The added impurity element is added. (Fig. 3 (B)) Dopin
Can be done by ion doping or ion implantation
Good. The condition of the ion doping method is that the dose amount is 1 × 10¹³
~ 5 × 10^Fifteenatoms / cm^TwoAnd the acceleration voltage is 60 to 100
Performed as keV. In this embodiment, the dose is 1.5 × 1
0^Fifteenatoms / cm^TwoAnd the acceleration voltage is set to 80 keV.
Was. Element belonging to Group 15 as an impurity element imparting n-type
Using arsenic, typically phosphorus (P) or arsenic (As)
However, phosphorus (P) is used here. In this case, the conductive layer 3
15 to 319 are masses for the impurity element imparting n-type.
And the self-aligned high-concentration impurity regions 321 to 32
5 are formed. The high-concentration impurity regions 321 to 325
1 × 10²⁰~ 1 × 10^{twenty one}atoms / cm ^ThreeN type in the concentration range of
An impurity element to be added is added.

Next, as shown in FIG. 3C, a second etching process is performed without removing the resist mask. Here, CF ₄ , Cl ₂ and O ₂ are used as etching gases.
And the respective gas flow rate ratios are 20/20/20
(Sccm) and a pressure of 1 Pa applies 50
An RF (13.56 MHz) power of 0 W was supplied to generate plasma to perform etching. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 124.62 nm / mi.
n, the etching rate for TaN is 20.67 nm /
min and the selectivity ratio of W to TaN is 6.05. Therefore, the W film is selectively etched. The taper angle of W became 70 ° by the second etching. By the second etching process, the second conductive layer 33 is formed.
0b to 334b are formed. On the other hand, the first conductive layer 315
a to 319a are hardly etched to form first conductive layers 330a to 334a.

Next, a second doping process is performed. The doping is performed using the second conductive layers 330b to 334b as a mask for the impurity element, so that the semiconductor element below the tapered portion in the first conductive layer is doped with the impurity element. In this embodiment, P is used as the impurity element.
Plasma doping was performed using (phosphorus) at a dose of 1.5 × 10 ¹⁴ , a current density of 0.5 μA, and an acceleration voltage of 90 keV. Thus, the low-concentration impurity regions 340 to 344 overlapping with the first conductive layer are formed in a self-aligned manner. The concentration of phosphorus (P) added to low-concentration impurity regions 340 to 344 is 1 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ , and depends on the thickness of the tapered portion in the first conductive layer. It has a gentle concentration gradient. Although the impurity concentration in the semiconductor layer overlapping the tapered portion of the first conductive layer slightly decreases from the end of the tapered portion in the first conductive layer toward the inside, the impurity concentration is approximately the same. . Further, an impurity element is also added to the high-concentration impurity regions 321 to 325, and the high-concentration impurity regions 345 to 325 are also added.
49 are formed (FIG. 4A).

Next, as shown in FIG. 4B, a third etching process is performed by using a photolithography method. This third etching treatment is performed in order to partially etch the tapered portion of the first conductive layer so that the tapered portion overlaps with the second conductive layer. However, a mask made of resist (350, 351) is formed in a region where the third etching is not performed, as shown in FIG.

Etching in Third Etching Process
The condition is that Cl is used as an etching gas. _TwoAnd SF₆Using
Each gas flow ratio is 10/50 (sccm)
ICP etching method as well as first and second etching
This is performed using The TaN in the third etching process
Is 111.2 nm / min,
The etching rate for the gate insulating film is 12.8 nm / m
in.

In this embodiment, etching was performed by applying a 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1.3 Pa to generate plasma. A 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, first conductive layers 340a to 342a are formed.

By the third etching, first conductive layers 352a to 354a are formed, and impurity regions (LDD regions) 355 to 357 which do not overlap therewith are formed. Note that impurity regions (GOLD regions) 340 and 3
42 remains overlapping first conductive layers 330a and 332a.

The electrode formed by the first conductive layer 330a and the second conductive layer 330b ultimately becomes the gate electrode of the n-channel TFT of the driving circuit, and the first conductive layer 352a The electrode formed with the second conductive layer 352b finally becomes the gate electrode of the p-channel TFT of the driver circuit.

Similarly, the electrode formed by the first conductive layer 353a and the second conductive layer 353b finally becomes the gate electrode of the n-channel TFT in the pixel portion, and the first conductive layer 354a and the The electrode formed by the second conductive layer 354b finally becomes the gate electrode of the p-channel TFT in the pixel portion. Further, the first conductive layer 332a and the second conductive layer 3
The electrode formed by 32b finally becomes one electrode of a capacitor (holding capacity) of the pixel portion.

As described above, in the present embodiment, the impurity regions (LDDs) which do not overlap the first conductive layers 352a to 354a
Regions) 355 to 357 and impurity regions (GOLD regions) 340 and 342 overlapping with the first conductive layers 330a and 332a can be formed at the same time, and can be separately formed according to TFT characteristics.

Next, the gate insulating film 320 is etched. Here, the etching process is performed by adding C to the etching gas.
Reactive ion etching method (RIE method) using HF ₃
This is performed using In this embodiment, the chamber pressure is 6.7P
a, RF power 800 W, CHF ₃ gas flow rate 35 sccm
To perform an etching process. As a result, parts of the high-concentration impurity regions 345 to 349 are exposed, and the insulating films 360 to 36 are exposed.
4 are formed separately.

Next, after removing the mask made of resist, masks 365 and 366 made of resist are newly formed, and a third doping process is performed. Due to this third doping process, the semiconductor layer serving as the active layer of the p-channel TFT has a conductivity type (p-type) opposite to the one conductivity type (n-type).
Region 37 to which an impurity element for imparting a type is added.
0 to 375 are formed (FIG. 4C). Second conductive layer 3
52b, 332b, and 354b are used as a mask for the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligned manner.

In this embodiment, the impurity regions 370 to 375
Is formed by an ion doping method using diborane (B ₂ H ₆ ). Phosphorus is added at different concentrations to the impurity regions 370 to 375 by the first doping process and the second doping process, and the concentration of the impurity element imparting p-type is 2 × in each of the regions. 10 ²⁰ ~
By performing the doping treatment at 2 × 10 ²¹ atoms / cm ³ , there is no problem because it functions as a source region and a drain region of a p-channel TFT.

Through the above steps, impurity regions are formed in the respective semiconductor layers. Note that, in this embodiment, the method of doping an impurity (boron) after etching the gate insulating film is described; however, the impurity may be doped without etching the gate insulating film.

Next, a mask 365 made of resist is used.
366 is removed to form a first interlayer insulating film 376 as shown in FIG. The first interlayer insulating film 376 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a film thickness of 15
A 0 nm silicon oxynitride film was formed. Needless to say, the first interlayer insulating film 376 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As a thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
700 ° C., typically at 500-550 ° C.
In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation treatment, nickel used as a catalyst at the time of crystallization contains impurity regions (345, 348, 370,
372, 374), and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced.
TF having channel forming region manufactured in this manner
T has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

Alternatively, after the activation process, a doping process may be performed to form a first interlayer insulating film.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, as shown in FIG. 5B, a second interlayer insulating film 380 made of an organic insulating material is formed on the first interlayer insulating film 376. In this embodiment, the film thickness is 1.6 μm.
Was formed. Next, each impurity region 3
Patterning for forming a contact hole reaching 45, 348, 370, 372, 374 is performed.

As the second interlayer insulating film 380, a film made of an insulating material containing silicon or an organic resin is used. As the insulating material containing silicon, silicon oxide, silicon nitride, or silicon oxynitride can be used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used.

In this embodiment, a silicon oxynitride film formed by a plasma CVD method was formed. Note that the thickness of the silicon oxynitride film is preferably 1 to 5 μm (more preferably 2 to 4 μm). A silicon oxynitride film is effective in suppressing deterioration of an EL element because moisture contained in the film itself is small. In addition, dry etching or wet etching can be used for forming the contact hole. However, considering the problem of electrostatic breakdown at the time of etching, it is preferable to use a wet etching method.

Further, in forming the contact hole here, since the first interlayer insulating film and the second interlayer insulating film are simultaneously etched, considering the shape of the contact hole, the material forming the second interlayer insulating film is It is preferable to use a material having an etching rate higher than that of the material forming the one interlayer insulating film.

Then, each of the impurity regions 345, 348, 3
Wirings 381 to 388 that are electrically connected to 70, 372, and 374, respectively, are formed. Then, a 50 nm thick T
Although a laminated film of an i film and a 500 nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning, another conductive film may be used.

Next, a transparent conductive film is formed on the
The pixel electrode 389 is formed by forming a pattern with a thickness of 0 nm and patterning. (FIG. 5B) In this embodiment, indium tin oxide (IT) is used as a pixel electrode.
O) 2-20% zinc oxide (Z
A transparent conductive film mixed with nO) is used.

The pixel electrode 389 is connected to the drain wiring 3
The current control T
An electrical connection is formed with the drain region of the FT.

Next, as shown in FIG. 6, an insulating film containing silicon (silicon oxide film in this embodiment) is formed to a thickness of 500 [nm], and an opening is formed at a position corresponding to the pixel electrode 389. Then, a third interlayer insulating film 390 functioning as a bank is formed. When the opening is formed, a tapered side wall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently smooth, the deterioration of the EL layer due to the step becomes a significant problem,
Caution must be taken.

In the present embodiment, a film made of silicon oxide is used as the third interlayer insulating film 390. However, depending on the case, polyimide, polyamide, acryl, B
An organic resin film such as CB (benzocyclobutene) can also be used.

Next, as shown in FIG. 6, an EL layer 391 is formed by a vapor deposition method. Here, a state in which one of the plurality of EL layers formed in the present invention is formed is shown.

First, PEPOT is formed on the pixel electrode 389 by spin coating. And then MTDAT
A is deposited to form a hole injection layer (not shown).
Further, a hole transport layer (not shown) is formed by evaporating S-TAD (spiro-type TAD).

Then, here, a light emitting layer made of spiro type DTVBi is formed by vapor deposition. This is a light-emitting material which emits blue light in a single layer. In this case, the film thickness is 1 to 40 nm, and a light emitting layer in which Alq ₃ is doped with DCM is formed on the DTVBi by a co-evaporation method. This is a light-emitting material that emits red light in a single layer. Further, the film is formed to have a thickness of 1 to 40 nm. When the light-emitting layer has a stacked structure of the above two layers, a white light-emitting layer can be formed.

Further, after forming another light emitting layer as shown in this embodiment mode, Alq ₃ is deposited as an electron transporting layer (not shown). The film thickness at this time is 1 to
The thickness may be set to 50 nm. Thus, an EL layer is formed. Further, a cathode (MgAg electrode) 392 and a protection electrode 393 are formed by an evaporation method. At this time, it is desirable that heat treatment be performed on the pixel electrode 389 before the EL layer 391 and the cathode 392 are formed to completely remove moisture. In this embodiment, Mg is used as the cathode of the EL element.
Although an Ag electrode is used, an AlLi alloy, a material composed of aluminum and an element belonging to Group 1 or 2 of the periodic table, or another known material may be used.

The protective electrode 393 is provided to prevent the deterioration of the cathode 392, and is typically a metal film containing aluminum as a main component. Of course, other materials may be used. Also,
Since the EL layer 391 and the cathode 392 are extremely weak to moisture, the layers up to the protective electrode 393 are continuously formed without being exposed to the atmosphere.
It is desirable to protect the EL layer from outside air.

As a material for forming the EL layer 391, a known material can be used. In this embodiment, the hole injection layer, the hole transport layer (Hole transporting layer),
The EL layer has a four-layer structure including a light emitting layer (Emitting layer) and an electron transport layer.
Alternatively, there may be a case where any portion other than the light emitting layer is missing. Various examples of such combinations have already been reported,
Either of these configurations may be used.

Although the protection electrode 393 can protect the EL layer 391 from moisture and oxygen, it is more preferable to provide a passivation film 394. In this embodiment, the passivation film 394 has a thickness of 300 nm.
A thick silicon nitride film is provided. This passivation film may be formed continuously after the protection electrode 393 without being exposed to the atmosphere.

The thickness of the EL layer 391 is 10 to 400.
[nm] (typically 60 to 150 [nm]), and the thickness of the cathode 392 is 80 to 200 [nm] (typically 100 to 150 [n].
m]).

Thus, the structure as shown in FIG. 6 is completed. In this specification, a device manufactured up to the structure shown in FIG. 6 is called an EL module. In the manufacturing process of the EL module in this embodiment, a source signal line is formed of Ta and W which are materials forming a gate electrode, and a source and a source are formed due to a circuit configuration and a process.
Although the gate signal line is formed of Al which is a wiring material forming the drain electrode, a different material may be used.

Further, a driver circuit 506 having an n-channel TFT 501 and a p-channel TFT 502 and a pixel portion 507 having a switching TFT 503, a current controlling TFT 504, and a capacitor 505 can be formed over the same substrate.

In this embodiment, since the light is emitted from the bottom due to the element structure of the EL element, the switching TFT 5
03 shows a configuration in which an n-channel TFT is used and a p-channel TFT is used as the current control TFT 504, but this embodiment is merely a preferred embodiment, and is not limited to this.

The n-channel TFT 50 of the drive circuit 506
Reference numeral 1 denotes a channel formation region 400, a low-concentration impurity region 3 overlapping with a first conductive layer 330a forming a part of a gate electrode.
40 (GOLD region) and a high-concentration impurity region 345 functioning as a source region or a drain region.
The channel forming region 40 is formed in the p-channel TFT 502.
1. There are impurity regions 370 and 371 functioning as a source region or a drain region.

The switching TFT 50 of the pixel portion 507
3 does not overlap with the channel formation region 402 and the first conductive layer 353a forming the gate electrode, and functions as a low-concentration impurity region 356 (LDD region) formed outside the gate electrode and as a source region or a drain region. It has a high concentration impurity region 348.

The current controlling TFT 504 of the pixel portion 507 includes a channel forming region 403 and high-concentration impurity regions 374 and 37 functioning as a source region or a drain region.
Five. The capacitor 505 is formed so that the first conductive layer 332a and the second conductive layer 332b function as one electrode.

In this embodiment, the structure in which the EL layer is formed on the pixel electrode (anode) and then the cathode is formed has been described. However, the EL layer and the anode are formed on the pixel electrode (cathode). It is good also as a structure. However, in this case, unlike the bottom emission described above, a top emission form is adopted. At this time, it is desirable that the switching TFT and the current control TFT are formed of the n-channel TFT having the low concentration impurity region (LDD region) described in this embodiment.

In this embodiment, the driving voltage of the TFT is 1.2 to 10 V, preferably 2.5 to 10 V.
5.5V.

When the display of the pixel portion is operating (in the case of displaying a moving image), the background display is performed by the pixels where the EL element emits light, and the character display is performed by the pixels where the EL element does not emit light. However, in the case where the moving image display of the pixel portion is stationary for a certain period of time or more (referred to as a standby state in this specification), the display method is switched (inverted) to save power. It is good to keep it.
Specifically, characters are displayed by pixels where the EL element emits light (also referred to as character display), and the background is displayed by pixels where the EL element does not emit light (also referred to as background display).

Embodiment 2 Next, a method of completing the EL module shown in FIG. 6 as a light emitting device will be described with reference to FIG.

FIG. 7A is a top view showing a state where the EL module is sealed, and FIG. 7B is a view showing AA ′ of FIG. 7A.
It is sectional drawing cut | disconnected by. 701 shown by a dotted line is a source side driver circuit, 702 is a pixel portion, and 703 is a gate side driver circuit. 704 is a cover material, 705 is a first seal material, 706 is a second seal material, and the first seal material 7
The inside surrounded by 05 is a space.

Reference numeral 708 denotes wiring for transmitting signals input to the source-side driving circuit 701 and the gate-side driving circuit 703, and a video signal or a clock signal from an FPC (flexible print circuit) 709 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The light emitting device in this specification includes not only the light emitting device body but also an FPC
Alternatively, this also includes a state where the PWB is attached.

Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 702 and a gate-side driver circuit 703 are formed above a substrate 710. The pixel portion 702 is formed by a plurality of pixels including a current control TFT 711 and a pixel electrode 712 electrically connected to a drain thereof. You. The gate side driving circuit 703 is an n-channel type TF
It is formed using a CMOS circuit (see FIG. 5) in which T713 and p-channel TFT 714 are combined.

The pixel electrode 712 functions as an anode of the EL element. Further, banks 715 are provided at both ends of the pixel electrode 712.
Are formed, and an EL layer 716 and a cathode 717 of an EL element are formed on the pixel electrode 712.

The cathode 717 also functions as a wiring common to all pixels, and is electrically connected to the FPC 709 via the connection wiring 708. Further, all elements included in the pixel portion 702 and the gate driver circuit 703 are covered with the cathode 717 and the passivation film 718.

The cover member 704 is attached to the first seal member 705. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 704 and the EL element. The space 707 inside the first sealant 705 is filled with an inert gas such as nitrogen. Note that an epoxy resin is preferably used as the first sealant 705. Further, it is preferable that the first sealant 705 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an effect of preventing oxidation may be contained in the space 707.

In this embodiment, the material of the plastic substrate constituting the cover member 704 is FRP (Fiberglass).
-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

After bonding the cover member 704 with the first sealant 705, a second seal member 706 is provided so as to further cover the side surface (exposed surface). Note that the same material as the first sealant 705 can be used for the second sealant 706.

With the above structure, the EL element is placed in the space 707.
By sealing the EL element, the EL element can be completely shut off from the outside, and it is possible to prevent a substance that promotes deterioration of the EL layer due to oxidation, such as moisture and oxygen, from entering from the outside. Therefore, a highly reliable light-emitting device can be obtained.

The structure of this embodiment can be implemented by freely combining with any structure of the first embodiment.

[Embodiment 3] FIG. 8A shows a more detailed top structure of the pixel portion, and FIG. 8B shows a circuit diagram thereof.
In FIG. 8, a switching TF provided on a substrate is provided.
T804 is the switching (n-channel type) TF shown in FIG.
It is formed using T503. Therefore, for the description of the structure, the description of the switching (n-channel) TFT 503 may be referred to. A wiring denoted by reference numeral 803 is a gate wiring for electrically connecting the gate electrodes 804a and 804b of the switching TFT 804.

Although the present embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The source of the switching TFT 804 is connected to the source wiring 815, and the drain is connected to the drain wiring 805. The drain wiring 805 is electrically connected to the gate electrode 807 of the current controlling TFT 806. Note that the current control TFT 806 is formed using the current control (p-channel type) TFT 504 in FIG. Therefore, for the description of the structure, the description of the current control (p-channel type) TFT 504 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The source of the current controlling TFT 806 is electrically connected to the current supply line 816, and the drain is electrically connected to the drain wiring 817. The drain wiring 817 is electrically connected to a pixel electrode (anode) 818 indicated by a dotted line.

At this time, a storage capacitor (capacitor) is formed in a region 819. Capacitor 819
Is the semiconductor film 8 electrically connected to the current supply line 816
20, between the gate electrode 807 and an insulating film (not shown) in the same layer as the gate insulating film. In addition, a capacitor formed by the gate electrode 807, the same layer (not shown) as the first interlayer insulating film, and the current supply line 816 can be used as a storage capacitor.

The configuration of this embodiment can be implemented by freely combining with any of the configurations of the first and second embodiments.

[Embodiment 4] In this embodiment, FIG. 9A shows an example of a pixel structure in a pixel portion of a light emitting device according to the present invention having a structure different from that in Embodiment 1, and FIG. Is shown in FIG. 9 (B).

In FIG. 9A, reference numeral 901 denotes a source signal line connected to the source of the switching TFT 902, and 903 denotes a write gate signal line connected to the gate of the switching TFT 902. Plus 90
Reference numeral 4 denotes a current controlling TFT, and reference numeral 905 denotes a capacitor (which can be omitted). Reference numeral 906 denotes a current supply line, 907 denotes an erasing TFT, and is connected to the erasing gate signal line 908. 909 is an EL element,
910 is a counter power supply. For the operation of the erasing TFT 907, refer to Japanese Patent Application No. 11-338786.

The drain of the erasing TFT 907 is connected to the gate electrode of the current controlling TFT 904, and the current controlling T
The gate voltage of the FT 904 can be forcibly changed. Note that the erasing TFT 907 is n
Although a channel TFT or a p-channel TFT may be used, it is preferable that the switching TFT 902 has the same structure as the switching TFT 902 so that off-state current can be reduced.

Next, the sectional structure will be described. FIG.
In (B), as a switching TFT 902 provided over a substrate 900, an n-channel TFT formed by a known method is used. This embodiment has a double gate structure. The double gate structure has a structure in which substantially two TFTs are connected in series, and has an advantage that an off-current value can be reduced. Further, a p-channel TFT formed using a known method may be used.

Next, as the erasing TFT 907, an n-channel TFT formed by a known method is used. In addition,
A p-channel TFT formed using a known method may be used. Note that a drain wiring 926 of the erasing TFT 907 is connected to another switching TFT by another wiring.
902 and a gate electrode 935 (935a, 935b) of the current controlling TFT.

In this embodiment, the structure of the switching TFT 902 and the structure of the erasing TFT 907 are both formed so that the gate electrode does not overlap the LDD region via the gate insulating film.

As the current controlling TFT 904, a p-channel TFT formed by a known method is used. The gate electrode 935 (935a, 935) of the current controlling TFT
b) is a switching TFT 902 by another wiring.
Are electrically connected to the drain wiring 916 of the erasing TFT 907 and the drain wiring 926 of the erasing TFT 907.

The structure of each of the current controlling TFTs 904 is formed such that the gate electrode does not overlap with the source region and the drain region via the gate insulating film.

In this embodiment, the current controlling TFT 90
4 has a single gate structure, but a plurality of TFs are shown.
A multi-gate structure in which T is connected in series may be used. Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

The drain wiring 936 is connected to the current supply line 9
06, and a constant voltage is always applied.

A first passivation film 941 is provided on the switching TFT 902, the current control TFT 904, and the erasing TFT 907, and an interlayer insulating film 942 made of a resin insulating film is formed thereon. Interlayer insulating film 94
It is very important to flatten the step due to the TFT by using 2. Since the EL layer formed later is very thin,
Light emission failure may occur due to the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

A transparent conductive film is used as the pixel electrode (anode) 943. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.
Note that it is electrically connected to the drain region of the current controlling TFT 904.

Further, an EL layer 945 is formed in a groove (corresponding to a pixel) formed by the banks 944a and 944b formed of an insulating film (preferably resin) and on the banks. Although only one pixel is shown here,
As shown in this embodiment, a hole injection layer, a hole transport layer,
An EL layer 945 including a plurality of light-emitting layers is formed in a pixel portion by forming a plurality of light-emitting layers, an electron transport layer, and an electron injection layer.

In this embodiment, the cathode 94 is provided on the EL layer 945.
6 are formed. Note that the cathode 946 is formed of MgAg.

When the cathode 946 is formed, the EL element 909 is completed. Note that the EL element 909 mentioned here
Denotes a capacitor formed by the pixel electrode (anode) 943, the EL layer 945, and the cathode 947.

In this embodiment, a protective electrode 947 made of aluminum is further formed on the cathode 946, and a passivation film 948 is further provided thereon. As the passivation film 948, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the light emitting device is improved.

As described above, the present invention can be used for a light emitting device having a structure as shown in FIG. In this embodiment, only the structure of the pixel portion has been described, but the drive circuit has the same configuration as that shown in the first embodiment.

The structure of this embodiment can be implemented by freely combining with any of the structures of the first to third embodiments.

[Embodiment 5] Next, FIG. 10A shows an example of a pixel structure in a pixel portion of a light emitting device according to the present invention having a structure different from that of Embodiment 4, and FIG. 1
0 (B). For details such as the driving method,
Reference may be made to Japanese Patent Application No. 2000-127384.

First, in FIG. 10A, reference numeral 1001 denotes a source signal line connected to the source of the switching TFT 1002;
02 is a write gate signal line connected to the gate electrode 02. Further, 1004 (1004a, 1004b) is a current controlling TFT, and 1005 is a capacitor (which can be omitted). 1006 is a current supply line, 1
Reference numeral 007 denotes an erasing TFT, and the erasing gate signal line 10
08. Note that reference numeral 1009 denotes an EL element.
Reference numeral 1010 denotes an opposite power supply.

The drain of the erasing TFT 1007 is connected to the gate electrode of the current controlling TFT 1004 so that the gate voltage of the current controlling TFT 1004 can be forcibly changed. The erasing TFT 10
07 is an n-channel TFT and a p-channel TFT
However, the structure is preferably the same as that of the switching TFT 1002 so that the off current can be reduced.

In this embodiment, the current controlling TFT 100
As No. 4, a first current control TFT 1004a and a second current control TFT 1004b are provided in parallel. Thus, the heat generated by the current flowing through the active layer of the current control TFT can be efficiently radiated, and deterioration of the current control TFT can be suppressed. Further, it is possible to suppress variations in drain current caused by variations in characteristics such as the threshold value and mobility of the current control TFT.

In this embodiment, two TFTs, a first current control TFT 1004a and a second current control TFT 1004b, are used as the current control TFTs, but the present embodiment is not limited to this. In each pixel, the number of TFTs used as current control TFTs may be two or more.

FIG. 10B is a cross-sectional view of the light emitting device of this embodiment, which has almost the same structure as that of the light emitting device of the third embodiment.
As described in the description above, there are two current control TFTs, and they are formed in parallel, and this will be described.

In FIG. 10B, the current controlling TFT
1004 includes a first current controlling TFT 1004a and a second current controlling TFT 1004b. The first
Drain 1032a of the current controlling TFT 1004a
Are connected to the EL element 1009 via the drain wiring 1036a.
Is electrically connected to the pixel electrode 1043. Also,
The drain 1032 of the second current controlling TFT 1004b
Similarly, the EL element 1 is connected to the EL element 1 via the drain wiring 1036b.
009 is electrically connected to the pixel electrode 1043.
Note that each of the structures of the first current control TFT 1004a and the second current control TFT 1004b is formed such that the gate electrode does not overlap with the source region and the drain region with the gate insulating film interposed therebetween.

The first current controlling TFT 1004a
Gate electrode 1034 (1034a, 1034b) and gate electrode 10 of second current controlling TFT 1004b.
35 (1035a, 1035b) is the switching T
Drain 1012 and drain wiring 101 of FT1002
6 are electrically connected. Note that the erasing TF
Drain 1022 of T1007 and drain wiring 1026
Are electrically connected via

In this embodiment, the structures of the switching TFT 1002 and the erasing TFT 1007 are formed such that the gate electrode does not overlap the LDD region via the gate insulating film.

In the present embodiment, only the structure of the pixel portion has been described.
Has the same configuration as that shown in FIG. Further, the configuration of this embodiment can be implemented by freely combining with any configuration of the first to fourth embodiments.

[Embodiment 6] In this embodiment, a case where a light emitting layer is formed for each of a plurality of pixel columns, which is different from the light emitting layer described in the embodiment of the present invention, will be described with reference to FIG.

In FIG. 11A, a source side driver circuit 1102 and a gate side driver circuit 1103 are provided over a substrate 1101.
And a pixel portion 1104 are formed. Note that the pixel portion 1
In FIG. 11B, a light-emitting layer is formed for each of a plurality of pixel columns, and an enlarged view of the pixel portion 1104 is shown in FIG.

In FIG. 11B, a pixel 1105 is
A plurality of them are formed vertically and horizontally. The pixel 11
Reference numeral 05 is formed by a gate line (G1), a source line (S1), and a current supply line (V1) provided in the pixel portion.

In this embodiment, the gate lines (G1 to G
y), a pixel column having a source line (S1) and a current supply line (V1) is called m1, and a pixel column having gate lines (G1 to Gy), a source line (S2) and a current supply line (V2) is m2. Further, a pixel column including a gate line (G1 to Gy), a source line (Sx), and a current supply line (Vx) is denoted by m.
Let's call it x.

In the present embodiment, a light emitting layer a (1106a) is formed in a pixel row composed of m1 and m2, and a pixel row m3 is set as a spare area a (1107a). The light emitting layer b (1106b) is formed, and the pixel row m
After setting x-1 as the spare area b (1107b), the pixel row m
A light emitting layer c (1106c) is formed on x. Note that formation of the light-emitting layer is omitted because the same method as that described in the embodiment mode of the invention may be used.

The structure of the pixel portion shown in this embodiment is different from the pixel portion shown in FIG. 1B not only in the shape of the light emitting layer but also in the circuit configuration. This is because it is necessary to connect to a different current supply line for each light emitting layer. In the pixel portion of this embodiment, the current supply lines (V1 to V1
x) are formed in parallel and alternately with the source lines (S1 to Sx).

When a light emitting layer having a shape different from that shown in this embodiment is formed, it is necessary to make a circuit configuration such that a different current supply line is connected to each light emitting layer.

The structure of this embodiment can be implemented by freely combining with any of the structures of Embodiments 1 to 5.

[Embodiment 7] In driving the light emitting device of the present invention, an analog drive using an analog signal as an image signal or a digital drive using a digital signal can be performed.

When analog driving is performed, an analog signal is sent to the source wiring of the switching TFT, and the analog signal including the gradation information becomes the gate voltage of the current controlling TFT. Then, a current flowing through the EL element is controlled by the current control TFT, and the emission intensity of the EL element is controlled to perform gradation display. Note that in the case of performing analog driving, the current control TFT is preferably operated in a saturation region.

On the other hand, when digital driving is performed, gradation display called time-division driving is performed, unlike analog gradation display. That is, by adjusting the length of the light emission time, the color gradation is visually changed. When digital driving is performed, the current control TFT is preferably operated in a linear region.

[0178] Since the EL element has a much higher response speed than the liquid crystal element, it can be driven at a high speed. Therefore, it can be said that the element is suitable for time division driving in which one frame is divided into a plurality of subframes and gradation display is performed.

As described above, since the present invention is a technology relating to the element structure, any driving method may be used.

The structure of this embodiment can be implemented by freely combining with any of the structures of Embodiments 1 to 6.

[Embodiment 8] In the embodiment 1, the case of the top gate type TFT was described. However, since the present invention is not limited to the TFT structure, as shown in FIG. May be implemented using an inverted staggered TFT. Further, the inverted staggered TFT may be formed by any means.

FIG. 12A shows a bottom gate type T
In manufacturing a light-emitting device using FT, the formed EL
It is a top view of a module. Source-side drive circuit 120
1, a gate side driving circuit 1202 and a pixel portion 1203 are formed. In FIG. 12A, xx ′
Area a12 of the pixel portion 1203 when the light emitting device is turned off at
FIG. 12B shows a cross-sectional view of No. 04.

In FIG. 12B, only the current controlling TFT among the pixel TFTs will be described. Reference numeral 1211 denotes a substrate, and 1212 denotes an insulating film serving as a base (hereinafter, referred to as a base film). As the substrate 1211, a light-transmitting substrate, typically, a glass substrate, a quartz substrate, a glass ceramic substrate,
Alternatively, a crystallized glass substrate can be used. However, it must withstand the maximum processing temperature during the manufacturing process.

Although the base film 1212 is particularly effective when a substrate containing mobile ions or a substrate having conductivity is used, the base film 1212 may not be provided on a quartz substrate. Underlayer 12
As 12, an insulating film containing silicon (silicon) may be used. In this specification, “an insulating film containing silicon”
Specifically, oxygen or nitrogen is contained at a predetermined ratio with respect to silicon such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film (SiOxNy: x and y are represented by arbitrary integers). Refers to an insulating film.

Reference numeral 1213 denotes a current control TFT, which is formed by a p-channel TFT. As shown in this embodiment, when the EL emission direction is the upper surface of the substrate (the surface on which the TFT and the EL layer are provided), the switching TFT is n.
It is preferable that the TFT be formed of a channel TFT and the current control TFT be formed of an n-channel TFT. However, the present invention is not limited to this configuration. The switching TFT and the current control TFT are n-channel TFs.
Either T or p-channel TFT may be used.

The current controlling TFT 1213 includes an active layer including a source region 1214, a drain region 1215, and a channel forming region 1216; a gate insulating film 1217; a gate electrode 1218; a first interlayer insulating film 1219; It is formed with the drain wiring 1221. In this embodiment, the current controlling TFT 1213
Is an n-channel TFT.

The drain region of the switching TFT is connected to the gate electrode 1218 of the current controlling TFT 1213. Although not shown, specifically, the gate electrode 1218 of the current controlling TFT 1213 is electrically connected to a drain region (not shown) of the switching TFT via a drain wiring (not shown). Note that the gate electrode 1218 has a single-gate structure, but may have a multi-gate structure. The source wiring 1220 of the current controlling TFT 1213 is connected to a current supply line (not shown).

The current controlling TFT 1213 is the EL element 12
30 is an element for controlling the amount of current injected into 30.
A relatively large amount of current flows. Therefore, it is preferable that the channel width (W) is designed to be larger than the channel width of the switching TFT. In addition, the current controlling TFT 1
The channel length (L) is preferably designed to be long so that an excessive current does not flow through 213. Desirably, 0.5 to 2 μA per pixel (preferably 1 to 1.5 μA)
A).

Further, the thickness of the active layer (particularly, the channel forming region) of the current controlling TFT 1213 is increased (preferably 50 to 100 nm, more preferably 60 to 8 nm).
0 nm), deterioration of the TFT may be suppressed.

After forming the current controlling TFT 1213, a first interlayer insulating film 1219 and a second interlayer insulating film (not shown) are formed, and a pixel electrode 1223 electrically connected to the current controlling TFT 1213 is formed. Is done. In this embodiment, the pixel electrode 1223 made of a conductive film is
It functions as 30 cathodes.

Specifically, an alloy film of aluminum and lithium is used, but a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

After the pixel electrode 1213 is formed, a third interlayer insulating film 1224 is formed. Note that the third interlayer insulating film 1224 functions as a so-called bank.

Next, an EL layer 1225 is formed. Note that FIG. 12B is a cross-sectional view in which pixel columns in which the same EL layer is formed are arranged.

The EL layer in this example used Alq3 as the electron injection layer, BCP as the electron transport layer, and a CBP doped with Ir (ppy) 3 as the light emitting layer. Further, a hole transport layer was formed using α-NPD.

Next, an anode 1226 made of a transparent conductive film is formed on the EL layer. In this embodiment, a conductive film made of a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used as the transparent conductive film.

Further, by forming a passivation film made of an insulating material on the anode, an inversely staggered TFT is formed.
An EL module having a structure can be formed.
Note that the light emitting device manufactured according to this embodiment is the same as that shown in FIG.
Light can be emitted in the direction (upper surface) of the arrow (B).

The inverted staggered TFT has a structure in which the number of steps is easily reduced as compared with that of the top gate type TFT, and thus is very advantageous in reducing the manufacturing cost, which is an object of the present invention.

The structure of this embodiment can be implemented by freely combining with any of the structures of Embodiments 1 to 7.

[Embodiment 9] Since the light emitting device of the present invention is a self-luminous type, it has excellent visibility in a bright place and a wide viewing angle as compared with a liquid crystal display. Therefore, it can be used as a display portion of various electric appliances.

[0200] Such electric appliances of the present invention include a navigation system, a sound reproducing device (car audio,
Audio components), game machines, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), devices having a display capable of reproducing a recording medium and displaying its image, and the like. In particular,
For a portable information terminal that is often viewed from an oblique direction, it is important to use a light emitting device because the width of the viewing angle is important. Specific examples of these electric appliances are shown in FIGS.

FIG. 13A shows a display device,
01, a support 1302, a display unit 1303, and the like. Note that the display unit 1303 is housed, and appears by opening it in the direction of the arrow at the time of use. The operation buttons 1304 are also covered with the display unit 1303 when not in use, but appear when the display unit 1303 is opened.

[0202] The light emitting device of the present invention can be used for the display portion 1303. Note that the light-emitting device of the present invention is a self-luminous type and does not require a backlight, and can be a display portion thinner than a liquid crystal display.

FIG. 13B is a destination display version of a train or a bus used at a station or a bus stop, and includes a main body 1310, a display unit 1311, a mounting unit 1312, and the like. The light emitting device of the present invention can be used for the display portion 1311. As a result, the display can be classified according to the type of the train or the route or the destination.

FIG. 13C shows a game machine,
21, a display unit 1322, an operation button a1323, an operation button b1324, a speaker unit 1325, and the like. The light emitting device of the present invention can be used for the display portion 1322.

[0205] Further, the electric appliances often display information distributed through an electronic communication line, and in particular, opportunities to display moving image information are increasing. Since the response speed of the EL material is extremely high, the light emitting device of the present invention is preferable for displaying moving images.

FIG. 14A shows a mobile phone,
01, audio output unit 1402, audio input unit 1403, display unit 1404, operation switch 1405, antenna 1406
including. The light-emitting device of the present invention can be used for the display portion 1404. Note that the display portion 1404 can reduce power consumption of the mobile phone by displaying white characters on a black background.

FIG. 14B also shows a mobile phone.
Unlike (A), it is a two-fold type. Body 14
11, an audio output unit 1412, an audio input unit 1413, a display unit a1414, a display unit b1415, and an antenna 1416. Note that this type of mobile phone is not provided with an operation switch, but one of the display units a and b is provided on one of the display units as shown in FIGS. 14C, 14D, and 14E. It displays the character information and provides its function. The other display unit mainly displays image information. Note that the light emitting device of the present invention has a display portion a14.
14 or the display unit b1415.

FIG. 14F shows a sound reproducing device, specifically, a car audio.
2, including operation switches 1423 and 1424. The light-emitting device of the present invention can be used for the display portion 1422. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus. The display unit 1
The power consumption 422 can be suppressed by displaying white characters on a black background. This is particularly effective in a portable sound reproducing device.

[0209] In the portable electric appliance described in this embodiment, as a method for reducing power consumption, a sensor unit for detecting external brightness is provided, and when used in a dark place, a display unit is provided. To add a function such as lowering the brightness of the image.

[0210] As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electric appliances in various fields. Further, any configuration shown in the first to eighth embodiments may be applied to the electric appliance of the present embodiment.

[Embodiment 10] In this embodiment, a case where an SRAM is introduced in a pixel portion will be described. FIG. 15 is an enlarged view of the pixel 1504.

In FIG. 15, reference numeral 1505 denotes a switching TFT. The gate electrode of the switching TFT 1505 is connected to a gate signal line (G1 to G1) for inputting a gate signal.
Gn) is connected to a gate signal line 1506. One of the source region and the drain region of the switching TFT 1505 is one of the source signal lines (S1 to Sn) for inputting a signal.
7, the other is connected to the input side of the SRAM 1508. The output side of the SRAM 1508 is a current control TFT
1509 is connected to the gate electrode.

One of the source region and the drain region of the current control TFT 1509 is a current supply line (V1 to V1).
n) is connected to a current supply line 1510 which is one of the above, and the other is connected to an EL element 1511.

[0214] The EL element 1511 includes an anode and a cathode, and an EL layer provided between the anode and the cathode. When the anode is connected to the source region or the drain region of the current controlling TFT 1509, in other words, when the anode is a pixel electrode, the cathode is a counter electrode. Conversely, the cathode is a current control TF
When connected to the source or drain region of T1509, in other words, when the cathode is a pixel electrode, the anode serves as a counter electrode.

The SRAM 1508 has two p-channel TFTs and two n-channel TFTs. The source region of the p-channel TFT is Vddh on the high voltage side, and the source region of the n-channel TFT is the low voltage side. Vss. One p-channel TFT and one n-channel TFT are paired, and one SR
Two pairs of a p-channel TFT and an n-channel TFT exist in the AM.

Also, a pair of p-channel TFT and n
The channel type TFT has drain regions connected to each other. The gate electrodes of the paired p-channel TFT and n-channel TFT are connected to each other. The drain region of one pair of the p-channel TFT and the n-channel TFT is kept at the same potential as the gate electrode of the other pair of the p-channel TFT and the n-channel TFT. I'm dripping.

The drain region of one pair of p-channel and n-channel TFTs is an input side to which an input signal (Vin) enters, and the other pair of p-channel and n-channel TFTs The drain region of the type TFT is an output side where an output signal (Vout) is output.

The SRAM is designed to hold Vin and output Vout which is a signal obtained by inverting Vin. That is, if Vin is Hi, Vout becomes a Lo signal equivalent to Vss, and if Vin is Lo, Vout becomes Vd.
It becomes a Hi signal equivalent to dh.

As shown in this embodiment, in the case where one SRAM is provided for each pixel 1504, since the memory data in the pixel is held, the static image is stored in a state where most of the external circuits are stopped. Can be displayed. Thereby, low power consumption can be realized. Also,
It is also possible to provide a plurality of SRAMs for a pixel,
When a plurality of AMs are provided, a plurality of data can be held, so that a gray scale display based on a time gray scale can be performed.

The structure of this embodiment can be implemented by freely combining with any structure of Embodiments 1 to 9.

[0221]

According to the present invention, a multi-color active matrix type high-definition light emitting device can be easily realized. Further, by using a light-emitting layer made of a triplet compound among a plurality of light-emitting layers, power saving can be realized.

[Brief description of the drawings]

FIG. 1 illustrates a method for manufacturing a pixel portion of a light-emitting device of the present invention.

FIG. 2 illustrates a method for manufacturing a pixel portion of a light-emitting device of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the light-emitting device of Example 1.

FIG. 4 is a diagram showing a manufacturing process of the light-emitting device of Example 1.

FIG. 5 is a diagram showing a manufacturing process of the light-emitting device of Example 1.

FIG. 6 is a diagram showing a manufacturing process of the light-emitting device of Example 1.

FIG. 7 is a diagram showing a sealing structure of a light emitting device of Example 2.

FIG. 8 is a top view structure and a circuit diagram of a pixel portion of a light emitting device according to a third embodiment.

9A and 9B are a circuit diagram and a cross-sectional view of a pixel portion of a light-emitting device according to a fourth embodiment.

10A and 10B are a circuit diagram and a cross-sectional view of a pixel portion of a light-emitting device according to a fifth embodiment.

FIG. 11 illustrates a method for manufacturing a pixel portion of a light-emitting device of the present invention.

12A and 12B are a top view and a cross-sectional view of a light-emitting device according to an eighth embodiment.

FIG. 13 is a view showing a specific example of an electric appliance using the light emitting device of the ninth embodiment.

FIG. 14 is a diagram showing a specific example of an electric appliance using the light emitting device of the ninth embodiment.

FIG. 15 is a diagram illustrating a pixel portion of a light emitting device according to a tenth embodiment.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05B 33/08 H05B 33/08 33/14 33/14 A F term (Reference) 3K007 AB03 AB04 AB06 AB17 BA06 BB04 BB05 BB07 CA01 CB01 DA01 DB03 EA01 EB00 GA04 5C080 AA06 BB05 CC03 DD28 FF11 JJ03 JJ06 5C094 AA05 AA08 AA22 AA24 AA31 AA43 AA48 BA03 BA12 BA27 CA19 CA20 CA24 CA25 DA13 DB01 DB02 DB04 EA04 EA04 EA04 EB04 JA20 5G435 AA04 AA16 BB05 CC09 CC12 EE37 EE41 HH12 HH13 HH14 KK05 LL03 LL07

Claims (17)

[Claims] 1. An active matrix light-emitting device in which a pixel portion and a driver circuit are formed over an insulating surface, wherein the pixel portion has a plurality of EL layers, and the plurality of EL layers share the EL layer.
A light emitting device comprising a plurality of L elements. 2. An active matrix light-emitting device in which a pixel portion and a driver circuit are formed over an insulating surface, wherein the pixel portion has a plurality of EL layers, and the plurality of EL layers share the EL layer.
A light-emitting device, wherein a plurality of L elements are provided to form at least one display area. 3. An active matrix light-emitting device in which a pixel portion and a driver circuit are formed over an insulating surface, wherein the pixel portion has a plurality of EL layers provided continuously over a plurality of pixels. Each pixel has at least one TFT
A light-emitting device comprising: an EL element using the EL layer. 4. An active matrix light-emitting device in which a pixel portion and a driver circuit are formed over an insulating surface, wherein the pixel portion has a plurality of display regions each including a plurality of pixels and one EL layer; E sharing the same EL layer for each display area
A light-emitting device, wherein an L element is provided in the pixel. 5. The light emitting device according to claim 1, wherein the EL layer is formed in a plurality of continuous pixel rows. 6. The device according to claim 5, wherein the current supply line electrically connected to the current control TFT is arranged so as to be parallel to the direction in which the pixel rows are formed. Light emitting device. 7. The light emitting device according to claim 1, wherein the EL layer is formed in a plurality of continuous pixel columns. 8. The device according to claim 7, wherein a current supply line electrically connected to the current control TFT is arranged so as to be parallel to a direction in which the pixel columns are formed. Light emitting device. 9. The light emitting device according to claim 1, wherein the number of the EL layers is two to six. 10. A light-emitting device according to claim 1, wherein at least one EL layer contains a third transition element. 11. The light-emitting device according to claim 1, wherein one EL layer occupies a region of 70 to 90% of the entire EL layer. 12. The light-emitting device according to claim 1, wherein a spare region is provided between adjacent EL layers among the EL layers. 13. The light emitting device according to claim 12, wherein the EL element in the spare area does not emit light. 14. The method according to claim 12, wherein
A light emitting device, wherein 1 to 5 spare areas are provided. 15. A light emitting device according to claim 1, wherein the driving voltage is 1.2 to 10 V. 16. A light-emitting device according to claim 1, wherein a display method of a character display and a background display is switched when switching from operation to standby. 17. The light-emitting device according to claim 1, wherein the light-emitting device is a type selected from a display device, a destination display board, a game machine, a mobile phone, and a sound reproducing device. Light emitting device.