JP2002140064A - Device and method for image display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device equipped with a line flicker prevention function at a low cost. SOLUTION: In this scanning type image display device including a generating means which generates pixel data of respective pixels arrayed vertically and horizontally and constituting an image to be displayed, a storage means which stores the generated pixel data, and a display means which displays the image on a screen according to the pixel data read out of the storage means, the filtration-completed pixel data of the pixels constituting the image to be displayed are generated by replacing pixel data of one pixel generated by the generating means with other pixel data obtained by passing pixel data of multiple vertically successive pixels including one pixel through a low-pass filter and stored in the storage means and processes to store the pixel data in the storage means (steps S11-S14) are executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display apparatus having a function of preventing line flicker and a method of displaying an image so that line flicker does not occur.

[0002]

2. Description of the Related Art When displaying an image including many straight lines, such as a graphics image, on an interlaced scanning type image display device, all pixels on a specific line in the first field are white. , The pixels of the other lines located near are all black including the first field and the second field. When such an image is displayed as it is, the display of the first field and the second field
Since there is a 1/60 second time difference between the display of the field and the scanning line of the first field and the scanning line of the second field, the vertical positions are shifted from each other due to the interlaced scanning.
This particular line will change from white to black or black to white every 1/60 second. That is, the specific line in the first field repeats blinking at a cycle of 1/30 second, which causes a problem that so-called line flicker occurs and the display quality deteriorates.

In order to cope with such a problem, it is known that an image display device has a line flicker preventing function. FIG. 5 shows a configuration of a typical conventional image display apparatus having a line flicker prevention function. In FIG. 5, 5
1 is a first memory that holds pixel data, 52 is a second memory that holds pixel data, 53 is a first memory interface circuit that controls access to the first memory 51, and 54 is access to the second memory 52 , A second memory interface circuit 55, a first memory bus, a second memory bus 56, a CPU 57,
58 is a read control circuit, 59 is an arithmetic circuit, 60 is a video output circuit, and 61 is a TV monitor.

The operation of the above-described conventional image display apparatus having a line flicker prevention function will be described with reference to the flowchart of FIG. The CPU 57 generates pixel data corresponding to an image to be displayed, for example, a graphics image (step S51). When the pixel data is pixel data of the first field, the memory write request signal, the write address on the first memory 51, and the pixel data are written in the first memory 51 in order to write the pixel data into the first memory 51. It is sent to the memory bus 55. When the pixel data is data of a pixel in the second field, a memory write request signal and a second
The write address on the memory 52 and the pixel data are sent to the second memory bus 56.

[0005] These data and signals are first
Via the memory bus 55 or the second memory bus 56 of the first memory interface circuit 53 or the second memory bus 56
, And subjected to necessary conversion, and is provided to the first memory 51 or the second memory 52. Thus, the pixel data of the first field is stored in the first memory 51, and the pixel data of the second field is stored in the second memory 52 (step S5).
2). When the CPU 57 finishes storing all the pixel data for one frame in the first memory and the second memory (Step S
53) The read control circuit 58 is instructed to start reading pixel data for one frame.

If the memory addresses in the first memory 51 and the second memory 52 are appropriately associated with the display position on the screen of the TV monitor 61, the pixel data can be stored in the first memory 5
By reading out the data from the first or second memory 52 in a predetermined order, the pixel data can be arranged on the screen of the TV monitor 61 as shown in FIG.
In FIG. 7, A _{i, j} is the pixel data of the pixel on the first field, and B _{i, j} is the pixel data of the pixel on the second field. For example, A _{1, j} represents the pixel data of the j-th pixel on the first line of the first field, A _{2, j} represents the pixel data of the j-th pixel on the second line of the first field,
B _{1, j} represents the pixel data of the j-th pixel on the first line of the second field _, and B _{2, j} represents the second pixel of the second field.
Represents the pixel data of the j-th pixel on the line, and so on.

[0007] First, the read control circuit 58 sends a first memory interface circuit 53 from the first memory 51 to the first memory 51.
Via the memory bus 55, the pixel data A _1,1 of the first pixel on the first line of the first field and the second memory 5
2, the pixel data _B1,1 of the first pixel in the first line of the second field is simultaneously read out via the second memory interface circuit 54 and the second memory bus 56 (step S54). Next, the two read pixel data A _1,1 and B _1,1 are input to the arithmetic circuit 59, respectively. The arithmetic circuit 59 calculates an average value C _1,1 = (A _1,1 + B _1,1 ) / 2 from these two pixel data A _1,1 and B _1,1 and calculates the average value as a video. This is given to the output circuit 60 (step S55). In the video output circuit 60, the average value C
₁ , ₁ is converted into a signal format suitable for display on the TV monitor 61 and output (step S56). Therefore, at the beginning of the first line of the first field on the screen of the TV monitor 61,
In the original pixel data A _{1, 1} without the mean value of A _{1, 1} and B _1,1 C _1,1 =
Pixel data equal to (A _1,1 + B _1,1 ) / 2 is arranged (step S57).

Next, in the same manner as described above, the read control circuit 58 determines the pixel data A _1,2 of the second pixel of the first line of the first field and the pixel data of the second pixel of the first line of the second field. Data B ₁ and B are read simultaneously. From the two read pixel data A _1,2 and B _1,2 , an average value C _1,2 = (A _1,2 + B _1,2 ) / 2 is calculated in the same manner as described above. T
2 of the first line of the first field of the screen of the V monitor 61
In the third position, not pixel data A _1,2 but A _1,2 and B _1,2
Of pixel data equal to the average value C _1,2 = (A _1,2 + B _1,2 ) / 2. The above operation is repeated until all the pixel data of the first line of the first field are arranged.

Next, in order to display the second line of the first field, the read control circuit 58 reads A _2,1 and B _2,1 simultaneously (step S54), and their average value C _2,1 = (A
_(2,1 + B _2,1 ) / 2 is calculated (step S55). In the same manner as above, the first position of the second line of the first field of the TV monitor 61 is not the original pixel data A _2,1 but the original pixel data A _2,1 .
Pixel data equal to the average value C _2,1 = (A _2,1 + B _2,1 ) / 2 of A _2,1 and B _2,1 is arranged.

When the display of all the lines in the first field is completed in this manner, subsequently, the read control circuit 5
8 stores pixel data B _1,1 of the first pixel on the first line of the second field and pixel data A _2,1 of the first pixel on the second line of the first field in the second memory 52 and the first memory 51, respectively. At the same time, and their average value D _1,1 =
(B _1,1 + A _2,1 ) / 2 is calculated. At the beginning of the first line of the second field of the TV monitor 61, the original pixel data B
Instead of _1,1 , the average value of B _1,1 and A _2,1 D _1,1 = (B _1,1 +
A _2,1 ) / 2 pixel data is arranged. Hereinafter, the same operation as in the case of the first field is performed, and the second
Complete the display of all lines in the field. Thereby, an image for one frame is displayed (step S5).
8). FIG. 8 shows an array of pixel data of an image displayed by the above operation. This operation is repeatedly executed until a display stop instruction is issued, and the array of pixel data shown in FIG. 8 is supplied to the TV monitor screen to display a still image.

Here, as in the case described above, in FIG. 7, all the pixels on the second line of the first field of the image stored in the first and second memories are white (the pixel value is 1).
00) and all the pixels on the other lines are black (pixel value is 0), as is clear from FIG.
The pixels of the second line of the first field and the pixels of the first line of the second field all have a pixel value of 50 in the screen of the display device having the conventional flicker prevention function, and the pixels of the other lines are All have a pixel value of zero. Accordingly, since white horizontal lines are present in both the first field and the second field, and the luminance of these white lines is also half of the luminance of the white lines of the original image, the line flicker is considerably reduced. .

[0012]

As described above, the conventional image display device having the function of preventing line flicker can display a graphics image or the like without generating line flicker. However, in the case of a normal image display device having no line flicker prevention function, only one memory access system including the image storage memory, the memory interface circuit, and the memory bus is required. In a display device having functions, it is necessary to provide two independent memory access systems, which increases the manufacturing cost.

This is because, in an ordinary image display device having no line flicker prevention function, the reading speed of the pixel data from the memory, that is, the sampling frequency of the original image is typically, for example, 13.5 MHz ( In contrast, in the case of an image display device having the above-described line flicker prevention function, two pixel data are read out within the same sampling period, and the average value is calculated. This is because it is necessary and high-speed processing is required.

If a high-speed memory element and a memory bus having a wide bus width are used, and each pixel data is read out in a time period of, for example, half of 74 ns by a time division operation, one memory access system can be obtained. You can do it,
High-speed memory elements and wide memory buses are expensive, and this also increases the manufacturing cost of the device.

The present invention has been made to solve the above-described problem, and has as its object to provide an image display device having a line flicker preventing function at low cost. It is another object of the present invention to provide a method for displaying an image without causing line flicker by using an image display device that does not include a high-speed memory element and a memory bus having a wide bus width.

[0016]

SUMMARY OF THE INVENTION The object of the present invention is to provide a means for generating pixel data of each pixel constituting a picture to be displayed, which are arranged vertically and horizontally, and for storing the generated pixel data. In a scanning-type image display device including a storage unit that performs, and a display unit that displays an image on a screen according to pixel data read from the storage unit, the pixel data of one pixel generated by the generation unit is A filter for each pixel constituting the image to be displayed by replacing pixel data of a plurality of vertically continuous pixels including the one pixel with another pixel data obtained by passing through a low-pass filter. Filter means for generating processed pixel data, wherein the filtered pixel data is stored in the storage means for displaying the image. It is solved by that the image display device.

The pixel data generated by the generating means and the filtered pixel data generated by the filtering means may be stored in different areas in the storage means for displaying the image.

Either storing only the pixel data generated by the generation means in the storage means, storing only the filtered pixel data generated by the filter means in the storage means, or generating the pixel data by the generation means The image processing apparatus may further include a selection unit that selects and executes either one of storing the processed pixel data and the filtered pixel data generated by the filter unit in different areas of the storage unit.

The selecting means stores only the pixel data generated by the generating means in the storage means when displaying the image by sequential scanning, and the filtering means when displaying the image by interlaced scanning. When only the generated filtered pixel data is stored in the storage unit, and the image is displayed by both the sequential scanning and the interlaced scanning, or when it is not possible to specify whether to display the image by the sequential scanning or the interlaced scanning. Can store the pixel data generated by the generation unit and the filtered pixel data generated by the filter unit in different areas in the storage unit.

[0020] The filter means may use the average value of the pixel data of two pixels of the first field and the second field adjacent to each other in the vertical direction as the other pixel data.

Another object of the present invention is to provide a generating means for generating pixel data of each pixel which is arranged in a vertical direction and a horizontal direction and constitutes an image to be displayed, and a storage means for storing the generated pixel data. Display means for displaying an image on a screen according to the pixel data read from the storage means, and pixel data of one pixel generated by the generation means,
A filter for each pixel constituting the image to be displayed by replacing pixel data of a plurality of vertically continuous pixels including the one pixel with another pixel data obtained by passing through a low-pass filter. In an image display method in a scanning type image display device including a filter unit that generates processed pixel data, an operation of storing pixel data generated by the generation unit in the storage unit is performed for all pixels of one frame. A first step of repeatedly executing until the pixel data is stored in the storage means, and reading out the pixel data from the storage means, and processing the read-out pixel data by the filter means to obtain the filtered pixel data. The operation of generating and storing again in the storage means is repeatedly performed for all the pixels of the one frame. It is solved by an image display method characterized by comprising a second step of.

The pixel data generated in the first step and stored in the storage means can be overwritten with the filtered pixel data in the second step.

[0023] The filtered pixel data generated in the second step may be stored in an area different from the area in the storage means that stores the pixel data generated in the first step. it can.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram illustrating a configuration of an image display device according to a first embodiment of the present invention having a line flicker prevention function. In FIG. 1, 1
1 is a memory for holding pixel data, 12 is a memory interface circuit for controlling access to the memory 11, 13 is a memory bus, 14 is a CPU, 15 is a read control circuit, 16 is a video output circuit, and 17 is a TV monitor.

The operation of the apparatus of the first embodiment will be described with reference to the flowchart of FIG. The CPU 14 generates pixel data of an image to be displayed on the TV monitor (Step S).
11). However, unlike the related art, one pixel data is not generated and written to the memory, but a plurality of pixel data (for example, two pixel data or three pixel data) is used.
Are continuously generated and sent to a vertical low-pass filter (VLPF) that performs an averaging process (step S1).
2). Although not shown in FIG. 1, this vertical low-pass filter is a filter realized by the CPU 14 executing a program stored in a memory (not shown).

The CPU 14 has, for example, a 2-tap VLPF.
Is used, pixel data A _{i, j} and B _{i, j} of the original image are first generated (for arbitrary i and j), and C _{i, j} = (A
_{i, j} + B _{i, j} ) / 2 or pixel data B
_{i, j} and A _{i + 1, j} are generated, and D _{i , j} = (B _{i, j} + A _{i + 1, j} ) /
2 is calculated. Next, the CPU 14 calculates the pixel data C _{i, j} = (A _{i, j} + B _{i, j} ) / 2 generated by the VLPF processing.
_{Alternatively, Di, j} = ( _{Bi, j} + _{Ai + 1, j} ) / 2 is stored in the memory 11 (step S13).

As described above, the averaging process, that is, the VLP
The pixel data on which the F processing has been performed is generally pixel data that enables display with reduced line flicker. CP
The U14 repeats this operation to store the pixel data (averaged pixel data) of one frame for which line flicker has been prevented in the memory 11 (step S14). That is, the memory 11 stores the pixel data of the arrangement shown in FIG.

When all the pixel data for one frame has been stored in the memory, the CPU 14 instructs the read control circuit 15 to prevent the line flicker stored in the memory 11 in order to display the image on the TV monitor 17. Is given. The read control circuit 15
In response to this instruction, the first pixel data C _1,1 of the first line of the first field is read from the memory 11 via the memory interface circuit 12 and the memory bus 13 (step S15). The read pixel data C _{1 , 1} is supplied to the video output circuit 16, which converts the pixel data into a signal format suitable for displaying on the TV monitor 17 and outputs it (step S 16). . Thus, at the beginning of the first line of the first field of the screen of the TV monitor 17, not the original pixel data A _1,1 but pixel data C _1,1 = (A _1,1 + B) for which line flicker prevention has been prevented. _1,1 ) /
2 are arranged (step S17).

Next, the readout control circuit 15 reads out the second pixel data C1, ₂ on the first line of the first field in the same manner as described above. The read pixel data C _1,2 is supplied to the TV monitor 17 via the video output circuit 16, and as pixel data A _1,2 of the original image as second pixel data on the first line of the first field. Will be displayed instead. In this manner, the pixel data C _{i, j} of the first field which has been subjected to the line flicker prevention is sequentially read from the memory 11, and the image of the first field which has been subjected to the line flicker prevention is displayed on the TV monitor 17. You.

Next, the read control circuit 15 reads the first pixel data _D1,1 on the first line of the second field.
The read pixel data D _1,1 is supplied to the TV monitor 17 via the video output circuit 16, and
At the beginning of the line, not the original pixel data B _1,1 but the pixel data D _1,1 = (B _1,1 +
A _{2 , 1} ) / 2 are arranged.

In the same manner, the pixel data D _{i , j} of the second field which has been subjected to the line flicker prevention is sequentially read out from the memory 11, and is displayed on the TV monitor 17 in the second field. The image is displayed. Thereby, an image for one frame is displayed (step S18). This operation is repeatedly executed until a display stop instruction is issued, and the arrangement of the pixel data shown in FIG. 8 is displayed on the screen of the TV monitor 17 as a still image with line flicker prevention measures taken.

As described above, the process of converting the original pixel data of FIG. 7 into the pixel data with line flicker countermeasures as shown in FIG. 8 is performed when the pixel data generated by the CPU 14 is stored in the memory 11. (That is, memory 1
It is not performed at the time of reading pixel data from 1). Therefore, since real-time processing is not required for this pixel data conversion processing, one sampling period of the original image (typically, 74n
Sec) generates A _{1, 1} and B _{1, 1} to the further calculates the C _{1, 1,}
It is not necessary to store this in the memory. For example, this series of processing may be performed within two sampling periods. Therefore, unlike the conventional device described with reference to FIG. 5, the device of the present embodiment does not need to include two independent memory access systems that can operate independently. Further, it is not necessary to provide an expensive memory element having a response speed twice or more that of a normal element or an expensive memory bus having a bus width twice or more of a normal bus.

The VLPF used in the display device of the present invention is not limited to the two-tap type used in the first embodiment, and various types different from those can be used. The following are some examples. Hereinafter, A _{i, j} represents original pixel data of the first field, and B _{i, j} represents original pixel data of the second field. (1) Example of 2-tap VLPF (provided in the above-described conventional apparatus and the apparatus of the first embodiment) C _{i, j} = (A _{i, j} + B _{i, j} ) / 2: D _i for first field display _{, j} = (B _{i, j} + A _{i + 1, j} ) / 2: for displaying the second field (2) Another example of a 2-tap VLPF C _{i, j} = (A _{i, j} + B _{i-1, j} ) / 2: For first field display D _{i, j} = (B _{i, j} + A _{i, j} ) / 2: For second field display (3) Example of 3-tap VLPF C _{i, j} = (B _{i− 1, j} + 2A _{i, j} + B _{i, j} ) / 4: for displaying the first field D _{i, j} = (A _{i, j} + 2B _{i, j} + A _{i + 1, j} ) / 4: for displaying the second field ( 4) Example of (2n + 1) tap VLPF C _{i, j} = h (n) * B _{i- (n-1), j} + h (n-1) * A _{i- (n-2), j} + ·・ ・ + H (1) * B _{i-1, j} + h (0) * A _{i, j} + h (1) * B _{i, j} + ・ ・ ・ ・ ・ ・ + h (n-1) * A _{i + ( n-2), j} + h (n) * B _{i + (n-2), j} : D _{i, j} for displaying the first field = h (n) * A _{i- (n-2), j} + h ( n-1) * B _{i- (n-2), j} + ... + h (1) * A _{i, j} + h (0) * B _{i, j} + h (1) * A _{i + 1, j} + ... + h (n-1) * B _{i + (n-2), j} + h (n) * A _{i + (n-1), j} : For displaying the second field, h (0) + 2 * h (1) + 2 * h (2) + ... + 2 * h (n) = 1

Embodiment 2 In the first embodiment, only the pixel data subjected to the VLPF processing is stored in the memory 11 in step S14 of FIG. 2, but in the second embodiment, the original pixel data and the pixels subjected to the VLPF processing are stored as shown in FIG. Both data are stored in the original image storage area and the line flicker countermeasure image storage area prepared in the memory 11, respectively. The configuration of the device of Embodiment 2 is shown in FIG.
And the overall operation is the same as that shown in the flowchart of FIG. In this way, at the time of reading from the memory 11, any pixel data can be selected and displayed according to the user's preference.

Embodiment 3 FIG. In the third embodiment, an original image storage area and an image storage area with line flicker countermeasures are provided in the memory 11 as in the second embodiment, but in step S13 in FIG. 2, only the original pixel data is stored in the original image. It is possible to select one of three types: storing in an area, storing only pixel data subjected to VLPF processing in a line flicker-prevented image storage area, or storing both of these pixel data in respective areas. The configuration of the device of the third embodiment is the same as that shown in FIG. 1, and the overall operation is the same as that shown in the flowchart of FIG. This has the effect that the time required to store the generated image data in the memory can be reduced in some cases.

Embodiment 4 FIG. In the fourth embodiment, the selection of the three modes of storing pixel data in the memory in the third embodiment is automatically executed as follows depending on the type of the display device. (1) When an image is displayed only on a display device of a progressive scanning type, only original pixel data is stored in a corresponding storage area. (2) When displaying an image only on a display device of the interlaced scanning (interlaced scanning) method, only the pixel data subjected to the VLPF processing is stored in the corresponding storage area. (3) At other times, both the original pixel data and the VLPF-processed pixel data are stored in the corresponding storage areas.

The configuration of the device according to the fourth embodiment is the same as that shown in FIG. 1, and the overall operation in the cases (2) and (3) is the same as that shown in the flowchart of FIG.
The overall operation in the case of (1) is the same as that shown in the flowchart of FIG. 2 except that step S12 is omitted. This has the effect that the time required to store the generated pixel data in the memory can be automatically reduced as the case may be. Further, an effect is obtained that pixel data more suitable for the method of the display device (sequential scanning or interlaced scanning) is automatically selected.

Embodiment 5 Embodiment 1, 2, 3, 4
Then, while the CPU 14 creates the original pixel data,
The LPF processing is also performed, and the pixel data subjected to the VLPF processing is stored in the memory. In the fifth embodiment, as shown in the flowchart of FIG. 3, the original pixel data for one frame is temporarily stored in the memory 11 ( Steps S21 and S2
3) After that, the original pixel data is sequentially read from the memory 11, the VLPF processing is performed, and the processing of storing the VLPF-processed pixel data in the memory 11 again is performed for each frame (step S24). ~
S27).

Operation of reading pixel data from memory, converting video output, and displaying on a monitor (steps S28 to S28)
S31) is the same as the operation in FIG. 2 (steps S15 to S18). This has the effect of simplifying the processing of the CPU in the pixel data generation stage and the VLPF processing stage.

Embodiment 6 FIG. In the sixth embodiment, in step S26 of the flowchart of FIG.
The second embodiment differs from the fifth embodiment in that the original pixel data stored in step 2 is overwritten with the VLPF-processed pixel data. However, a temporary holding area for temporarily holding several lines of VLPF-processed pixel data is provided in the memory 11, and the overwritten original pixel data is stored in the subsequent VLPF.
After the data is no longer used in the processing, the VLPF-processed pixel data is moved from the temporary holding area to the overwriting area. The configuration of the sixth embodiment is the same as that shown in FIG. 1, and the overall operation is the same as that shown in the flowchart of FIG. This has the effect of saving memory capacity.

Embodiment 7 FIG. In the seventh embodiment, as shown in FIG. 4, an original image storage area and an image storage area with line flicker countermeasures are provided in the memory 11, and in step S26 in FIG. 3, the area in which the original pixel data is stored in step S22. The fifth embodiment is different from the fifth embodiment in that VLPF-processed pixel data is stored in an area different from that of the fifth embodiment. In this way, at the time of reading from the memory 11, any one of the pixel data can be selected according to the user's preference and an image can be displayed.

[0042]

According to the first aspect of the present invention, the generated pixel data is stored in a memory after being subjected to a process for preventing line flicker by a vertical low-pass filter in advance and then stored in a memory. When displaying, there is no need to perform line flicker prevention processing on the pixel data read from the memory. Therefore, it is not necessary to read out the pixel data from the memory at a high speed, and it is sufficient to read out the pixel data at the sampling speed of the original image. Further, there is no need to use an expensive memory element having at least twice the response speed or an expensive memory bus having a double bus width.

According to the second aspect of the present invention, both the original pixel data and the pixel data subjected to the vertical low-pass filter processing are stored in different areas of the memory, respectively, so that the image display is performed. In this case, the pixel data read from the memory can be selected according to the user's preference.

According to the third aspect of the present invention, only the original pixel data is stored in the corresponding area in the memory, or only the pixel data subjected to the vertical low-pass filter processing is stored in the memory. Since it is possible to select whether to store the pixel data in the area or to store both of the pixel data in the corresponding areas in the memory, the time required for storing the pixel data in the memory can be reduced in some cases.

According to the fourth aspect of the invention, when an image is displayed on a display device of a progressive scanning system, only original pixel data is stored in a memory and an image is displayed on a display device of an interlaced scanning system. Is to store only the pixel data subjected to the vertical low-pass filter processing in the memory and display the image on both the progressive scan display device and the interlaced scan display device, or the scanning method of the display device. Is unknown, both the original pixel data and the pixel data subjected to the vertical low-pass filter processing are stored in different areas in the memory, respectively. There is an effect that it can be automatically shortened according to the condition. Further, an effect is obtained that pixel data more suitable for the method of the display device is automatically selected.

According to the fifth aspect of the present invention, the average value of the pixel data of the two pixels of the first field and the second field which are adjacent in the vertical direction is calculated. With such an arithmetic operation, there is an effect that pixel data with line flicker countermeasures can be obtained.

According to the invention described in claim 6, original pixel data for one frame is stored in a memory in advance, and the original pixel data is sequentially read from the memory and subjected to a filtering process.
Since the data is stored in the memory again, there is an effect that the processing of the CPU becomes simpler.

According to the invention of claim 7, according to claim 6,
In the invention described in (1), the original pixel data is overwritten with the filtered pixel data, so that the memory capacity can be saved.

According to the invention of claim 8, according to claim 6,
In the invention described in (1), both the original pixel data and the filtered pixel data are stored in the respective areas, so that when displaying an image, it is possible to select the pixel data to be read out according to the user's preference. can get.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image display device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of the image display device of FIG. 1;

FIG. 3 is a flowchart illustrating an operation of the image display device according to the fifth embodiment of the present invention.

FIG. 4 is a diagram showing an internal configuration of a memory in the image display devices according to Embodiments 2 and 7 of the present invention.

FIG. 5 is a configuration diagram of a conventional image display device having a line flicker prevention function.

FIG. 6 is a flowchart illustrating an operation of the image display device of FIG. 5;

FIG. 7 is a diagram illustrating an array of original pixel data on a screen of an image display device.

FIG. 8 is a diagram illustrating an array of pixel data on which a line flicker prevention measure has been taken on a screen of an image display device.

[Explanation of symbols]

11 memory, 12 memory interface circuit, 1
3 memory bus, 14 CPU, 15 read control circuit, 16 video output circuit, 17 TV monitor.

Claims (8)

[Claims] 1. A generating means for generating pixel data of each pixel which is arranged in a vertical direction and a horizontal direction and constitutes an image to be displayed, a storing means for storing the generated pixel data, and a readout from the storing means. In a scanning type image display device including: a display unit that displays an image on a screen according to pixel data, wherein pixel data of one pixel generated by the generation unit is vertically continued including the one pixel. Filter means for generating filtered pixel data of each of the pixels constituting the image to be displayed by replacing pixel data of a plurality of pixels with another pixel data obtained by passing through a low-pass filter. An image display device, wherein the filtered pixel data is stored in the storage means for displaying the image. 2. The method according to claim 1, wherein the pixel data generated by the generation unit and the filtered pixel data generated by the filter unit are stored in different areas in the storage unit for displaying the image. The image processing apparatus according to claim 1, wherein: 3. The method according to claim 1, wherein only the pixel data generated by the generation unit is stored in the storage unit, only the filtered pixel data generated by the filter unit is stored in the storage unit, or the generation unit is Selecting means for selecting and storing either of the pixel data generated by the above and the filtered pixel data generated by the filter means in different areas of the storage means. The image display device according to claim 1, wherein: 4. The image processing apparatus according to claim 1, wherein the selection unit stores only the pixel data generated by the generation unit in the storage unit when displaying the image by sequential scanning, and the filter unit stores the pixel data when displaying the image by interlaced scanning. Only the filtered pixel data generated by the means is stored in the storage means, and it is not possible to specify whether the image is displayed by both the sequential scanning and the interlaced scanning or whether the image is displayed by the sequential scanning or the interlaced scanning. 4. The method according to claim 3, wherein in the case, both the pixel data generated by the generation unit and the filtered pixel data generated by the filter unit are stored in different areas in the storage unit. Image display device. 5. The filter device according to claim 1, wherein the average value of pixel data of two pixels in a first field and a pixel in a second field which are vertically adjacent to each other is set as the another pixel data. The image display device according to claim 1. 6. A generating means for generating pixel data of each pixel which is arranged in a vertical direction and a horizontal direction and constitutes an image to be displayed, a storing means for storing the generated pixel data, and a readout from the storing means. Display means for displaying an image on a screen in accordance with the pixel data; and pixel data of one pixel generated by the generation means being converted to pixel data of a plurality of vertically continuous pixels including the one pixel. A filter means for generating filtered pixel data of each pixel constituting the image to be displayed by replacing the pixel data with another pixel data obtained by passing through a pass filter. In the display method, an operation of storing the pixel data generated by the generation unit in the storage unit may be performed by using pixel data of all pixels for one frame. A first step of repeatedly executing until the image data is stored in the storage unit, reading pixel data from the storage unit, and processing the read pixel data by the filter unit to generate filtered pixel data; A second step of repeatedly executing the operation of storing the data again in the storage means for all the pixels of the one frame. 7. The pixel data generated in the first step and stored in the storage unit is overwritten with the filtered pixel data in the second step. Image display method. 8. The filter-processed pixel data generated in the second step is stored in an area different from the area in the storage unit that stores the pixel data generated in the first step. 7. The method according to claim 6, wherein
The image display method described in 1.