JP2002134681A - Manufacturing method of hybrid integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that many man-hours are taken because the manufacturing method of the conventional manufacturing method of a hybrid integrated circuit device is arranged in a process for attaching from small-sized parts to large-sized parts in good order. SOLUTION: After chip parts 4 fixed by solder paste, a bump 1 and a power transistor 11 are collectively printed by a solder cream 3, they are collectively mounted, and a simple line making a plurality of the conventional solder melting processes one time is realized by collectively melting it in a N2 reflow solder melting furnace.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit device, and more particularly to a method for manufacturing a hybrid integrated circuit device having a simplified process.

[0002]

2. Description of the Related Art A conventional method for manufacturing a hybrid integrated circuit device will be described with reference to FIGS.

FIG. 13 is a process flow chart. Lot number printing, solder printing, chip mounting, silver paste stamp, small signal transistor solder, bump solder, solder melting, silver paste curing, fine wire bonder, earth bonder, power transistor solder , And a thick wire bonder. As is clear from this flow,
They are arranged in a process of attaching large components in order from small components. Further, since each step is constituted by a single-function manufacturing apparatus, a transfer facility is provided between each step, as will become clear later.

FIGS. 14 to 20 show sectional views of respective steps. In addition, even if it is not shown, a clear process is omitted in the drawings.

In a lot number printing step, a lot number for manufacturing control is printed on the opposite main surface of a hybrid integrated circuit board (hereinafter referred to as a board) with ink.

Next, as shown in FIG. 14, in the solder printing step, a substrate 1 made of an insulating substrate made of ceramic or glass epoxy resin or a substrate 1 made by insulating the surface of a metal substrate is used.
A conductive path 2 formed of a copper foil or a conductive paint of a desired pattern is formed on the surface of the substrate 1, and a solder cream 3 is selectively printed on a predetermined portion of the conductive path 2 by screen printing. A solder cream 3 is attached to the substrate.

Further, in the chip mounting step, as shown in FIG. 15, a chip component 4 such as a chip capacitor or a chip resistor, which is a standard component, is temporarily bonded onto the solder cream 3 using a medium speed chip mounter.

Subsequently, as shown in FIG. 16, in a silver paste stamping step, the silver paste 5 is adhered to the conductive path 2 on which the small signal transistor is mounted with a stamp needle having the silver paste 5 attached to the tip. Since the silver paste is made to have a low viscosity with an organic solvent, it is necessary to leave the organic solvent for about 7 hours to evaporate the organic solvent so that the organic solvent does not hinder the fixing during bonding.

Subsequently, in the small signal transistor soldering step as shown in FIG. 17, a small signal transistor chip 6 is mounted on the silver paste 5 adhered to the previous step using a semiconductor chip mounter.

Subsequently, as shown in FIG. 18, in a bump soldering step, a bump 7 made of a metal piece to which a semi-power transistor 8 is fixed in advance is applied to a predetermined conductive path 2 by using a multifunctional chip mounter for odd-shaped parts. Is placed on the silver paste 5 adhered by a dispenser.

Subsequently, although not shown, in the solder melting step,
The solder cream 3 is melted. That is, the substrate 1 is placed on a hot plate and heated at 210 ° C. for about 2 to 3 minutes to fix the chip component 4.

Subsequently, in a silver paste hardening step (not shown), a large number of substrates 1 are housed in a hardening furnace at about 150 ° C.
The curing of the silver paste 5 is performed in a reducing atmosphere for 4 to 5 hours in a batch process. Since the organic solvent generated during curing is immediately exhausted from the furnace, it is possible to prevent the organic solvent from adhering to the substrate 1.

Subsequently, the substrate 1 taken out of the curing furnace proceeds to a fine wire bonding step as shown in FIG. In the thin wire bonding step, the base and the emitter electrode of the semi-power transistor fixed to the small signal transistor 6 and the bump 7 are connected to the corresponding conductive path 2 by an aluminum bonding thin wire 9 having a diameter of about 50 μm by an ultrasonic bonder.

Subsequently, although not shown, the earth bonder step is a specific step when a metal substrate is used as the substrate 1, and is used to remove a parasitic capacitance caused by an insulating film between the conductive path 2 and the substrate 1. The path 2 is connected to the exposed metal substrate.

Subsequently, in the power transistor soldering step, as shown in FIG.
A block to which the power transistor 11 is fixed is mounted. Solder cream printed and melted in advance on the conductive path 2 is soldered. When mounting the block, the solder 12 is melted again on a hot plate and ultrasonic waves are applied so that no burrs are generated. Secure the block.

Finally, in the thick wire bonding step as shown in FIG. 21, the connection between the base electrode and the emitter electrode of the power transistor 11 and the predetermined conductive path 2 is performed by bonding the ultrasonic bonder with an aluminum bonding thick wire 13 having a diameter of about 300 μm. Perform using In this step, a jumper wire is formed between the conductive paths 2 requiring the cross wiring.

FIG. 22 shows a manufacturing line for realizing the conventional method for manufacturing a hybrid integrated circuit device described in detail above.

The substrate 1 on which the conductive paths 2 are formed in a desired pattern is accommodated in a magazine M and flows through each process.

First, the magazine M is placed in the loading device L for supplying the substrate in the lot number printing process, and the substrate 1 after printing is stored in the magazine M by the unloading device UL.

Next, in the solder printing process, the components carried in the magazine M from the previous process are set in the loading device L, and the substrates 1 in the magazine M are supplied one by one to supply the solder cream. 3 is performed, and the sheets are stored one by one in the magazine M set in the unloading device UL.

Further, in the chip mounting step, the chip parts 4 are mounted by two chip mounters, thereby leveling the processing capability of the step.

Similarly, a silver paste stamping step, standing at room temperature for about 7 hours, a small signal transistor soldering step, a bump soldering step, a solder melting step, a silver paste curing step,
The hybrid integrated circuit device is completed by flowing the thin wire bonder process, the earth bonder process, the solder printing process, the power transistor soldering process, and the thick wire bonder process in the form of a magazine M using the load device L and the unload device UL in order. However, since the curing furnace is used in the silver paste curing process,
A large number of magazines M are stored, and the number of magazines M that can be stored in a curing furnace in batch processing is stored and processed.

FIG. 23 is a top view of the hybrid integrated circuit device. Arranged on the upper side of the substrate 1 are electrodes for fixing external leads.
Extends. The chip component 4 corresponds to a component with a circuit symbol of a resistor or a capacitor. The small-signal transistor 6 corresponds to the small-signal transistor 6 which is mostly diamond-shaped on the conductive path 2, and is provided with a base electrode B and an emitter electrode E. Two small bonding wires 9 extend from the small signal transistor 6, and are connected to the conductive path 2. On the bump 7, a semi-power transistor requiring heat radiation is fixed. The four blocks arranged on the lower left side are the power transistors 11 on the heat sink 10.
Is a block to which is fixed. From the base electrode B and the emitter electrode E of the power transistor 11, two bonding thick lines 13 (shown thick in the figure) are connected to predetermined conductive paths 2. In this thick bonding wire 13, a jumper wire J and a ground wire A of a crossing conductive path are also formed.

[0024]

In the conventional method of manufacturing a hybrid integrated circuit device, since the steps of mounting the large components in order from the small components are arranged in order, the loading device is sequentially arranged in the form of a magazine M between the processes. L, unloading device UL
However, there is a problem that a transport facility for flowing using the method is required, and a large work area is required for the processing facility and the transport facility for each process.

Further, since the solder is melted in two places, the solder melting step after the chip mounting step and the power transistor soldering step, the solder cream printing step and the solder melting step overlap, which increases the number of steps. This has been a problem of prolonging the number of process days.

[0026]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned many problems, and includes a step of attaching a conductive brazing material to a desired conductive path of a hybrid integrated circuit board; A step of collectively mounting the circuit elements fixed by the conductive brazing material, and placing the hybrid integrated circuit board on a belt moving on a heater block provided in a melting furnace, and further using an infrared lamp from above. Heating and circulating a N ² gas to collectively melt the conductive brazing material and fix the circuit element to the conductive path. In particular, the chip parts, bumps and power transistors that are fixed with solder paste are mounted collectively after solder cream printing, and are immediately melted collectively in a solder melting furnace. Is realized.

In the present invention, the circuit element includes a fixed circuit element such as a chip component and an atypical circuit element such as a power transistor fixed to a heat sink, and the fixed circuit element and the atypical circuit element are continuously connected to each other. The feature is that it is mounted on the conductive path, and instead of arranging the small parts in the order of the conventional order in the process of attaching the large parts, the number of process days is reduced by focusing on the conductive brazing material that fixes the circuit elements. A method of manufacturing a hybrid integrated circuit device is provided.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a hybrid integrated circuit device according to the present invention will be described with reference to FIGS.

FIG. 1 is a process flow diagram. Lot number printing, solder printing, chip mounting, multifunctional mounter (bump solder, power transistor solder), solder melting, silver paste stamp / small signal transistor solder, silver paste curing, Fine wire bonder, earth bonder,
It consists of each step of the thick wire bonder. As is clear from this flow, the circuit elements fixed by the solder paste are collectively collected, thereby realizing the simplification of the process.

FIGS. 2 to 9 show sectional views of respective steps.
In addition, even if it is not shown, a clear process is omitted in the drawings. The same components as those in the related art are denoted by the same reference numerals.

In the lot number printing step, a lot number for manufacturing control is printed on the opposite main surface of the hybrid integrated circuit substrate (hereinafter, referred to as a substrate) by laser.

Next, in the solder printing process as shown in FIG.
A substrate 1 made of an insulating substrate made of ceramic or glass epoxy resin or a substrate 1 having a surface of a metal substrate insulated is prepared, and a conductive path 2 formed on the surface of the substrate 1 with a copper foil or a conductive paint of a desired pattern. Is formed, and the solder cream 3 is selectively printed on a predetermined portion of the conductive path 2 where chip components, bumps and power transistors are to be placed by screen printing. The feature of this step is that all the circuit elements fixed by the solder cream 5 are printed with the solder cream 5 in this step.

Further, in the chip mounting step, as shown in FIG. 3, a chip component 4 such as a chip capacitor or a chip resistor, which is a standard component, is temporarily bonded onto the solder cream 3 using a medium speed chip mounter.

Subsequently, as shown in FIG. 4, in the first half of the multi-function mounting process, a bump 7 made of a metal piece to which a semi-power transistor 8 is fixed in advance is prepared, and a predetermined multi-function chip mounter for a deformed part is used. Is temporarily bonded to the solder cream 3 on the conductive path 2.

Subsequently, in the latter half of the multi-function mounting process as shown in FIG. 5, a block in which the power transistor 11 is fixed on a heat sink 10 having good heat dissipation is prepared, and a multi-function chip mounter for odd-shaped components is similarly used. Then, it is temporarily bonded to the solder cream 3 on the predetermined conductive path 2. On this occasion,
The solder cream 3 is not melted.

Subsequently, in the solder melting step as shown in FIG.
The bump 7 and the heat sink 10 are fixed to the conductive path 2.

This step is characterized in that the solder cream 3 is heated and melted in an N ² reflow solder melting furnace.
The N ² reflow solder melting furnace includes a metal mesh belt 21 on which the substrate 1 is placed and moves at a constant speed.
, A discharge block 23 and a suction pipe 24 alternately arranged to reflow N ² gas on the upper surface of the substrate 1, and an infrared lamp 25 for heating the substrate 1 from the upper surface. . The substrate 1 is uniformly and quickly heated from both sides by the infrared lamp 25 and the heater block 22,
A reflow condition under which the block in which the power transistor 11 is fixed on the heat sink 10 can be optimally fixed (normal temperature at the time of input → 4 to 5 seconds at about 210 ° C. at the time of melting → 100 times at the time of cooling)
(Below 10 ° C.), the solder cream 3 is heated and melted at a time for 4 to 5 minutes. Further, since the reflow of the N ² gas is performed by the discharge pipe 23 and the suction pipe 24 which are close to each other as shown by arrows, there is no scattering of flux, no generation of solder balls, and oxidation of the surface of the conductive path 2 such as copper foil. Can be prevented. The solder melting furnace used in this step will be described later with reference to FIG.

Subsequently, as shown in FIGS. 7 and 8, the silver paste 5 is applied to the conductive path 2 on which the small signal transistor is mounted in the silver paste stamp / small signal transistor soldering process with a stamp needle having the silver paste 5 attached to the tip. A chip 6 of a small signal transistor is attached on the attached silver paste 5.
Is mounted using a semiconductor chip mounter.

In this step, the silver paste is made to have a low viscosity with an organic solvent, but since there is no heating step until the silver paste hardening step, there is no danger of the organic solvent being scattered. Immediately, the small signal transistor chip 6 is mounted and sent to the next step. In this step, since the silver paste 5 is not dried at normal temperature, the processing can be speeded up by being continuously processed in the semiconductor chip mounter.

Subsequently, in a silver paste curing step (not shown), a large number of substrates 1 are housed in a curing furnace,
The curing of the silver paste 5 is performed in a reducing atmosphere for 4 to 5 hours in a batch process. Since the organic solvent generated during curing is immediately exhausted from the furnace, it is possible to prevent the organic solvent from adhering to the substrate 1.

Subsequently, the substrate 1 taken out of the curing furnace shifts to a fine wire bonding step as shown in FIG. In the thin wire bonding step, the base and the emitter electrode of the semi-power transistor fixed to the small signal transistor 6 and the bump 7 are connected to the corresponding conductive path 2 by an aluminum bonding thin wire 9 having a diameter of about 50 μm by an ultrasonic bonder.

Subsequently, although not shown, the earth bonder process is a unique process when a metal substrate is used as the substrate 1, and is used to remove a parasitic capacitance caused by an insulating film between the conductive path 2 and the substrate 1. The path 2 is connected to the exposed metal substrate.

Finally, in the thick wire bonding step as shown in FIG. 10, the connection between the base electrode and the emitter electrode of the power transistor 11 and the predetermined conductive path 2 is performed by bonding the ultrasonic bonder with a thick aluminum bonding wire 13 having a diameter of about 300 μm. Perform using In this step, a jumper wire is formed between the conductive paths 2 requiring the cross wiring.

FIG. 11 shows a manufacturing line for realizing the method for manufacturing the hybrid integrated circuit device of the present invention described in detail above.

The substrate 1 on which the conductive paths 2 are formed in a desired pattern is accommodated in a magazine M and flows through each process.

The feature of the present invention resides in that the lot number printing step, the solder printing step, the chip mounting step, the multifunctional mounter step (bump solder, power transistor solder) and the solder melting step are integrated into one line. In these steps, the substrate 1 flows continuously and no transfer equipment is provided.

First, the magazine M is placed in the load device L for supplying the substrate 1, and the substrate 1 is sent to a lot number printing process. In this step, the lot number is printed on the back surface of the substrate 1 by laser printing, and a sending signal from the subsequent solder printing step is awaited. When the sending signal is received, the substrate 1 is sent to the next process, the lot number is printed on the next substrate 1, and the process waits.

Next, in the solder printing step, the substrates 1 are supplied one by one from the previous step, and the screen printing of the solder cream 3 is performed and the process is on standby.

Further, in the chip mounting step, the chip parts 4 are mounted by a medium-speed chip mounter and the apparatus stands by. Then using a multi-function chip mounter for deformed parts multifunctional mounter step, bump solder in the first half, performs power transistors solder later, immediately sent to the solder melting step, the solder cream with N ² reflow solder melting furnace 3
Is heated and melted. One sheet is stored in each magazine M of the unloading device UL.

Thereafter, a loading device L and an unloading device U are sequentially formed in the form of a magazine M in the order of a silver paste stamp / small signal transistor soldering process, a silver paste curing process, a thin wire bonding process, an earth bonding process, and a thick wire bonding process.
The hybrid integrated circuit device is completed by flowing using L.
However, since a curing furnace is used in the silver paste curing step, a large number of magazines M are stored in the same manner as in the related art, and the number of magazines M that can be stored in the curing furnace is accommodated and processed by batch processing.

FIG. 12 shows a solder melting furnace used in the present invention.

The metal mesh belt 21 has an endless structure and is driven by a motor to move in one direction at a constant speed. Therefore, the speed at which the substrate 1 comes out of the furnace is set to 4 to 5 minutes required for melting the solder.

A heater block 22 is provided below the belt 21, and an infrared lamp 25 is provided above the belt 21 at regular intervals.
Is provided. The substrate 1 is uniformly and quickly heated from both sides by the infrared lamp 25 and the heater block 22, and the block in which the power transistor 11 is fixed on the heat sink 10 can be optimally fixed. (4 to 5 seconds → 100 ° C. or less during cooling), and the solder cream 3 can be heated and melted at a time in 4 to 5 minutes.

The discharge pipe 23 and the suction pipe 2 which are alternately arranged on the belt 21 for reflowing N ² gas in close proximity to each other.
4 are provided. That is, five reflow chambers 26 storing N ² gas are arranged continuously above the belt 21, and the N ² gas is sent out from the discharge pipe 23 by a fan 27 provided on the ceiling of each reflow chamber 26. The suction pipes 24 are alternately arranged with the discharge pipes 23, and each suction pipe 24 has a fan 2.
A reflow is realized by immediately recovering the N ² gas sent out from the discharge pipe 23.

In the solder melting furnace used in the present invention described above,
Immediately after printing the solder cream 3, the chip component 4, bump 7 and heat sink 10 are fixed to the conductive path 2,
There is a feature that the heat sink 10 can be flowed under conditions where the solder can be melted. In particular, no flux is scattered by N ² reflow, no solder balls are generated, and oxidation of the surface of the conductive path 2 such as a copper foil can be prevented. Further, in the solder melting furnace used in the present invention, compared with the conventional N ² reflow apparatus, the amount of N ² consumed to create a reducing atmosphere having an oxygen concentration of 500 ppm or less which prevents oxidation of the surface of the conductive path 2 such as a copper foil. Is 500L /
250 L / mi by circulating N ² gas from min
n and half.

The completed hybrid integrated circuit device is the same as that shown in FIG. 23, but its manufacturing line is greatly shortened from the conventional one.

[0057]

According to the present invention, first, chip components, bumps, and power transistors to be fixed with a solder paste are collectively mounted after solder cream printing, and are collectively melted in a solder melting furnace. Thus, since a simple line in which the conventional multiple processes are integrated into one line is realized, the processes from the lot number printing process to the solder melting process can be continuously performed, and the number of processing days can be reduced to 0.5 days. In addition, the process can be performed in 1 to 1.5 days from the beginning to the silver paste curing step, and can be reduced to about 1/3 or less from the conventional 4 days.

Second, since the lot number printing process to the solder melting process are integrated into one line, transport equipment such as a loading device L and an unloading device UL provided before and after each process is not required, and the equipment area is greatly increased. And the amount of capital investment can be reduced.

Third, since the solder cream is heated and melted in a batch in an N ² reflow solder melting furnace, the chip parts, bumps and heat sink can be fixed at the same time. There is no generation, and oxidation of the conductive path surface such as copper foil can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 3 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 5 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 6 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 7 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 8 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 9 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 10 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 11 is a diagram illustrating a method of manufacturing a hybrid integrated circuit device according to the present invention.

FIG. 12 is a diagram illustrating a solder melting furnace used in the method for manufacturing a hybrid integrated circuit device of the present invention.

FIG. 13 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 14 is a diagram illustrating a method for manufacturing a conventional hybrid integrated circuit device.

FIG. 15 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 16 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 17 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 18 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 19 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 20 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 21 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 22 is a diagram illustrating a method of manufacturing a conventional hybrid integrated circuit device.

FIG. 23 is a diagram illustrating the present invention and a conventional hybrid integrated circuit device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Hybrid integrated circuit board 2 Conductive path 3 Solder paste 4 Chip component 5 Silver paste 6 Small signal transistor 7 Bump 10 Heat sink 11 Power transistor

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiji Maehara 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5E319 AA03 AC01 BB05 CC33 CC45 CD29 CD35 GG15

Claims (4)

[Claims] A step of attaching a conductive brazing material to a desired conductive path of a hybrid integrated circuit board; and a step of mounting at least a circuit element fixed on the conductive path with the conductive brazing material. The hybrid integrated circuit board is placed on a belt moving on a heater block provided in a melting furnace, and further heated from above by an infrared lamp and N ² gas is circulated to melt the conductive brazing material at once. Fixing the circuit element to the conductive path. 2. The method for manufacturing a hybrid integrated circuit device according to claim 1, wherein a solder paste is used as said conductive brazing material. 3. The method according to claim 2, wherein the solder paste is screen-printed and attached to the desired conductive path.
A manufacturing method of the hybrid integrated circuit device according to the above. 4. An N ² gas is introduced from an exhaust pipe in the melting furnace, N ² gas is sucked out by an adjacent intake pipe, and the N ² gas is circulated on the hybrid integrated circuit board to form the conductive solder. The method for manufacturing a hybrid integrated circuit device according to any one of claims 1 to 3, wherein the material is collectively reflowed.