JP2002132185A - Thin film transistor, its manufacturing method, tft array using the same, liquid crystal display device and el display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a transistor which has high resistivity for BT stress, maintains stable characteristics and has high reliability. SOLUTION: An interface reaction between a gate insulation film and a gate electrode is suppressed and BT resistivity is improved by controlling moisture content in the gate insulation film and the film which constitutes the gate electrode. Thus, a highly reliable TFT array is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor array used for a liquid crystal display and a wiring material used for the same.

[0002]

2. Description of the Related Art At present, a very large number of liquid crystal displays are used for multimedia equipment, portable and communication equipment. In addition, common demands for a liquid crystal display from these electronic devices are a large screen, high definition, and high reliability. Particularly, recently, since a large number of liquid crystal displays have been used in portable devices, a panel with higher reliability has been demanded.

[0003] Many factors are involved in improving reliability. For example, the crystallinity of the semiconductor layer, the film quality of the gate insulating film, the film quality of the gate metal, the interface state between these materials, and the like. Generally, to evaluate reliability, AC tolerance evaluation, BT tolerance evaluation, and the like are performed. Above all, BT immunity guarantees the stability of operation, so it is a very important reliability item to ensure the full performance.

[0004] The problems of the current technology and the importance of BT reliability are described below.

First, FIG. 1 shows a cross-sectional structure of a thin film transistor according to the prior art. A semiconductor layer 12 is formed on a glass substrate 10, and a gate electrode 14 is formed via a gate insulating film 13. A MoW alloy is used as a gate electrode material, and a sputtering method is used as a forming method. The source electrode 18 and the drain electrode 19 are formed by ion-implanting the gate electrode 14 in a self-aligned manner. The gate electrode 14, the source electrode 18, and the drain electrode 19 have a multilayer wiring structure with an interlayer insulating film 17 therebetween.

[0006]

The BT resistance test is performed as a reliability test. The Id-Vg characteristics of nch before and after the test are shown in FIG.
Shown in BT resistance test condition is +3 on gate electrode at temperature 85 ℃
0V is applied for a certain period of time, and changes in Id-Vg characteristics are observed.

As shown in FIG. 5, for example, a transistor having poor BT resistance has a voltage application time of about 600 sec.
V and the threshold voltage Vth shift in the negative direction. (The electrical characteristics 51 before the BT resistance test and the electrical characteristics 52 after the test are shown.) If the characteristics fluctuate in this way, the following problems occur.

In the characteristics before the test, the current flowing through the transistor when Vg = 0 V is sufficiently small (indicated by a point 53), and the circuit is not operating. However, in the characteristic 52 after the test, the current flowing through the transistor when Vg = 0 V is considerably large (indicated by a point 54), and the transistor does not operate at Vg = 0V, but the transistor has a considerable amount. Is flowing. In such a state, the circuit not only malfunctions, but also finally stops operating completely due to heat generation.

As described above, in the BT resistance test, it is important that the Id-Vg characteristics do not change with stress.

This deterioration phenomenon is caused by a reaction occurring at the interface between the gate insulating film and the gate electrode. The W of MoW used for the gate electrode causes an oxidation reaction at the interface to generate an electric charge, which is attracted to the channel portion by the electric field and shifts the threshold voltage in the negative direction.

Therefore, in order to solve this problem, it is important to prevent an oxidation reaction at the interface between the two.

[0012]

A semiconductor thin film comprising an insulating base film, a channel region, and a source / drain region, a gate insulating film, a gate electrode, and a source / drain electrode are provided on an insulating substrate. In the thin film transistor using the alloy, the moisture in the gate insulating film and the MoW film as the gate electrode is controlled to 50 ppm or less.

In the manufacture of a thin film transistor having an insulating base film, a channel region, and a source / drain region on an insulating substrate, a gate insulating film, a gate electrode, and a source / drain electrode, the base layer is formed on the insulating substrate. Forming a gate insulating film layer on the semiconductor layer, heat-treating the gate insulating film at a temperature not lower than the temperature applied in the next step, and MoW on the gate insulating film.
A thin film transistor is manufactured by a process of forming a gate electrode made of an alloy.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a thin film transistor according to the present invention will be described below.

FIG. 1 is a sectional view showing the structure of a thin film transistor according to the present invention.

A base film 11 is formed on an insulating substrate 10, a semiconductor layer 12 is formed thereon, and a gate insulating film 1 is formed.
The gate electrode 14 is formed via the gate electrode 3. The source electrode 18 and the drain electrode 19 are formed by ion-implanting the gate electrode 14 in a self-aligned manner. The gate electrode 14, the source electrode 18, and the drain electrode 19 have a multilayer wiring structure with an interlayer insulating film 17 therebetween.

In this structure, the thickness of the semiconductor layer 12 is 30
The gate insulating film 13 uses a silicon oxide film and has a thickness of about 600 to 1500 °. Further, a MoW alloy is used for the gate electrode 14, and its thickness is 1500 to 300.
0Å. At this time, a film in which moisture contained in the gate insulating film 13 and the gate electrode 14 was suppressed to 50 ppm or less was used. The following method was used to suppress moisture in the film.
The gate insulating film 13 is formed by a plasma CVD method, but this time a TEOS film is used. After the gate insulating film 13 was formed, heat treatment was performed at a temperature equal to or higher than the temperature applied in the next step to remove moisture in the film. In this embodiment, at 600 ° C. for 1 hour,
The heat treatment was performed in a nitrogen atmosphere. At this time, it is important that the heat treatment is performed at a temperature higher than the temperature applied in the next step. The temperature higher than the temperature at which the interface between the gate insulating film 13 and the gate electrode 14 is formed is applied in the next step, and moisture in the film escapes. This is to prevent changing the interface between the two. By the heat treatment described above, the moisture contained in the film by several percent can be reduced to 50 ppm or less. The MoW film of the gate electrode 14 was formed by a sputtering method. At this time, it is important to form the film while suppressing the influence of the adsorbed moisture. During the film formation, the film is formed while heating at 150 ° C. or more, and the impurity gas and water in the target are sufficiently controlled. It is important to keep.

Next, the manufacturing method will be described with reference to FIG.

First, a base film 11 and a semiconductor layer 12 are formed on an insulating substrate 10 as shown in FIG. As the semiconductor layer 12, for example, polysilicon formed by forming amorphous silicon and then crystallizing by excimer laser annealing (ELA) is used. The thickness was about 300 to 800 mm. A silicon oxide film is used for the base film 11 and its thickness is 4000 to 80.
00 °. Thereafter, as shown in FIG. 2B, patterning is performed only on a portion where the semiconductor layer 12 is to be left by the photoresist 31. Semiconductor layer 1 by dry etching
The unnecessary portion 2 is removed by etching. Thereafter, a gate insulating film 13 is formed as shown in FIG. This time, the gate insulating film 13 was formed of a TEOS film by a plasma CVD method. Thereafter, the gate insulating film 13 is heat-treated in a heat treatment furnace. This time, the treatment was performed at 600 ° C. for 1 hour in a nitrogen atmosphere.
By this processing, moisture contained in the gate insulating film 13 is reduced.
It can be reduced to 50 ppm or less. Then (d)
A gate electrode 14 is formed as shown in FIG. At this time, the gate electrode 14 was formed by sputtering using a MoW alloy as a target. The heat treatment may be performed in a separate chamber before forming the MoW alloy in a sputtering apparatus for forming the gate electrode 14. After the heat treatment, it is preferable to form the gate electrode continuously in a vacuum, because the influence of moisture adsorbed on the surface of the gate insulating film can be removed.

Thereafter, a source region 15 and a drain region 16 are formed by ion shower doping as shown in (e), and a source electrode 18 and a drain electrode 19 are formed via an interlayer insulating film 17 as shown in (f). And formed a transistor structure.

Next, an embodiment in which an array using thin film transistors manufactured by the above-described structure and manufacturing method is applied to a TFT drive type liquid crystal display device will be described with reference to FIG.
A thin film transistor array 52 in which the above-described thin film transistor 51 is formed on the entire surface of a glass substrate is formed. A liquid crystal 55 is sandwiched between the transistor array 52 and the opposing substrate 54 on which the opposing electrode 53 is formed to complete a liquid crystal display.

Next, an array using the thin film transistors manufactured by the above-described structure and manufacturing method is used as a TFT drive type EL.
An embodiment applied to a display device will be described with reference to FIG.
A thin film transistor array 61 in which the above-described thin film transistor 51 is formed on the entire surface of a glass substrate is manufactured. An extraction electrode 63 is provided on the drain electrode 62 side of each transistor 51.
Is formed, and a light emitting body 64 is formed thereon to complete an EL display device.

[0023]

As described above, according to the present invention, a transistor having high resistance to BT stress, maintaining stable characteristics, and having high reliability can be realized. As a result, high image quality and highly reliable TF
It becomes possible to realize a T array.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a method for manufacturing a thin film transistor according to an embodiment of the present invention.

FIG. 3 is a diagram of a liquid crystal display device using the thin film transistor of the present invention.

FIG. 4 is a diagram of an EL display device using the thin film transistor of the present invention.

FIG. 5 is a diagram showing Id-Vg characteristics of nch before and after a BT resistance test in a conventional example.

[Explanation of symbols]

 Reference Signs List 11 base film 12 semiconductor layer 13 gate insulating film 14 gate electrode 15 source region 16 drain region 17 interlayer insulating film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05B33 / 26 H01L 29/78 617M 617V 627F F term (Reference) 2H092 JA25 JA29 JA38 JA42 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB52 JB57 KA05 KA07 KA12 KA16 KA18 MA05 MA07 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA28 MA35 MA37 MA41 NA22 NA24 NA25 NA30 3K007 AB13 BA06 CA01 CA03 EB00 FA01 5C094 AA05 AA14 AA31 BA03 BA27 EA04 CB11 DD02 DD13 EE06 EE44 EE50 FF02 FF07 FF30 FF36 GG02 GG13 GG25 HJ12 NN02 NN71 NN72 PP03 QQ11

Claims (10)

[Claims] A semiconductor thin film comprising an insulating base film, a channel region, and a source / drain region, a gate insulating film, a gate electrode, and a source / drain electrode on an insulating substrate;
A thin film transistor using a MoW alloy for the gate electrode, wherein moisture in the gate insulating film and the MoW film as the gate electrode is 50 ppm or less. 2. The thin film transistor according to claim 1, wherein the gate insulating film is a TEOS film. 3. A method for manufacturing a thin film transistor having a semiconductor thin film including an insulating base film, a channel region, and a source / drain region, a gate insulating film, a gate electrode, and a source / drain electrode on an insulating substrate. Forming a base layer and a semiconductor layer on a substrate, forming a gate insulating film layer on the semiconductor layer, heat treating the gate insulating film at a temperature equal to or higher than a temperature applied in a subsequent step, Forming a gate electrode made of a MoW alloy on a thin film transistor having a gate region, a source region, and a drain region. 4. A heat treatment of the gate insulating film is performed before forming the MoW in an apparatus for forming a MoW as a gate electrode,
4. The method for manufacturing a thin film transistor according to claim 3, further comprising a gate region, a source region, and a drain region, wherein MoW is continuously formed in a vacuum. 5. A thin film transistor array comprising the thin film transistors according to claim 1 arranged in a matrix. 6. A method of manufacturing a thin film transistor array according to claim 3, wherein said thin film transistors are arranged in a matrix. 7. A liquid crystal, wherein a liquid crystal is sandwiched between a first substrate having a thin film transistor array in which the thin film transistors according to claim 1 or 2 are arranged in a matrix and a second substrate having electrodes arranged opposite thereto. Display device. 8. A method according to claim 3, wherein a liquid crystal is sandwiched between a first substrate having a thin film transistor array arranged in a matrix and a second substrate having electrodes arranged opposite thereto. Of manufacturing a liquid crystal display device. 9. An electroluminescent material is sandwiched between a first substrate having a thin film transistor array in which the thin film transistors according to claim 1 or 2 are arranged in a matrix and a second substrate having electrodes arranged opposite thereto. Electroluminescent display device. 10. A method of manufacturing a thin film transistor according to claim 3, wherein an electroluminescent material is sandwiched between a first substrate having a thin film transistor array arranged in a matrix and a second substrate having electrodes arranged opposite thereto. A method for manufacturing an electroluminescent display device, comprising: