JP2002124856A - Duty correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for correcting the duty of a signal precisely in an environment using an LSI chip. SOLUTION: A delay circuit 102 delays the output S101 of a frequency divider circuit 101 sequentially through delay gates connected in series. A counter 107 compares the output of each delay gate with a signal S101 and outputs the number of stages of delay gate having 50% phase lag. A selector 108 delivers the output of delay gates at stages corresponding to 1/4, 1/2 and 3/4 of the detected number of stages. From the outputs of the selectors 103 and 108, a signal S109 having a frequency four times as high as that of the signal S101 is generated and the frequency of that signal is divided by two to produce a signal SOUT subjected to duty correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty correction circuit that can be built in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a conventional duty correction circuit, as described in, for example, Japanese Patent Application Laid-Open No. 4-364603, duty correction is performed using a selector and an exclusive logic (EXOR) gate.

[0003]

SUMMARY OF THE INVENTION However, LSI
With the progress of miniaturization, the balance between the delay amount included in the gate and the delay amount occupying the wiring has become unstable, and it has become difficult to set the delay amount of the gate that satisfies all the variations. I have. Considering the process variation, temperature, power supply voltage fluctuation, etc. in LSI,
If the difference between the delay time of the rise and the fall of the gate is different from the estimate at the time of design, there is a problem that an accurate duty cannot be obtained.

[0004] In view of the above problems, an object of the present invention is to provide a duty correction circuit capable of accurately correcting the duty of a signal even in an environment using an LSI chip.

[0005]

Means for Solving the Problems In order to solve the above-mentioned problem, a solution taken by the invention of claim 1 is substantially the same as a first frequency dividing circuit for dividing an input signal by two. A delay circuit in which k (k is a positive integer) delay gates having delays are connected in series, the output of the first frequency divider circuit being sequentially delayed by each delay gate, and each delay circuit of the delay circuit A detection circuit for detecting the number of stages of a delay gate that outputs a signal whose phase is delayed by 50% from the output of the first frequency divider by comparing the output of the gate with the output of the frequency divider; Selectors respectively outputting the outputs of the delay gates corresponding to 数, お よ び and ／ of the number of stages of the delay gate detected by the above, each output of the selector, and the first frequency dividing circuit From the output of
A waveform shaping circuit for generating a signal having a frequency four times as high as the output of the first frequency dividing circuit from the output of the delay gate delayed by%, and dividing the output of the waveform shaping circuit by 2 to perform duty correction And a second frequency dividing circuit that outputs the divided signal.

According to the first aspect of the present invention, each output of the selector has a phase of 12.1 from the output of the first frequency dividing circuit.
The signal is delayed by 5, 25, 37.5%. From these signals and the signal whose phase is delayed by 50%, a signal having a frequency four times that of the first frequency dividing circuit is generated by the waveform shaping circuit. Then, a signal whose duty has been corrected is generated by dividing the frequency of the signal by two, so that an accurate duty can be corrected.

According to the invention of claim 2, the delay amount of each delay gate in the duty correction circuit of claim 1 is set to a value corresponding to 1 / 4i (i is a natural number) of the cycle of the input signal. It is assumed that

[0008] According to the third aspect of the present invention, the first aspect is provided.
Is provided with a delay amount control circuit that controls a power supply voltage supplied to each delay gate of the delay circuit and stabilizes the delay amount of each delay gate.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a configuration of a duty correction circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a first frequency dividing circuit including a D flip-flop (hereinafter, referred to as “D-FF”);
Is a delay circuit composed of a plurality of delay gates connected in series, 103 and 108 are first and second selectors each having an output of each delay gate constituting the delay circuit 102 as an input,
104 is an AND circuit, 105 is an inverter, 106 is D
-FF 107 is an output S101 of the first frequency dividing circuit 101
, A waveform shaping circuit (oscillation circuit) that receives the output signals S106, S107, and S108 from the second selector 108 and the output signal S102 from the first selector 103 as inputs, and 110 a D-FF. The second
Is a frequency dividing circuit. The detection circuit 10 is configured by the first selector 103, the AND circuit 104, the inverter 105, the D-FF 106, and the counter 107.

The first frequency divider 101 divides the input signal SIN by two. The output S101 of the first frequency divider 101 is sequentially delayed by each delay gate forming the delay circuit 102, and the output of each delay gate is input to the first and second selectors 103 and 108. The AND circuit 104 has the first
S102 of the selector 103 and the first frequency divider 10
1 and an output S101, and an output signal S103 representing a logical product thereof is supplied to the D input of the D-FF. D-
The FF 106 receives the inverted signal of the output S101 of the first frequency dividing circuit 101 as a clock input. Thereby, the D-FF1
06, the phase shift of the outputs S101 and S102 is 50
%, The value "1" is latched and the phase shift is 50%.
When it is not less than%, "0" is latched. D-FF106
Is an enable input EN of the counter 107.
Is input to

The counter 107 counts the output S101 of the first frequency divider 101 when the enable EN is "1", and holds the count when it is "0". Counter 1
07 is output to the first and second selectors 10
3, 108 as a control signal. In response to the control signal S105, the second selector 108 generates a signal S108 having a delay amount of 1/4 of the output signal S102 of the first selector 103 and a signal S107 having a delay amount of 1/2.
And a signal S106 having a delay amount of ／.

The waveform shaping circuit 109 includes a second selector 10
8 and the first and second output signals S106, S107 and S108.
The output signal S102 from the selector 103 is input, and a clock having a frequency four times the frequency of the input signal SIN is generated. The output signal S109 of the waveform shaping circuit 109 is divided by two by the second frequency dividing circuit 110 and output as the output signal SOUT.

Here, the delay amount of each of the delay gates constituting the delay circuit 102 is a value which, when multiplied by 4i (i is a natural number), corresponds to 50% of the period of the output S101 of the first frequency dividing circuit 101, That is, 1/4 of the cycle of the input signal SIN
It is set to a value corresponding to i.

FIG. 2 is a timing chart showing the operation of the duty correction circuit shown in FIG. Referring to FIG.
The operation of the duty correction circuit shown in FIG. 1 will be described.

The first selector 103 sequentially selects the outputs of the delay gates # 1, # 2,..., #K of the delay circuit 102 in accordance with the output S105 of the counter 107. This first
Selection output S102 of the selector 103 of the AND circuit 1
04, the phase is compared with the output S101 of the first frequency dividing circuit 101.

When the phase shift between the output S101 of the first frequency divider 101 and the selected output S102 of the first selector 103 is 50% or less, the output S10 of the AND circuit 104 is output.
3 becomes “1” and the enable input S of the counter 107
104 is fixed to "1". Thereby, the counter 1
07 counts up the output S101 of the first frequency dividing circuit 102 and causes the first selector 103 to output the output signal of the next stage delay gate as the selected output S102.

On the other hand, when the phase shift becomes 50%, the output S103 of the AND circuit 104 becomes "0",
Since the enable input S104 becomes "0", the counter 107 stops its operation. At this time, the counter 107
Is assumed to be n (positive integer). However, the value of n is a multiple of 4 from the setting of the delay amount of each delay gate configuring the delay circuit 102 as described above.

The second selector 108 outputs the output signals of the n / 4-stage delay gate, the n / 2-stage delay gate and the 3n / 4-stage delay gate according to the output S105 of the counter 107, that is, the value n. The signals S106, S107,
Output as S108. Each signal S106, S107,
S108 is the output signal S101 of the first frequency dividing circuit 101
Are delayed by 12.5%, 25%, and 37.5%.

The waveform shaping circuit 109 includes a second selector 1
08, the selected output S102 of the first selector 103 when the phase shift becomes 50%, and the output signal S101 of the first frequency dividing circuit 101, the output signal S101 A signal S109 having a frequency four times as high is output. This output signal S109 is
By dividing the frequency by 2 by the frequency dividing circuit 110, a signal SOUT having the same cycle as the input signal having the duty of 50% can be output.

Here, when the EXOR circuit is used for duty correction as in the conventional configuration, the EXOR circuit
Due to the fact that the circuit generally has the characteristic that the rise time and the fall time are significantly different, there has been a possibility that the accuracy of the duty correction may not be sufficiently obtained. On the other hand, in the present embodiment, the original clock signal is divided by four without using the EXOR circuit, and the clock signal divided by four is processed by the circuit using the D-FF. High duty correction can be realized.

In the configuration shown in FIG. 1, a detection pulse input is provided, and by inputting the detection pulse,
The counter 107 can be reset, the number of delay stages can be calculated again, and the duty correction can be executed.

For example, by providing a voltage fluctuation detection circuit separately and inputting a voltage fluctuation detection signal as a detection pulse, it becomes possible to perform duty correction again when the power supply voltage fluctuates. Alternatively, by separately providing a temperature fluctuation detection circuit and inputting a temperature fluctuation detection signal as a detection pulse, duty correction can be performed again when a temperature fluctuation occurs. Alternatively, it is also possible to provide a separate duty variation detection circuit, detect the duty-corrected data again, and execute the duty correction again when the duty correction is not sufficient.

The delay amount of each delay gate constituting the delay circuit 102 of FIG. 1 is not always stable, but varies due to process variations and changes in power supply voltage and temperature. Therefore, in order to further improve the accuracy of the duty correction, a circuit that stabilizes the delay amount of each delay gate is required.

FIG. 3 is a diagram showing a configuration of a circuit for controlling the delay amount of the delay gate in the duty correction circuit of FIG. In FIG. 3, reference numeral 102 denotes a delay circuit including a plurality of delay gates shown in FIG. 1, and the amount of delay is variably configured by a supplied power supply voltage S511. 502 is a NAND circuit, 503 and 504
Is an AND circuit, 505 is a counter, 506 is a clock generation circuit, 507 is a D-FF, 508 is a digital / analog conversion circuit (hereinafter abbreviated as "DAC"), and 509 is a D-
The output S507 (n bits) of the FF507 is supplied to the delay circuit 10
Power supply voltage control data S5 for controlling the delay amount
This is a conversion circuit for converting into 10. The components other than the delay circuit 102 constitute the delay amount control circuit 50.

FIG. 4 is a timing chart showing the operation of the circuit shown in FIG. The operation of the circuit of FIG. 3 will be described with reference to FIG.

The signal S101 is sequentially delayed by each delay gate of the delay circuit 102. Output SI of each delay gate
, SIk (k is the number of delay gates constituting the delay circuit 102) is input to the clock generation circuit 506. The clock generation circuit 506 generates a rising signal (506 in FIG. 9) from the outputs SI1, SI2,... SIk of the respective delay gates using two signals, and generates a clock signal S506 from the combination of the rising signals. Generate. This clock signal S506 is input to the counter 505.

The signal S101 and the inverted signal of the output SI1 of the first-stage delay gate are input to the NAND circuit 502. The output S502 of the NAND circuit 502 and the reference signal S500 are input to an AND circuit 504,
The output of the circuit 504 is provided to the counter 505 as a reset signal. The output S505 (n bits) of the counter 505 is input to the D-FF 507.

Here, the reference signal S500 is normally fixed at "H", and when the environment changes such as when the power supply voltage or temperature fluctuates or when the power is turned on, the reference signal S500 is set as shown in FIG. 3
"L" for a predetermined period necessary to reset the circuit
Is a pulse signal. When the reference signal S500 becomes “L”, the delay amount of each delay gate is controlled again.

The inverted signal of the signal S101 and the first signal
The output SI1 of the stage delay gate is input to the AND circuit 503, and the output S503 of the AND circuit 503 is the D-FF50.
7 as a clock. The output (n bits) S507 from the D-FF 507 is converted by the conversion circuit 509 into power supply voltage control data S510 for controlling the delay amount of the delay circuit 102, and the conversion circuit 509
The analog voltage S508 corresponding to the output S510 of the
508.

The delay amount of the delay circuit 102 is controlled by supplying the analog voltage S508 as the power supply voltage S511 of the delay circuit 102. Note that the power supply voltage S509 supplied to the DAC 508 is supplied separately from the power supply voltage S511 supplied to the delay circuit 102.

Now, the delay amount per delay gate is a
When the time of a half cycle of the signal S101 is represented by b, the delay gate is set to m (= b /
a) are required.

Since the period of the signal S506 inputted as a clock to the counter 505 is 2a, the signal S101
Of the counter at the point where is delayed by a half cycle becomes m / 2. However, when the delay amount of the delay gate fluctuates due to process variations or fluctuations in the power supply voltage, the output value S505 of the counter 505 is m / 2.
Not necessarily.

Therefore, the signal S after a half cycle of the signal S101
503, the output S505 of the counter 505 is
Latched by the FF 507, the value S5 of the D-FF 507
07 is smaller than the reference value m / 2, the delay gate 1
Since it is determined that the delay amount per stage is large, the conversion circuit 5
09 outputs to the DAC 508 digital data S510 that increases the power supply voltage S511 of the delay gate. As a result, the delay amount of each delay gate of the delay circuit 102 decreases.

On the other hand, the value of the D-FF 507 is equal to the reference value m / 2.
If it is larger than the threshold value, it is determined that the delay amount per one stage of the delay gate is small.
0 is output to the DAC 508. Thereby, the delay circuit 1
02, the delay amount of each delay gate increases.

With the above operation, the delay amount of each delay gate of the delay circuit 102 can be kept constant regardless of process variations, temperature and voltage variations.

It is to be noted that a voltage fluctuation detecting circuit is separately provided,
By inputting the voltage change detection signal as the reference signal S500, it is possible to adjust the delay amount of the delay circuit again when the power supply voltage changes. Similarly, by separately providing a temperature fluctuation detection circuit and inputting a temperature fluctuation detection signal as a reference signal S500,
When the use temperature changes, the delay amount of the delay circuit can be adjusted again.

[0038]

As described above, according to the present invention, it is possible to accurately correct the signal duty even if the power supply voltage or temperature fluctuates or the production varies after the LSI is formed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a duty correction circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the duty correction circuit shown in FIG.

FIG. 3 is a diagram illustrating a configuration of a circuit that controls a delay amount of each delay gate in the duty correction circuit illustrated in FIG. 1;

FIG. 4 is a flowchart showing the operation of the circuit shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 detection circuit 50 delay amount control circuit 101 first frequency dividing circuit 102 delay circuit 108 selector 109 waveform shaping circuit 110 second frequency dividing circuit

Claims (3)

[Claims] 1. A first frequency dividing circuit for dividing an input signal by two, and k (k is a positive integer) delay gates having substantially the same delay are connected in series. A delay circuit for sequentially delaying the output of the first frequency divider circuit with each delay gate, and comparing the output of each delay gate of the delay circuit with the output of the frequency divider circuit to obtain an output of the first frequency divider circuit. A detection circuit for detecting the number of stages of the delay gate that outputs a signal whose phase is delayed by 50% from the detection circuit;
A selector for outputting the outputs of the delay gates corresponding to 4, 1/2 and 3/4 respectively; a delay gate whose phase is delayed by 50% from the outputs of the selector and the output of the first frequency divider; And a waveform shaping circuit for generating a signal having a frequency four times that of the output of the first frequency dividing circuit from the output of the first frequency dividing circuit; dividing the output of the waveform shaping circuit by 2 and outputting as a duty-corrected signal And a second frequency dividing circuit for performing the duty correction. 2. The duty correction circuit according to claim 1, wherein the delay amount of each of the delay gates is one of a period of the input signal.
/ 4i (i is a natural number). 3. The duty correction circuit according to claim 1, further comprising a delay amount control circuit that controls a power supply voltage supplied to each delay gate of the delay circuit and stabilizes a delay amount of each delay gate. Characteristic duty correction circuit.