JP2002117674A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which an interval from a write-in command to a read-out command can be shortened and an effective data transfer rate can be enhanced. SOLUTION: This device is provided with plural address counters and plural timing generating circuits, provided corresponding to each of plural memory banks, a data bus for read-out and a data bus for write-in provided commonly for plural memory banks, a data output buffer connected to the data bus for read-out, and a data input buffer connected to the data bus for write-in.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a method for improving the data transfer efficiency of a synchronous semiconductor memory.

[0002]

2. Description of the Related Art As a storage element used in various electronic devices, a synchronous DRAM (synchronous DRA) is used instead of a conventional asynchronous dynamic random access memory (DRAM).
M, hereafter abbreviated as SDRAM) is about to become mainstream. SDRAM
Is characterized in that data reading / writing is performed in synchronization with a clock, and the data transfer rate can be higher than that of an asynchronous DRAM. For example, the clock frequency is 100MHZ
If z and the number of data input / output terminals is 16, the data transfer rate will be 200 MB / s. Recently, in order to further increase the data transfer rate, double data rate synchronous DRAM
(Hereinafter abbreviated as DDR-SDRAM) has appeared. In DDR-SDRAM, data read / write is performed in synchronization with each of the rising and falling edges of the clock.
It is twice as large as RAM. For example, under the same conditions as above, 400MB /
s.

[0003]

However, the conventional SDRAM
And DDR-SDRAM have a problem that when reading and writing are mixed, the data transfer rate cannot be sufficiently increased. This will be described with reference to the drawings.

FIG. 18 is a timing chart in the case where reading is performed after writing in the DDR-SDRAM.
The burst length (the number of times data is continuously written or read) is BL = 4, the read latency (the number of cycles from the read command until the first data is output) is CLR = 2, and the write latency (the first data from the write command is (The number of cycles until input) is when CLW = 1. CLK
And / CLK are differential clocks, and DQ is a data input / output terminal. At time t0, a write command (Write) is input, and data is input four times from time t1 (D0 to D3). Times of Day
At t4, a read command (Read) is input, and data is output four times from time t6 (Q0 to Q3). The problem here is that to write all four data D0 to D3, the interval tWRD from the write command to the read command
Is to take enough. because,
This is because if a read command is input during writing, the writing operation is interrupted. Conventional DDR-SDRAM
In general, tWRD must take (BL / 2 + 2) cycles. For example, if BL = 4, tWRD
= 4 cycles. For this reason, when writing and reading coexist, there is a problem that the command input interval cannot be reduced and the effective data transfer rate does not increase.

[0005]

In order to solve the above-mentioned problems, in a semiconductor device according to the present invention, a plurality of memory banks operable independently of each other and a plurality of memory banks provided corresponding to each of the plurality of memory banks are provided. A plurality of address counters and a plurality of timing generating circuits; a read data bus and a write data bus commonly provided in the plurality of memory banks; a data output buffer connected to the read data bus; A data input buffer connected to the data bus. Thus, while one memory bank is performing a read operation, another memory bank can perform a write operation.

[0006]

FIG. 1 shows the configuration of a DDR-SDRAM according to the present invention. In the figure, CLKIN clock input circuit, ICG is an internal clock generation circuit, and from the differential clock CLK, / CLK (“/” before the signal name indicates a negative logic signal) Generates internal clocks CCLK, / CCLK and / BCLK. CB is a command input circuit, CL is a command latch circuit, CD is a command decoder, and SM is a state machine. The externally input signals / RAS, / CAS, / WE, / CS and the bank address signals BA0, BA1 are latched by CL, decoded by CD, and used to set the internal state by SM. M0 to M3 are memory banks. Although not shown in the figure, each memory bank has a memory array in which memory cells are arranged at intersections of word lines and bit lines, and a row decoder and a column decoder for selecting a desired memory cell. . AB is an address input circuit, which receives an external address signal Ai (i = 0 to n, n is 12, for example). AC
0 to AC3 are column address counters, PD0 to PD3 are column predecoders, TG0 to TG3 are timing generation circuits, CCG0 to CC
G3 is a clock generation circuit for controlling the operation of the column address counter. These circuits are provided corresponding to each memory bank. The column predecoder supplies an address signal to a column decoder in the memory bank, and the timing generation circuit controls a read / write operation of the memory bank. A row predecoder for supplying an address signal to a row decoder in a memory bank is omitted. RDB is a read data bus, and WDB is a write data bus. These buses are provided commonly to the memory banks. PS is a parallel / serial converter, SP is a serial / parallel converter, DIN is a data input buffer, and DOUT is a data output buffer. At the time of reading, the data read from the memory bank
The signal is parallel / serial converted by the PS through B and output from DOUT to the data input / output terminal DQ. At the time of writing, the data input from DQ is serial / parallel converted by the SP via DIN and written to the memory bank through WDB. P
S and SP are provided because data input / output is 2 per cycle.
This is because the operation of the internal circuit of the memory is performed once per cycle, while the operation is performed once (when the CLK rises and falls).
Although only one PS, SP, DIN, DOUT, and DQ are shown in the figure, there may be a plurality (for example, 4 to 16) in practice.

A first feature of the present invention is that an address counter and a timing generation circuit are individually provided for each memory bank. The second feature is that RDB and WDB are provided separately. Thus, as will be described in detail later, when one memory bank (for example, M0) is performing a read operation, another memory bank (for example, M0)
M1) can perform a write operation. That is,
Since the address counters are individually provided, AC0 may generate the read address of the memory bank M0, and AC1 may generate the write address of the memory bank M1. Further, since the read data bus and the write data bus are separate, data does not conflict on the bus.

Next, main circuits constituting the DDR-SDRAM of FIG. 1 will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram of the clock input circuit CLKB and the internal clock generation circuit ICG. Clock input circuit C
LKB is composed of P-channel MOS transistors MP1 and MP2 and N-channel
A differential amplifier composed of MOS transistors MN1, MN2 and MN3;
It consists of an inverter IV1. This differential amplifier is activated when the enable signal EN is at a high potential ("H"). When EN is low potential ("L"), MN3 is turned off,
The current of the differential amplifier is cut off. The potential difference between the external clock signals CLK and / CLK is amplified by the differential amplifier and IV1, and output as the signal CLKIN. In addition, P channel MO
The S transistor MP3 fixes the input terminal of the IV1 to “H” when the signal EN is “L” to prevent a through current from flowing through the IV1.

The internal clock generation circuit ICG is composed of two one-shot circuits OS. One is from CLKIN to internal clock C
CLK and / CCLK are generated, and the other generates / BCLK from CLKIN. Since the latter has almost the same circuit configuration as the former, the description of the circuit configuration is omitted in the figure. As described below, CCLK is a command latch, / CCLK is a command decoder, and / BCLK
Is used in the state machine and the counter clock generation circuit. Next, the operation of the one-shot circuit will be described.

In the initial state, the node N1 is "H" and the output C
CLK is "L" and / CCLK is "H". The potential of the node N1 is held by a latch including two inverters IV4 and IV6 (IV6 is an inverter having a small current driving capability). Since the output of the inverter IV8 is "L", the output of the NAND gate NA2 is "H", the output of NA1 is "L", and the output of the inverter IV9, that is, the node N2 is "H". Where input CLKIN
Transitions from "L" to "H", the two N-channel MOS transistors MN4 and MN5 are both turned on, and the node N1
Becomes “L”. As a result, CCLK becomes "H" and / CCLK becomes "H".
On the other hand, the output of the inverter IV4 becomes "H" and the output of the inverter IV5 becomes "L", and after the delay time of the delay circuit DLY1 has elapsed, the output of DLY1 becomes "L". NAND gate NA1
Becomes "H", the output of inverter IV9, that is, node N2
Becomes "L". P-channel MOS transistor MP4 turns on,
Since the N-channel MOS transistor MN5 is turned off, the node N1 returns to “H”, CCLK returns to “L”, and / CCLK returns to “H”. As can be seen from the above description, the delay circuit is used during the period when CCLK is "H" (the period when / CCLK is "L").
It is determined by the delay time of DLY1, and does not depend on the period during which the input CLKIN is "H". Therefore, regardless of the duty of the external clock signal, the command latch,
An internal clock signal having a width suitable for operation of a circuit such as a command decoder can be generated. Note that / PUP is a reset signal, for example, a signal that becomes "L" when the power is turned on. When this is "L", the latch consisting of NA1 and NA2 is reset (the initial state described above).

FIG. 3 is a circuit diagram of the command input circuit CB and the command latch CL. Command signal / RAS, / CAS, / W
An input circuit and a latch are provided for each of E, / CS, and bank address signals BA0 and BA1. Since CB is the same circuit as the above-mentioned clock input buffer, the description of the circuit configuration is omitted. The difference is that a single-ended signal and a reference voltage VREF are input instead of the differential input signal. The CL latches an input signal using the above-described internal clock signal CCLK. When CCLK is "L", the output of the clock inverter CIV1 is low impedance and the output of CIV2 is high impedance, so that the input signal is output as it is. When CCLK is "H", the output of CIV1 becomes high impedance and the output of CIV2 becomes low impedance, so that the input signal is ignored and the state is maintained. In addition,
The clock inverter can be realized by the circuit shown in FIG.

FIGS. 4 to 6 are circuit diagrams of the command decoder. In DDR-SDRAM, a method of designating a command by a combination of signals such as / RAS, / CAS, / WE, and / CS is standardized, and the present embodiment also follows the standardized method. Commands include a bank active command and a refresh command, but here, only commands related to reading and writing related to the present invention are shown.

FIG. 4 shows a read command decoder.
Four command decoders CDR1 corresponding to the memory banks M0 to M3 and one command decoder CDR2 common to the memory banks
Are provided. NAND gates NA20, NA21 and NO in CDR1
The command signal and the bank address are ANDed by the R gate NO20 and latched and output by the latch composed of the clock inverters CIV20 and CIV21 and the inverter IV22.
It becomes RDY [0]. The internal clock signal / CCLK is used for the latch. In addition, AND gate with inverted signal of / CCLK by AND gate
Is taken and the output becomes RD [0]. When a read command is input to memory bank M0, CST, RASB, CAST, WE
Since B, BA0B, and BA1B all become "H", RDY [0] is set to / CCLK
Becomes "H" at the falling edge of, and is held for one cycle. RD [0] goes "H" at the falling edge of / CCLK and goes "L" at the rising edge of / CCLK. That is, it becomes “H” only during the period when / CCLK is “L”. CDR2 has almost the same configuration as CDR1, except that no bank address is input and the output is shifted for two cycles by shift register SR20 (generally CL1 is output).
W + 1 cycle) differently delayed. Output RD2 is 2 when a read command (regardless of memory bank) is input.
It becomes "H" after the cycle.

The shift register SR20 used in FIG.
For example, it can be realized by the circuit of FIG. Here, the input signal RDY is delayed by two cycles by the internal clock signal / BCLK. Here, RST is a reset signal, which is used, for example, to clear the contents of the shift register when the power is turned on.

FIG. 5 shows a decoder CDW for a write command and a decoder CDS for a burst stop command. CDW
Then, as in CDR2, the output is shifted by shift register SR30 to 2
It is delayed by one cycle (generally CLW + 1 cycle).
When a write command is input to the memory bank M0, outputs WT2 [0] and WT2Y [0] are output after two cycles. WT2Y
[0] goes "H" for one cycle, and WT2 [0] goes "H" only while / CCLK is "L". When the burst stop command is input, the signal BST becomes “H” only while the / CCLK is “L”.

The shift register SR30 used in FIG.
For example, it can be realized by the circuit of FIG. Here, the input signal WTY [0] is delayed by two cycles by the internal clock signal / BCLK. Here, RST is a reset signal, which is used, for example, to clear the contents of the shift register when the power is turned on. The contents of the shift register are also cleared by RD [0] and PRE [0]. The reason for this will be described later. The clock NAND gate used here can be realized by the circuit in FIG.

FIG. 6 shows a decoder CD for a precharge command.
Indicates P. When the all bank precharge command is input (at this time, the signal A10T is "H"), the output signal PRE
[0] to PRE [3] all become "H". When a precharge command for a specific memory bank is input, only one of PRE [0] to PRE [3] becomes "H" depending on the bank address. In any case, only when / CCLK is "L"
H ".

FIG. 8 shows a circuit diagram of the state machine SM.
Some state machines indicate the active state and the inactive state of the bank. However, here, only the state machines related to reading and writing related to the present invention will be described.
One set of read / write-related state machines is provided for each memory bank, that is, four sets in total. However, for simplicity, only a circuit for the memory bank M0 is shown in the figure. The output signal BRD [0] is output while the memory bank M0 is performing burst read.
HWT, and BWT [0] is a signal which becomes "H" during burst writing of the memory bank M0.

The state of BRD [0] is determined by two NAND gates NA52 and NA52.
It is held by a latch consisting of 54. When RD [0] becomes "H", that is, when a read command for the memory bank M0 is input, the latch is set. The latch is reset in any of the following cases (1) to (4).

(1) When a read command for another memory bank is input. At this time, any one of RD [1] to RD [3] becomes "H".

(2) When a burst stop command is input. At this time, BSTOP becomes "H".

(3) When a precharge command for all banks or bank M0 is input. In this case PR
E [0] becomes "H".

(4) When burst reading is completed. BEND [0] becomes “H” in the last cycle of the burst read, and the output of the NAND gate NA50 becomes “L” in the next cycle (only during the period when / BCLK is “L”).

The state of BWT [0] is determined by two NAND gates NA53 and NA53.
It is held by a latch consisting of 55. When WT2 [0] becomes "H", that is, two cycles after a write command to the memory bank M0 is input, the latch is set. The latch is reset in any of the following cases (1) to (5).

(1) Two cycles after a write command for another memory bank is input. At this time WT2
One of [1] to WT2 [3] becomes "H".

(2) Two cycles after a read command (in any memory bank) is input. At this time, RD2
Becomes "H".

(3) When a read command for the memory bank M0 is input. At this time, RD [0] becomes "H".

(4) When a precharge command for all banks or bank M0 is input. In this case PR
E [0] becomes "H".

(5) When burst writing is completed. BEND [0] becomes "H" in the last cycle of the burst write, and the output of the NAND gate NA51 becomes "L" in the next cycle (only during the period when / BCLK is "L").

FIG. 9 shows counter clock generation circuits CCG0 to CCG.
The circuit diagram of G3 is shown. A total of four circuits are provided, one for each memory bank. In the following description, the circuit CCG0 for the memory bank M0 will be described.

Among the output signals, the output signal YCLK1 [0] is a signal for instructing the address counter AC0 to take in an external address, and the YCLK2 [0] is a signal for instructing the address counter AC0 to count up. YCLK1 [0] is input when a read command to memory bank M0 is input (RDY [0] becomes "H" at this time) or two cycles after the write command is input (WTY2 [0] at this time)
Becomes "H"). In either case, / BCLK is "
It becomes "H" only during the period of "L". The output signal YCLK2 [0] is during burst reading of the memory bank M0 (BRD [0] is "H" at this time) or during burst writing (BWT [ 0]
Is "H") and a new read / write command is not input to the memory bank M0. YCLK2 [0] also goes "H" only while / BCLK is "L". The reason why the delay circuit DLY0 is inserted in the input portion of / BCLK is to wait until the signals BRD [0] and BWT [0] are determined.

FIG. 10 is a circuit diagram of the timing generation circuit. Although four timing generation circuits are provided, one for each memory bank, only a circuit TG0 for the memory bank M0 is shown in the figure for simplicity.

The timing generation circuit TG0 generates an output signal YIOR [0] or YIOW [0] when the above-mentioned counter clock signal YCLK1 [0] or YCLK2 [0] becomes "H". YC
The OR of LK1 [0] and YCLK2 [0] is obtained, and the one-shot generating circuit OS70 outputs the one-shot pulse YIOE after the delay time of the delay circuit DLY70. The OS 70 can be realized by a circuit similar to the OS of FIG. 2, for example. During burst reading or writing of memory bank M0 (in this case, BRD [0] or
BWT [0] is "H") is YRWL [0], then YRWLD
[0] is output. As a result, YIOR [0] is output during burst reading, and YIOW [0] is output during burst writing. YIOR [0] or YIOW [0] controls the column decoder in the memory bank M0 and determines the timing of reading data from the bit line to the data bus RDB or writing data from the data bus WDB to the bit line. Used for The reason that BRD [0] is once ANDed by the AND gate A70 after passing through the latch composed of CINV70, CINV72, and IV74 is correct even if YRWL [0] is delayed by one cycle or more than / BCLK. This is to output [0]. BWT [0]
The same applies to.

Next, the operation of this embodiment will be described with reference to the drawings. FIGS. 11 to 14 are operation timing charts when a read command (Read) to the memory bank M0 is input after a write command (Write) to the memory bank M0. FIG. 11 shows one cycle after Write, and FIG.
13 shows the case where Read is input after three cycles, and FIG. 14 shows the case where Read is input after four cycles. In each case, the burst length is BL = 4, the read latency is CLR = 2, and the write latency is CLW = 1. It is assumed that the memory bank M0 has been activated in advance by a bank active command.

First, FIG. 11 will be described. When a write command is input at time t0, WTY [0] becomes "H". This is shifted by the shift register SR30. At time t1, a read command is input and RD [0]
Becomes "H", so that the shift register is cleared as described above (see FIG. 7).
T2Y [0] does not become "H". Therefore, BWT [0] does not become “H”, and writing to memory bank M0 is not executed.
On the other hand, at t1, RD [0] becomes "H", so that BRD [0] becomes "H".
, And the read operation from the memory bank M0 is started. YCLK1 [0] is output, the address “b” input from the address terminal is set in the address counter AC0, and the output AY [0] becomes “b”. As a result, the column address "
Data is read out from the bit lines “b” and “b + 1” to the data bus RDB, and in the next cycle, YCLK2 [0] is output,
AY [0] is counted up to "b + 2", and data is read out from the bit lines of the column addresses "b + 2" and "b + 3" to the data bus RDB. The read data is output to the DQ terminal from time t3 (Q0 to Q3). When AY [0] is counted up to "b + 2", the burst end signal BEND [0] becomes "H", and BRD [0] becomes "L" in the next cycle, and the read operation ends. I do. The read series of data is output to the DQ terminal from t3. The data at the column addresses "b" and "b + 1" are converted from parallel / serial to output data Q0 and Q1, and the data at "b + 2" and "b + 3" are converted from parallel / serial to output data Q2. , Q3.

FIG. 12 is almost the same as FIG. In this case as well, since WTY [0] is cleared while being shifted in the shift register SR30, WT2Y [0] does not become “H”,
No write operation is performed.

In the case of FIG. 13, WT2Y [0] at time t2
Becomes "H", BWT [0] becomes "H", and the write operation is started. YCLK1 [0] is output, and the address "a" input at time t0 is set in the address counter AC0 (although omitted in FIG. 1, a shift register similar to that in FIG. 7 is provided in the address input unit). Therefore, an address signal delayed by two cycles at the time of writing and generally delayed by CLW + 1 cycle is used.) The input data D0 and D1 are serial / parallel converted and passed through the data bus WDB, and the column address
a "and" a + 1 "bit lines, respectively. However, at the next t3, a read command is
Since RD [0] becomes “H”, BWT [0] becomes “L” and the write operation is stopped at this point. On the other hand, since BRD [0] becomes "H", the read operation is started. The following operations are the same as those in FIG.

In the case of FIG. 14, the operation until time t2 is the same as that of FIG.
3, but the read operation is not input at time t3, so that the write operation is continued. That is,
YCLK2 [0] is output and the output AY [0] of the address counter AC0
Is counted up to "a + 2" and the column address is
The input data D2 and D3 are written from the data bus WDB to the bit lines of “a + 2” and “a + 3.” When AY [0] is counted up to “a + 2”, the burst end signal BEND [0 ] Becomes "H", BWT [0] becomes "L" in the next cycle, and the write operation ends, while a read command is input at time t4, so that RD [0] becomes "H". And BRD [0] becomes "H",
The read operation is started. The following operations are the same as those in FIG.

As is clear from the above description, the burst write operation is completed, that is, the burst length BL
= In order to write the data for four times to the memory, the read command is four cycles after the write command (generally, BL / 2
+ CLW + 1 cycles) or later. Therefore, in this case, tWRD = 4, which is the same as the conventional case shown in FIG.

However, this is because the memory banks for writing and reading are the same. In the case of a memory bank in which writing and reading are different, tWRD can be reduced. This will be described below.

FIGS. 15 and 16 are operation timing charts when a read command (Read) for the memory bank M1 is input after a write command (Write) for the memory bank M0. FIG. 15 shows the case where Read is input one cycle after Write, and FIG. In all cases, the burst length is BL = 4 and the read latency is CL
R = 2 and the write latency is for CLW = 1. In addition,
It is assumed that each of the memory banks M0 and M1 has been activated in advance by a bank active command.

First, FIG. 15 will be described. When a write command to the memory bank M0 is input at time t0, WTY [0] becomes "H". This is shift register SR3
Shifted by 0. At time t1, memory bank M1
RD [1] is set to "H" when the read command is input, but different from the case of FIG.
SR30 is not clear. Therefore, at t2 after two cycles, WT2Y [0] becomes "H", BWT [0] becomes "H", and the write operation to the memory bank M0 is started.
YCLK1 [0] is output, the address “a” input at time t0 is set in the address counter AC0, and the output AY
[0] becomes "a". As a result, data D0 and D1 are written from the data bus WDB to the bit lines of the column addresses "a" and "a + 1". However, at the next t3 (two cycles after the read command is input), RD2 becomes "H", so that BWT [0] becomes "L", and the write operation to the memory bank M0 is stopped at this point. You. On the other hand, at t1, BRD
[1] becomes “H”, and the read operation from the memory bank M1 is started. YCLK1 [1] is output, the address “b” input from the address terminal is set in the address counter AC1, and the output AY [1] becomes “b”. As a result, data is read out from the bit lines of the column addresses “b” and “b + 1” to the data bus RDB. In the next cycle, YCLK2 [1] is output, AY [1] is counted up to "b + 2", and data is transmitted from the bit lines of the column addresses "b + 2" and "b + 3" to the data bus RDB. Is read out. When AY [1] is counted up to "b + 2", the burst end signal BEND [1] becomes "H", BRD [1] becomes "L" in the next cycle, and the read operation ends. I do. A series of read data is output to the DQ terminal from t3 (Q0 to Q3).

Next, FIG. 16 will be described. When a write command to the memory bank M0 is input at time t0, WTY [0] becomes "H". This is shift register SR3
Shifted by 0. At time t2, memory bank M1
RD [1] becomes "H" when a read command is input to RD [1]. However, since the banks are different, unlike the case of FIG.
SR30 is not clear. Therefore, at t2 after two cycles, WT2Y [0] becomes "H", BWT [0] becomes "H", and the write operation to the memory bank M0 is started.
YCLK1 [0] is output, the address “a” input at time t0 is set in the address counter AC0, and the output AY
[0] becomes "a". As a result, data D0 and D1 are written from the data bus WDB to the bit lines of the column addresses "a" and "a + 1". In the next cycle, YCLK2 [0] is output,
AY [0] is counted up to “a + 2”, and data D2 and D3 are written from the data bus WDB to the bit lines of the column addresses “a + 2” and “a + 3”. When AY [0] is counted up to "a + 2", the burst end signal BEND [0] becomes "H", BWT [0] becomes "L" in the next cycle, and the write operation ends. I do. On the other hand, at t2, BRD [1] becomes "H", and the read operation from the memory bank M1 is started. YCLK1 [1] is output, the address "b" input from the address terminal is set in the address counter AC1, and the output AY [1] is "
b ", so that the column addresses" b "and" b + 1 "
Is read out to the data bus RDB from the bit line. In the next cycle, YCLK2 [1] is output, AY [1] is counted up to "b + 2", and the column address "b + 2"
And data is read out from the bit line “b + 3” to the data bus RDB. When AY [1] is counted up to "b + 2",
The burst end signal BEND [1] becomes "H", and in the next cycle
BRD [1] becomes "L", and the read operation ends. A series of read data is output to the DQ terminal from t4 (Q0 to Q
3).

As is apparent from the above description, when the memory banks for writing and reading are different, in order to complete the burst write operation, the read command is issued two cycles after the write command (generally BL / 2 + CLW + 1-
Input after CLR cycle) or after.
That is, in this case, tWRD = 2, which is shorter than the conventional case shown in FIG. The reason why tWRD can be shortened is that while one memory bank is performing a read operation, another memory bank can perform a write operation. In the time charts of FIG. 15 and FIG.
There is a period in which both T [0] and BRD [1] are "H".
This indicates that the write operation on the memory bank M0 and the read operation on the memory bank M1 are performed in parallel. Since the counter clock generation circuit and the address counter are provided for each memory bank and the read data bus and the write data bus are separated, no conflict occurs even if such parallel operations are performed.

Although the example in which the present invention is applied to the DDR-SDRAM has been described above, the present invention is applicable not only to the DDR-SDRAM but also to a normal single data rate SDRAM. However, since DDR-SDRAM has a higher original data transfer rate, the effect of applying the present invention is greater.

[0047]

As described above, according to the present invention,
When one memory bank is performing a read operation,
Another memory bank can perform a write operation. Therefore, the interval tWRD from the write command to the read command can be reduced, and the effective data transfer rate can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a DDR-SDRAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a clock input buffer and an internal clock generation circuit in FIG.

FIG. 3 is a circuit diagram of a command input buffer and a command latch in FIG. 1;

FIG. 4 is a circuit diagram of a command decoder in FIG. 1;

FIG. 5 is a circuit diagram of a command decoder in FIG. 1;

FIG. 6 is a circuit diagram of a command decoder in FIG. 1;

FIG. 7 is a circuit diagram of the shift register in FIGS. 5 and 6;

FIG. 8 is a circuit diagram of the state machine in FIG. 1;

FIG. 9 is a circuit diagram of a counter clock generation circuit in FIG. 1;

FIG. 10 is a circuit diagram of a timing generation circuit in FIG. 1;

FIG. 11 is an operation timing chart of the DDR-SDRAM of FIG. 1;

FIG. 12 is an operation timing chart of the DDR-SDRAM of FIG. 1;

FIG. 13 is an operation timing chart of the DDR-SDRAM of FIG. 1;

FIG. 14 is an operation timing chart of the DDR-SDRAM of FIG. 1;

FIG. 15 is an operation timing chart of the DDR-SDRAM of FIG. 1;

FIG. 16 is an operation timing chart of the DDR-SDRAM of FIG. 1;

FIG. 17 is a circuit diagram of a clock inverter and a clock NAND gate.

FIG. 18 is an operation timing chart of a conventional DDR-SDRAM.

[Explanation of symbols]

CLKB: Clock input circuit, ICG: Internal clock generation circuit, CB: Command input circuit, CL: Command latch, CD ...
Command decoder, SM: State machine, AB: Address input circuit, CCG0 to CCG3: Counter clock generation circuit, AC
0 to AC3: column address counter, PD0 to PD3: column predecoder, TG0 to TG3: timing generation circuit, M0 to M3 ...
Memory mat, RDB: Read data bus, WDB: Write data bus, PS: Parallel / serial conversion circuit, SP:
Serial / parallel conversion circuit, DOUT: Data output circuit, DIN: Data input circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akifumi Tsukimori 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. Address Hitachi Device Engineering Co., Ltd. (72) Inventor Yoshinobu Nakagome 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in the Semiconductor Group, Hitachi, Ltd. 5B024 AA15 BA21 BA23 BA29 CA11 CA16

Claims (4)

[Claims] A plurality of memory banks operable independently of each other; a plurality of address counters and a plurality of timing generation circuits provided corresponding to each of the plurality of memory banks; and a common memory for the plurality of memory banks. And a data output buffer connected to the read data bus, and a data input buffer connected to the write data bus. 2. The apparatus according to claim 1, further comprising an address input circuit provided commonly to said plurality of memory banks, wherein an output of said address input circuit is input to said plurality of address counters. 13. The semiconductor device according to claim 1. 3. A plurality of clock generation circuits provided corresponding to each of the plurality of memory banks, wherein each of the plurality of address counters counts in synchronization with an output signal of each of the plurality of clock generation circuits. The semiconductor device according to claim 1, wherein: 4. A semiconductor memory having a plurality of memory banks operable independently of each other and performing continuous data reading and continuous data writing in synchronization with a clock, wherein a data writing operation to one of the plurality of memory banks is performed. During execution, if a command instructing a data read operation to the same memory bank is input, the data write operation is stopped. If a command to instruct a data read operation to another memory bank is input, the write operation is stopped. A semiconductor device characterized by continuing.