JP2000339957A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with a write system by which a skew generated between a clock signal and a DQ strobe signal can be permitted to the full. SOLUTION: In a DDR-SDRAM, the input timing of a signal to every pin is prescribed by the point of intersection of a clock signal CLK with a clock signal /CLK and by both the edge of the rise of a DQ strobe signal (DSQ) and the edge of its fall. The DDR-SDRAM is featured in such a way that, on the basis of the logical product of the clock signals CLK, /CLK with the DQ strobe signal (DSQ), write data which is input to a write driver(WD) 23 is controlled. Since the logical product of the clock signals with the strobe signal is used, it is possible to prevent a skew from being generated between the signals, and the margin of a write operation can be reduced. In addition, since the skew is not increased more than necessary, an erroneous write operation is prevented, and the reliability of this semiconductor memory device can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a DDR (Double Data Rate) -SD.
Regarding RAM.

[0002]

2. Description of the Related Art Generally, in an SDRAM, a command (eg, / CS, / RAS, / CAS, / WE) is generated at a rising edge of a clock signal CLK from a low ("L") level to a high ("H") level. Etc.), input timings of signals to pins, address pins, DQ pins, DQM pins, and the like.

FIG. 9 shows a simplified waveform of an input signal to each pin and its timing in the write mode of the SDRAM. In FIG. 9, tCMS is a command setup time, and tCMH is a command hold time.
Time, tAS is address setup time, t
AH is the address hold time, tDS is the data input setup time, and tDH is the data input time.
Each hold time is shown, and the hatched area is Don't Care.

[0004] A bank active command is input (of various control signals acting as command COM, / CS is at "L" level, / RAS is at "L" level,
/ CAS is at “H” level, / WE is at “H” level)
The row address of the address signal Add is fetched. At this time, the output disable / write mask DQM is at “L” level and the clock enable signal CK
E is at "H" level.

Subsequently, a write command is input (of various control signals acting as command COM, / CS is at "L" level, / RAS is at "H" level, / C
AS is at the “L” level, / WE is at the “L” level), and the column address of the address signal Add is fetched. At this time, the output disable / write mask signal DQM maintains the “L” level, and the clock enable signal CKE maintains the “H” level. As a result, Din1, Din2,
Are sequentially supplied to the memory cells to perform writing.

In the SDRAM, the clock signal CLK
The setup and hold are defined based on the rising of the “L” level and “H” level to １ ／ level. Also, each input signal waveform is １ ／ of that at the time of signal switching.
The level is the starting point.

The DDR-SDRAM basically has the same configuration as the above-mentioned SDRAM and performs the same operation, but receives a clock signal / CLK having a phase opposite to that of the clock signal CLK. And a pin for inputting a DQ strobe signal DQS. The DQ strobe signal DQS is basically the same signal as the write data DQ, but is externally input at the time of writing and output from the chip at the time of reading.

FIG. 10 is a diagram for explaining the operation of the DDR-SDRAM, and shows a simplified waveform of an input signal to each pin and its timing in the write mode. In FIG. 10, tIS is an input setup time, tIH is an input hold time, tDS is a data input setup time, and tDH is a data input hold time.

In the DDR-SDRAM, the setup and hold of the address signal Add, the command COM, and the clock enable signal CKE are performed by the clock signal CL.
The timing is defined at the intersection of K and / CLK. At this time, the clock signal CLK rises from the “L” level to the “H” level, and the clock signal / CLK changes to the “H” level.
It is stipulated that the input of the command COM and the address signal Add is allowed only at the intersection of the falling from the level to the “L” level. In short, since the clock signal CLK rises from the “L” level to the “H” level, it is substantially the same as the SDRAM. However, in the DDR-SDRAM, the input timing of the DQ (write data) pin and the DM (write mask data) pin is specified at both the rising edge and the falling edge of the DQ strobe signal DQS. DDR
Here, the reading and writing of data are performed at a double cycle of the clock signal CLK.

As described above, in the write operation of the DDR-SDRAM, the input timing of the signal to each pin is defined at both the intersection of the clock signals CLK and / CLK and the rising edge and the falling edge of the DQ strobe signal DQS. Done.

In the DDR-SDRAM, the skew between the clock signals CLK and / CLK and the DQ strobe signal DQS has a rule as shown in FIG. In FIG. 11, tDSV indicates a strobe effective window of input data, tDQSS indicates a setup of a transition from an “L” level to an “H” level of a clock, and tDSV defines a window of a signal DQS. CLK is defined.

First, clock signals CLK and / CLK
And the signal DQS are signals to be unified, but this DQ strobe signal was born from a user's desire to reduce the burden on the clock driver.

As described above, in the DDR-SDRAM, two types of signals are used for defining the input timing of the write mode. The skew time between these two signals is specified, but does not exist in the conventional SDRAM. For this reason, a problem arises if the DDR-SDRAM write system is constructed with the SDRAM write system (when the DQ strobe signal DQS and the clock signal CLK are externally input).

First, the basic write operation of the SDRAM will be described with reference to the timing chart of FIG. When the write command COM is input after the bank is activated, (1) first, the column address in the address signal Add is decoded, and the column selection line CSL0 is selected in synchronization with the clock signal CLK. (2) In parallel, the write data DQ0 is fetched in synchronization with the clock signal CLK. (3) This data DQ0 is transferred to the write driver WD, and writing to the memory cell is performed. These series of operations are synchronized with a clock signal CLK which is an absolute reference signal. Then, in synchronization with the next rising of the clock signal CLK from the “L” level to the “H” level, the data DQ1 is transferred to the write driver WD and written into the memory cell, and the data DQ1 is changed from the “L” level of the clock signal CLK to “ The data DQ2 is transferred to the write driver WD and written to the memory cell in synchronization with the next rise to the H level, and the same operation is sequentially repeated thereafter.

On the other hand, in the DDR-SDRAM, as shown in the timing chart of FIG. 10, the input timing of the write command and the column address includes the rising of the clock signal CLK from the "L" level to the "H" level, and The column selection signal CSL and the write driver are controlled by the clock signal CLK because it is defined at the intersection of the falling of the clock signal / CLK from the “H” level to the “L” level. Write data DQ (Din0, Din1, Din2,...) And write mask data DM whose timing is defined by both rising and falling of the DQ strobe signal DQS are taken in synchronization with the inversion operation of the signal DQS. The signal is transferred to the write driver in synchronization with the inversion of the signal DQS, and writing to the memory cell is performed.

However, in this system, when a skew SKW as shown in FIG. 13 occurs between the clock signals CLK and / CLK and the DQ strobe signal DQS,
Since the transfer timing of the write data DQ and the write mask data DM to the write driver is advanced (when DQS is fast) or delayed (when DQS is slow),
The write operation margin is reduced. In addition, if the skew increases, the possibility of erroneous writing increases, and the reliability decreases.

[0017]

As described above, the conventional semiconductor memory device has a problem that a skew occurs between the clock signal and the DQ strobe signal, and the write operation margin is reduced.

Further, when the skew increases, the possibility of erroneous writing increases, and there is a problem in that the reliability decreases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a write system capable of maximally allowing a skew generated between a clock signal as an external input signal and a DQ strobe signal. To provide a semiconductor memory device provided with the same.

Another object of the present invention is to provide a semiconductor memory device capable of reliably preventing erroneous writing and improving reliability.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor memory device wherein a first clock signal rises from a low level to a high level and a first clock signal having a phase opposite to that of the first clock signal. The input timing of the write command and the column address is defined at the intersection of the falling of the clock signal 2 from the high level to the low level, and the rising and falling of the DQ strobe signal which is input from the outside at the time of writing and output from the chip at the time of reading In the semiconductor memory device in which the input timing of the write data and the write mask data is defined by both of the first and second,
And the write data input to the write driver is controlled based on the logical product of the clock signal and the DQ strobe signal.

According to a second aspect of the present invention, there is provided the semiconductor memory device, wherein the first clock signal rises from a low level to a high level, and the second clock signal having a phase opposite to that of the first clock signal. The input timing of a write command and a column address is defined at the intersection of the falling from the high level to the low level of the DQ. The DQ strobe signal that is input from the outside during writing and is output from the chip during reading is written at both the rising and falling of the chip. In a semiconductor memory device in which input timing of data and write mask data is defined, a period in which a column selection signal is at a high level and an activation period of a write driver are defined by the first and second clock signals and the DQ strobe signal. The control is based on the logical product of.

Further, in the semiconductor memory device according to the present invention, the first clock signal rises from a low level to a high level, and the second clock signal having a phase opposite to that of the first clock signal. The input timing of a write command and a column address is defined at the intersection of the falling from the high level to the low level of the DQ. The DQ strobe signal that is input from the outside during writing and is output from the chip during reading is written at both the rising and falling of the chip. In a semiconductor memory device in which input timing of data and write mask data is defined, an output signal of a first input buffer to which write data is input and a second input buffer to which the first and second clock signals are input Output signal,
An output signal of a third input buffer to which the first and second clock signals are input, and an output signal of a fourth input buffer to which the DQ strobe signal is input; A latch circuit for latching the output signal of the second input buffer based on the logical product of the output signals of the second and third input buffers and the output signal of the fourth input buffer.

According to a fourth aspect of the present invention, in the semiconductor memory device, the first clock signal rises from a low level to a high level, and the high level of the second clock signal having a phase opposite to that of the first clock signal. The input timing of the write command and the column address is defined at the intersection of the fall from the level to the low level. The write data is input from the outside at the time of write, and the write data is input at both the rise and fall of the DQ strobe signal output from the chip at the time of read. In a semiconductor memory device in which input timing of write mask data is defined, a first primary latch that latches input write data in synchronization with a rise of a DQ strobe signal from a low level to a high level; The data is changed from the high level of the DQ strobe signal to the low level. A second primary latch that latches in synchronization with the falling edge of the data, and data latched in the first and second primary latches are logically ANDed with the DQ strobe signal and the first and second clock signals. Based on the first
Alternatively, there is provided a secondary latch for holding a half cycle of the second clock signal, and a write control clock generation circuit for supplying an output signal of the secondary latch to the write driver as write data.

Further, in the semiconductor memory device according to a fifth aspect of the present invention, the first clock signal rises from a low level to a high level, and the second clock signal has a phase opposite to that of the first clock signal. The input timing of the write command and the column address is defined at the intersection of the falling of the signal from the high level to the low level, and the DQ is input from the outside during writing and is output from the chip during reading.
In a semiconductor memory device in which input timings of write data and write mask data are defined by both rising and falling of a strobe signal, input write data is latched in synchronization with a rise of a DQ strobe signal from a low level to a high level. A first primary latch that latches the input write data in synchronization with a fall of the DQ strobe signal from a high level to a low level, and a second primary latch that latches the input write data in the first primary latch. A first data holding unit that holds data for one cycle of the first or second clock signal based on a logical product of the DQ strobe signal and the first and second clock signals;
And the data latched in the second primary latch is divided into the first and second clock signals based on the logical product of the DQ strobe signal and the first and second clock signals. A write control clock generating circuit for supplying the output signals of the first and second secondary latches to the write driver as write data.

According to the first aspect of the present invention, the write data input to the write driver is controlled based on the logical product of the first and second clock signals and the DQ strobe signal. Skew can be prevented from occurring with the DQ strobe signal, and a decrease in the margin of the write operation can be suppressed. Further, since the skew does not increase more than necessary, erroneous writing can be prevented and the reliability can be improved.

According to the second aspect of the present invention, the period during which the column selection signal is at a high level and the period during which the write driver is activated are defined by the first and second clock signals and the DQ strobe signal. Since the control is performed based on the logical product, it is possible to prevent a skew from occurring between the clock signal and the DQ strobe signal, and to suppress a decrease in the margin of the write operation. Further, since the skew does not increase more than necessary, erroneous writing can be prevented and the reliability can be improved.

According to a third aspect of the present invention, the latch circuit includes the output signals of the second and third input buffers to which the first and second clock signals are input and the fourth input buffer. The output signal of the first input buffer to which the write data is input is latched based on the logical product of the output signals of the first and second output signals, so that skew between the clock signal and the DQ strobe signal can be prevented, and the write operation can be prevented. Margin reduction can be suppressed. Further, since the skew does not increase more than necessary, erroneous writing can be prevented and the reliability can be improved.

According to the fourth aspect of the present invention, as a primary latch for latching input write data in synchronization with a DQ strobe signal, latch is performed in synchronization with a rise of a DQ strobe signal from a low level to a high level. Since the path is divided into two paths, that is, the first primary latch and the second primary latch that latches in synchronization with the fall of the DQ strobe signal from the high level to the low level, the write data holding period in the chip is reduced. Can be extended,
A transfer margin to the secondary latch is created. As a result, even if the skew increases, erroneous writing can be prevented and reliability can be improved.

According to a fifth aspect of the present invention, a primary latch for latching input write data in synchronization with a DQ strobe signal is provided in synchronization with a rise of a DQ strobe signal from a low level to a high level. And the second primary latch which latches in synchronization with the fall of the DQ strobe signal from the high level to the low level. The retention period can be extended, and a transfer margin to the first and second secondary latches is created. As a result, even if the skew increases, erroneous writing can be prevented and reliability can be improved. In addition, since two secondary latches are provided corresponding to the first and second primary latches, the data window can be changed to the first and second primary latches.
For one cycle of the clock signal of FIG.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is for describing a semiconductor memory device according to an embodiment of the present invention, and shows a schematic configuration by extracting column-related circuits in a DDR-SDRAM.

The DQ latch system described here
The main example is the WD serial transfer type (of the RWD line)
The parallel transfer type is listed as an example.

The DDR-SDRAM shown in FIG. 1 has input buffers 11 to 16, a latch circuit 17, a column address latch 18, a counter 19, a mode set register 20,
It includes a column predecoder 21, a write control clock generation circuit 22, a write driver (WD) 23, a memory cell array 24, a column decoder 25, a row decoder 26, and the like. The input buffer 11 has write data DQn, the input buffer 12 has an address signal Addn, and the input buffer 13 has a clock signal CQn.
LK, / CLK, the input buffer 14 has clock signals CLK, / CLK, the input buffer 15 has a DQ strobe signal DQS, and the input buffer 16 has control signals / RAS, / CAS, / WE, / CS. Each is entered. Each of the input buffers 11, 13,
14, 15 output signals IntDQ, IntCLK, / I
ntCLK and IntDQS are the latch circuits 17 respectively.
Supplied to The input buffers 12 and 13 have substantially the same differential input configuration, and clock signals CLK and / CLK are supplied to each of them as a differential input signal. At this time, the clock signal CLK is input to one input terminal of the input buffer 12, and the clock signal / CLK is supplied to the other input terminal. A clock signal / CLK is supplied to an input terminal of the input buffer 13 corresponding to one input terminal of the input buffer 12, and a clock signal CLK is supplied to an input terminal corresponding to the other input terminal. Output signals of these input buffers 12 and 13 are supplied to the column address latch 18. The column address latch 18 is provided with a counter 19, which is incremented each time a latch operation is performed. Output signal IntCL of the input buffers 13 and 15
K (/ IntCLK), IntDQS (/ IntDQ
S) is supplied to the write control clock generation circuit 22. The output signals of the input buffers 13 and 16 are
It is supplied to the mode set register 20, and each mode entry signal is output from the mode set register 20.

The output signal WDn of the latch circuit 17 is
It is supplied to the write driver 23. The output signal of the column address latch 18 is supplied to the column predecoder 2
1 and predecoded, and a predecode signal output from the column predecoder 21 is supplied to the write driver 23 and the column decoder 25. Further, the output signal of the write control clock generation circuit 22 is supplied to the write driver 21 and the column decoder 25. The output signal of the write driver 23 is supplied to the memory cell array 24.

In the memory cell array 24, a plurality of word lines WL are provided along a row direction, and a plurality of bit lines BL are provided along a column direction. A memory cell MC including a transistor and a capacitor is arranged at each intersection position.
The word line WL is selected by a row decoder 26, and the bit line BL is selected by a column decoder 25.

Although not shown, the row decoder 2
A row-related circuit is connected to 6, and a word line WL is selected.

FIGS. 2 (a) to 2 (c) and FIG.
2 shows a detailed configuration example of a latch circuit 17 in the circuit shown in FIG. The circuit shown in FIG. 2A includes the internal clock signal IntCL output from the input buffer 13.
A circuit for generating clock signals CLKINC and CLKINT for controlling the latch operation from K,
32 and 33 and a transfer gate 34. The transfer gate 34 has a configuration in which a current path of an N-channel MOS transistor whose gate is connected to a power supply Vcc and a current path of a P-channel MOS transistor whose gate is connected to a power supply Vss are connected in parallel.

The internal clock signal IntCLK is supplied to the input terminal of the inverter 31. The output signal of the inverter 31 sequentially passes through the inverters 32 and 33, and the clock signal CLKINC is output from the output terminal of the inverter 33. Further, the internal clock signal IntCLK sequentially passes through the inverters 31 and 32 and the transfer gate 34, and is output as a clock signal CLKINT.

The circuit shown in FIG.
4 and clock signals / CLKINC and / C for controlling the latch operation from the internal clock signal / IntCLK output from
This is a circuit for generating LKINT, and the inverters 35 and 3
6, 37 and a transfer gate 38. The transfer gate 38 is configured such that a current path of an N-channel MOS transistor whose gate is connected to a power supply Vcc and a current path of a P-channel MOS transistor whose gate is connected to a power supply Vss are connected in parallel.

The internal clock signal / IntCLK is supplied to the input terminal of the inverter 35, and the output signal of the inverter 35 passes through the inverters 36 and 37 sequentially, and the clock signal / CLKINC is output from the output terminal of the inverter 37. The internal clock signal / IntCLK passes through the inverters 35 and 36 and the transfer gate 38 sequentially, and is output as a clock signal / CLKINT.

The circuit shown in FIG.
5 internal DQ strobe signal IntDQS
From DQ strobe signal DQSIN for controlling latch operation
C and DQSINT are generated by the inverter 3
9, 40 and 41 and a transfer gate 42. The transfer gate 42 includes a current path of an N-channel MOS transistor having a gate connected to the power supply Vcc, and a P-channel transistor having a gate connected to the power supply Vss.
The current paths of the channel type MOS transistors are connected in parallel.

The internal DQ strobe signal IntDQS is supplied to the input terminal of an inverter 39.
Output signal sequentially passes through inverters 40 and 41, and the DQ strobe signal DQSIN
C is output. Also, the internal DQ strobe signal Int
The DQS sequentially passes through the inverters 39 and 40 and the transfer gate 42, and receives the DQ strobe signal DQSINT.
Is output.

The circuit shown in FIG. 3 is an essential part of the latch circuit 17, and the signals CLKINC, CLKINT, / CL output from the circuits shown in FIGS. 2 (a) to 2 (c).
KINC, / CLKINT, DQSINC, DQSIN
Under the control of T, the internal write data IntDQ output from the input buffer 11 is latched, and the output signal WDn is supplied to the write driver 23.

This circuit comprises transfer gates 43 and 4
4, clocked inverters 45, 46, inverter 4
7, 48, 61, 62, 63, P-channel MOS transistors 49, 50, 51, 55, 56, 57, and N
Channel type MOS transistors 52, 53, 54, 5
8, 59 and 60 are included. The output signal IntDQ of the input buffer 11 is transferred to the transfer gate 4
3, 44 are supplied to one end. The transfer operations of the transfer gates 43 and 44 are controlled by signals DQSINT and DQSINC output from the circuit shown in FIG. The other end of the transfer gate 43 is connected to the output end of the clocked inverter 45 and the input end of the inverter 47, and the other end of the transfer gate 44 is connected to the output end of the clocked inverter 46 and the inverter 48. Input terminal is connected. The clocked inverters 45 and 46 connect the signals DQSINT and DQSI
The operation is controlled by the NC.

The gates of the MOS transistors 51 and 52 are connected to the connection point (node Na) between the input terminal of the clocked inverter 45 and the output terminal of the inverter 47. The current paths of the MOS transistors 49 to 54 are
It is connected in series between the power supplies Vcc and Vss. The signal CLKINC output from the circuit shown in FIG. 2A is supplied to the gate of the MOS transistor 49, and the signal DQSINC is supplied to the gate of the MOS transistor 50. The signal DQSINT is supplied to the gate of the MOS transistor 53, and the gate of the MOS transistor 5
4 is supplied with the signal CLKINT.

Similarly, the connection point (node N) between the input terminal of the clocked inverter 46 and the output terminal of the inverter 48
The gates of the MOS transistors 57 and 58 are connected to b). The current paths of the MOS transistors 55 to 60 are connected in series between the power supplies Vcc and Vss. M
The signal / CLKINC output from the circuit shown in FIG. 2B is supplied to the gate of the OS transistor 55.
The signal DQSIN is connected to the gate of the OS transistor 56.
T is supplied. The gate of the MOS transistor 59 is supplied with the signal DQSINC, and the gate of the MOS transistor 60 is supplied with the signal / CLKINT.

The connection points of the current paths of the MOS transistors 51 and 52 and the connection points of the current paths of the MOS transistors 57 and 58 are connected to the input terminal of the inverter 61 and the output terminal of the inverter 62, respectively. The output terminal of the inverter 61 is connected to the input terminals of the inverters 62 and 63. Then, an output signal WDn is output from the output terminal of the inverter 63 to the write driver 23.

FIGS. 4A and 4B respectively show FIGS.
Write control clock generation circuit 22 in the circuit shown in FIG.
(A) is a circuit diagram, and (b) is a DDR-SDRA related to this circuit.
6 is a timing chart of M. 4A, when the clock signal CLK rises from "L" level to "H" level and the DQ strobe signal DQS rises from "L" level to "H" level, the column selection signal CSLA, CSLB is set to “H” level. This circuit includes NAND gates 71 and 77 and inverters 72 to 76 and 78. The input terminal of the NAND gate 71 has an internal clock signal Int.
CLK and an internal DQ strobe signal / IntDQS, and the output of this NAND gate 71 is an inverter 72,
73 input terminals. Inverter 7
2 is supplied to one input terminal of a NAND gate 77, and the output signal of the inverter 73 is supplied to the other input terminal of the NAND gate 77 via inverters 74 to 76. The output of the NAND gate 77 is output as a signal ColCLK via the inverter 78 and supplied to the write driver 23 and the column decoder 25. The signal ColCLK is supplied to the inverters 73 to 7.
6 and a signal having a pulse width corresponding to the difference between the signal delay time of the inverter 72 and the signal delay time of the inverter 72.

Next, the write operation of the DDR-SDRAM shown in FIGS. 1 to 4 will be described focusing on the latch circuit 17 with reference to the timing chart of FIG.

Write data DQ and write mask data D
Since M is taken in at the rising edge and falling edge of the DQ strobe signal DQS (according to the tDS / tTH regulation), the primary latch in the latch circuit 17 shown in FIG. 3 performs the signal DQSINT, which is generated from the internal DQ strobe signal IntDQS, It is controlled by DQSINC. In addition, the secondary latch is provided at the intersection of the rising edge of the clock signal CLK and the falling edge of the clock signal / CLK with DQ
In order to synchronize with the inversion operation of strobe signal DQS, signal CLKI generated from internal clock signal IntCLK
NT, CLKINC, internal clock signal / IntCLK
, And the signals DQSINT and DQSINC.

As a result, as shown in the timing chart of FIG. 5, the internal write data IntDQ (DQa,
DQb, DQc, DQd,...) Are latched in a latch section (node Na) formed by clocked inverter 45 and inverter 47 in response to the fall of internal DQ strobe signal IntDQS, and internal DQ strobe signal IntDQS is output. In response to the rise, the latch is latched by a latch section (node Nb) formed by clocked inverter 46 and inverter 48. And the inverter 6
An output signal WDn is output from the output terminal of the output terminal No. 3.

In the DDR-SDRAM, the DQ strobe signal DQS and the clock signal CLK are operated in the same phase. At this time, a circuit path to be latched at the rising edge and the falling edge of the DQ strobe signal DQS is divided up and down to thereby form an internal latch data window. Can be expanded. The reason for using the two-part configuration is that if a skew occurs between the DQ strobe signal DQS and the clock signal CLK, the transfer margin to the secondary latch is reduced if the two-part configuration is not used.

In the latch circuit 17, write data DQ and write mask data DM synchronized with the DQ strobe signal DQS and the clock signal CLK are generated, and these signals are transferred to the write driver 23 via the RWD line. The write driver 23 performs writing to the memory cell MC via the M / LDQ line.

Similarly, the clock signal CLK and DQ
An AND signal ColCLK with the strobe signal DQS is used. That is, the write control clock generation circuit 22
Is used as the trigger signal. This is because, when a skew occurs between the clock signal CLK and the DQ strobe signal DQS, the control of the write command and the column address signal taken in synchronization with the clock signal CLK is performed by the write data DQ and the write mask data. This is because the operation is not performed before the DM is transferred to the write driver 23 or at the timing when the data of the next cycle is read (that is, the timing of the fetched write data DQ and the write mask data DM is matched). With such a configuration, the write data D
The timing for fetching the Q and the write mask data DM and activating the write driver 23 is determined by a logical product signal Col of the DQ strobe signal DQS and the clock signal CLK.
CLK can be controlled.

The present invention is not limited to the above-described embodiment, but can be implemented in various modifications without departing from the gist. Next, another configuration example of the latch circuit 17 and the write control clock generation circuit 22 will be described.

FIGS. 6A and 6B respectively show FIGS.
FIG. 13 is a circuit diagram for explaining another configuration example of the secondary latch in the circuit shown in FIG. The secondary latch shown in FIG. 3 converts input data into clock signals CLK and / CLK.
Of the clock signals CLK,
/ CLK for one cycle. The circuit section shown in FIG. 6A is connected to the node Na of the primary latch in the circuit shown in FIG. 3, and the circuit section shown in FIG.
The node Nb of the primary latch in the circuit shown in FIG.
Connected to. That is, in the circuit shown in FIG.
The data transferred through the two paths of the primary latch is
In the circuits shown in FIGS. 6A and 6B, the data transferred to the two paths of the primary latch is input to the two secondary latches, while the data is input to the next latch.

In the circuit configuration shown in FIG. 3, the write data and the write mask data are serially time-divisionally transferred and transferred, so that the number of bus lines up to the write driver 23 can be reduced. CL
Only one-half period of K can be held. In contrast, FIG.
According to the configurations shown in FIGS. 3A and 3B, although the number of bus lines is large, the data window can hold one cycle of the clock signals CLK and / CLK.
The margin in the circuit operation can be increased as compared with the configuration shown in FIG.

FIGS. 7A and 7B are diagrams for explaining another example of the configuration of the write control clock generation circuit 22 in the circuit shown in FIG. 1. FIG. 7A is a circuit diagram, and FIG. b) Figure shows DDR-SDRA related to this circuit
6 is a timing chart of M. The circuit shown in FIG. 7A outputs the column selection signal CSLA when the clock signal CLK rises from “L” level to “H” level and the DQ strobe signal DQS rises from “L” level to “H” level. When the clock signal / CLK falls from "H" level to "L" level and the DQ strobe signal DQS falls from "H" level to "L" level, the column selection signal CSL
B is set to the “H” level. This circuit comprises NAND gates 71, 77, 91, 97 and inverters 72-77.
76, 78, 92 to 96, 98. The input terminal of the NAND gate 71 has an internal clock signal IntCLK and an internal DQ strobe signal / IntDQS.
The output of the NAND gate 71 is supplied to input terminals of inverters 72 and 73, respectively. The output signal of the inverter 72 is supplied to one input terminal of a NAND gate 77, and the output signal of the inverter 73 is supplied to the other input terminal of the NAND gate 77 via inverters 74 to 76. And this NAND gate 77
Is output as a signal ColCLK via an inverter 78. Also, the input terminal of the NAND gate 91
An internal clock signal / IntCLK and an internal DQ strobe signal / IntDQS are supplied.
Are supplied to input terminals of inverters 92 and 93, respectively. An output signal of the inverter 92 is supplied to one input terminal of a NAND gate 97, and is supplied to the inverter 93.
Is supplied to the other input terminal of the NAND gate 97 via the inverters 94 to 96. Then, the output of the NAND gate 97 is output as a signal / ColCLK via the inverter 98, and the write driver 23
Is supplied to the column decoder 25.

Even with such a configuration, the skew generated between the clock signal, which is an external input signal, and the DQ strobe signal can be tolerated as much as possible, and erroneous writing can be reliably prevented to improve reliability.

FIG. 8 is a circuit diagram showing another example of the configuration of the circuit shown in FIG. This circuit comprises NAND gates 81-84, inverters 88-90, a P-channel type M
The configuration includes an OS transistor 85, an N-channel MOS transistor 86, and a resistor 87. The input terminal of the NAND gate 81 has an internal clock signal IntCLK
And an internal DQ strobe signal / IntDQS,
The output of the NAND gate 81 is supplied to one input terminal of the NAND gate 82. The output signal of the NAND gate 82 is supplied to one of the input terminals of the NAND gates 83 and 84 and the MO signal.
It is supplied to the gates of S transistors 85 and 86, and the other input terminal of the NAND gate 82 is connected to the NAND gate 8
3 output signals are provided. MOS transistor 8
5, the current path of the resistor 87 and the current path of the MOS transistor 86 are connected in series between the power supplies Vcc and Vss.
An input terminal of an inverter 88 is connected to a connection point between the MOS transistor 85 and the resistor 87.
Is supplied to the input terminal of the inverter 89. The output signal of the inverter 89 is supplied to NAND gates 83 and 8.
4 is supplied to the other input terminal. The output of the NAND gate 84 is supplied to the signal ColC via the inverter 90.
LK and supplied to the write driver 23 and the column decoder 25.

Note that two circuits shown in FIG. 8 are prepared, and the signal IntCL is provided in the same manner as the circuit shown in FIG.
K, / IntDQS and signals / IntCLK, / IntD
If QS is input, the same operation as the circuit shown in FIG. 7A is performed, and the same operation and effect can be obtained.

[0062]

As described above, according to the present invention, it is possible to obtain a semiconductor memory device having a write system capable of maximizing the skew generated between a clock signal as an external input signal and a DQ strobe signal.

Further, a semiconductor memory device which can reliably prevent erroneous writing and improve reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a semiconductor memory device according to an embodiment of the present invention, and showing a schematic configuration of a column-related circuit in a DDR-SDRAM extracted;

FIGS. 2A and 2B are diagrams for explaining a configuration example of a latch circuit in the circuit shown in FIG. 1; FIG. 2A is a diagram showing a circuit for generating a clock signal for write operation control from an internal clock signal; The figure shows a circuit that generates a clock signal for controlling the write operation from the internal clock signal.
FIG. 4C is a diagram showing a circuit for generating a DQ strobe signal for controlling a write operation from an internal DQ strobe signal.

FIG. 3 is a circuit diagram for explaining a detailed configuration example of a latch circuit in the circuit shown in FIG. 1 and showing a main part.

FIG. 4 is a diagram for explaining a configuration example of a write control clock generation circuit in the circuit shown in FIG. 1;
(A) is a circuit diagram, and (b) is a DD related to this circuit.
9 is a timing chart of an R-SDRAM.

FIG. 5 is a timing chart for explaining the operation of the semiconductor memory device according to the embodiment of the present invention;

6A and 6B are diagrams for explaining another configuration example of the latch circuit shown in FIG. 3; FIG. 6A is a circuit diagram showing a part of a secondary latch, and FIG. FIG.

FIG. 7 is a diagram for explaining another configuration example of the write control clock generation circuit in the circuit shown in FIG. 1;
(A) is a circuit diagram, and (b) is a DD related to this circuit.
9 is a timing chart of an R-SDRAM.

FIG. 8 is a circuit diagram showing another configuration example of the circuit shown in FIG.

FIG. 9 is a timing chart showing waveforms of input signals to respective pins and their timings in a write mode of the SDRAM.

FIG. 10 is a timing chart showing input signal waveforms to respective pins and their timings in a write mode of the DDR-SDRAM.

FIG. 11 is a timing chart for explaining a rule regarding skew between two signals of a clock signal and a DQ strobe signal in a DDR-SDRAM.

FIG. 12 is a timing chart for describing a basic write operation of the SDRAM.

FIG. 13 is a timing chart when the skew between the clock signal and the DQ strobe signal in the DDR-SDRAM is 0, when the DQ strobe signal is early, and when the DQ strobe signal is slow.

[Explanation of symbols]

11 to 16: input buffer, 17: latch circuit, 18: column address latch, 19: counter, 20: mode set register, 21: column predecoder, 22: write control clock generation circuit, 23: write driver, 24: memory Cell array, 25 column decoder, 26 row decoder, Addn address signal, DQn write data, CLK clock signal (first clock signal), / CLK clock signal (second clock signal), DQS DQ Strobe signal, / RAS, / CAS, / WE, / CS ... control signal, COM ... command, DM ... write mask data.

Claims (5)

[Claims] 1. A write command at an intersection of a rise of a first clock signal from a low level to a high level and a fall of a second clock signal having a phase opposite to that of the first clock signal from a high level to a low level. And the input timing of a column address are defined. The input timing of write data and write mask data is defined by both rising and falling edges of a DQ strobe signal which is externally input at the time of writing and output from the chip at the time of reading. A semiconductor memory device, wherein write data input to a write driver is controlled based on a logical product of the first and second clock signals and the DQ strobe signal. 2. A write command at an intersection of a rise of a first clock signal from a low level to a high level and a fall of a second clock signal having a phase opposite to that of the first clock signal from a high level to a low level. And the input timing of a column address are defined. The input timing of write data and write mask data is defined by both rising and falling edges of a DQ strobe signal which is externally input at the time of writing and output from the chip at the time of reading. In the device, a period in which a column selection signal is at a high level and an activation period of a write driver are controlled based on a logical product of the first and second clock signals and the DQ strobe signal. Storage device. 3. A write command at an intersection of a rise of a first clock signal from a low level to a high level and a fall of a second clock signal having a phase opposite to that of the first clock signal from a high level to a low level. And the input timing of a column address are defined. The input timing of write data and write mask data is defined by both rising and falling edges of a DQ strobe signal which is externally input at the time of writing and output from the chip at the time of reading. In the apparatus, an output signal of a first input buffer to which write data is input, an output signal of a second input buffer to which the first and second clock signals are input, and the first and second clock signals are The fourth input buffer to which the output signal of the third input buffer and the DQ strobe signal are input. The output signals of the buffers are respectively input, and the output signals of the first input buffer are latched based on the logical product of the output signals of the second and third input buffers and the output signal of the fourth input buffer. A semiconductor memory device provided with a latch circuit. 4. A write command at an intersection of a rise of a first clock signal from a low level to a high level and a fall of a second clock signal having a phase opposite to that of the first clock signal from a high level to a low level. And the input timing of a column address are defined. The input timing of write data and write mask data is defined by both rising and falling edges of a DQ strobe signal which is externally input at the time of writing and output from the chip at the time of reading. A first primary latch that latches input write data in synchronization with a rise of a DQ strobe signal from a low level to a high level; and a device that shifts the input write data from a high level to a low level of the DQ strobe signal. Second latching in synchronization with the falling edge of A latch and the data latched by the first and second primary latches are divided by a half of the first or second clock signal based on the logical product of the DQ strobe signal and the first and second clock signals. A semiconductor memory device comprising: a secondary latch that holds a cycle; and a write control clock generation circuit that supplies an output signal of the secondary latch to the write driver as write data. 5. A write command at an intersection of a rise of a first clock signal from a low level to a high level and a fall of a second clock signal having a phase opposite to that of the first clock signal from a high level to a low level. And the input timing of a column address are defined. The input timing of write data and write mask data is defined by both rising and falling edges of a DQ strobe signal which is externally input at the time of writing and output from the chip at the time of reading. A first primary latch that latches input write data in synchronization with a rise of a DQ strobe signal from a low level to a high level; and a device that shifts the input write data from a high level to a low level of the DQ strobe signal. Second latching in synchronization with the falling edge of A latch and data latched in the first primary latch are held for one cycle of the first or second clock signal based on a logical product of the DQ strobe signal and the first and second clock signals. The data latched by the first secondary latch and the second primary latch is calculated based on the logical product of the DQ strobe signal and the first and second clock signals.
A second secondary latch for holding one cycle of the first or second clock signal, and a write control clock generator for supplying output signals of the first and second secondary latches as write data to a write driver A semiconductor memory device provided with a circuit.