JP2002111488A - Oscillating circuit of phase locked loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillating circuit of phase locked loop capable of detecting a off-synchronization precisely with a simple phase comparison circuit and capable of reducing jitter of clock signals of oscillation outputs even in any type of the comparison circuit. SOLUTION: In the oscillating circuit, a charge pomp 7-1 controls charge- discharge of a smoothing filter 7-2 to input an output voltage of the filter 7-2 into a voltage controlled oscillator 7-3 as a control voltage by the control signal responding to a phase-difference from a reference signal. With connecting a constant-current circuit 1-1 in shunt with the pomp 7-1 to the filter 7-2, the circuit 1-1 applies or sucks constantly a constant current to the filter 7-2 to apply the output voltage of the filter 7-2 applied or sucked constantly the constant current all the time as the control voltage of the oscillator 7-3, so that the off-synchronization is detected by comparing the control voltage with a reference voltage by a comparator 1-4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) oscillation circuit, and more particularly to a phase locked loop for extracting a clock signal synchronized with an electric or optical received signal in a transmission apparatus. The present invention relates to an oscillation circuit, which detects a loss of synchronization due to disconnection of a received signal or the like, and a phase locked loop oscillation circuit including a circuit for reducing jitter of an output clock signal.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration of a conventional phase locked loop oscillation circuit having an out-of-synchronization detecting circuit. The phase locked loop oscillation circuit inputs the first and second control signals output from a phase comparison circuit (not shown) to the charge control terminal and the discharge control terminal of the charge pump 7-1, respectively, and Output signal of the low-pass filter 7-2
The control voltage smoothed by the voltage control oscillator (VCO) 7-3
Add to

A voltage-controlled oscillator (VCO) 7-3 outputs a clock signal having a frequency corresponding to the input control voltage, and the clock signal is supplied to a phase comparison circuit (not shown). Is compared to The phase comparison circuit is
A first control signal corresponding to the lag phase difference and a second control signal corresponding to the lead phase difference are output, and the output of the voltage controlled oscillator (VCO) 7-3 is output by the first and second control signals. The phase of the clock signal is controlled.

If the first and second control signals are not properly output, the phase of the clock signal output from the voltage controlled oscillator (VCO) 7-3 will not be maintained properly, and the state will be out of synchronization. Therefore, the out-of-synchronization detection circuit 7-4 monitors whether the first and second control signals are output properly.

The out-of-synchronization detection circuit 7-4 includes first and second control signals corresponding to the phase difference (a signal output in a negative logic is a signal that has been made a positive logic in an inversion circuit 7-5). The logical sum output signal is input to the OR circuit 7-6, and is input to the gate terminal of a switch element such as the transistor Tr. The transistor Tr is connected to the power supply voltage VCC via the resistors R1 and R2, and the connection point (e) of the resistors R1 and R2 is connected to the capacitor C1 and the input terminal of the comparator 7-7.

[0006] The comparator 7-7 is connected to the voltage at the connection point (e) between the capacitor C1 and the resistors R1 and R2 and the reference voltage Vre.
f, and detects an out-of-synchronization state of the phase-locked loop oscillation circuit based on the comparison result, and outputs an alarm (ALM) signal in the out-of-synchronization state.

That is, in the out-of-synchronization detection circuit 7-4, the transistor Tr becomes conductive only when the control signal is output to the charge pump 7-1, and the DC input voltage to the comparator 7-7 decreases. The comparator 7-7 observes the degree of the voltage drop, and when the voltage becomes equal to or lower than the reference voltage Vref, determines that the state is out of synchronization and outputs an alarm (ALM) signal.

FIG. 8 shows an operation waveform timing chart of each part of the phase locked loop oscillation circuit. (A) of FIG.
Shows operation waveforms at the time of synchronization lock, and FIG. 11B shows operation waveforms at the time of loss of synchronization. FIG. 9A shows a first control signal for charge pump charging based on the delay phase difference,
(B) of the figure shows the first control signal converted to the positive logic by the inverting circuit 7-5, and (c) of the figure shows the second control signal for charge pump discharge based on the leading phase difference. Show. (D) of the figure shows the logical sum output of the first and second control signals, and (e) of the figure shows the resistance R of the out-of-sync detection circuit 7-4.
1 shows a voltage waveform at a connection point (e) between R2 and a capacitor C1.

As shown in FIG. 1A, at the time of synchronization lock, since the phase difference from the reference signal detected by a phase comparison circuit (not shown) is small, the first and second phase differences are adjusted. 2, the pulse width of the control signal is narrow, the pulse width output from the OR circuit 7-6 and input to the transistor Tr is narrow, so that the transistor Tr conducts only for a short time, and the connection between the resistors R1 and R2 and the capacitor C1. The voltage at point (e) is
Since the voltage becomes close to the power supply voltage VCC and exceeds the reference voltage Vref, the comparator 7-7 determines that the synchronous lock state is established, and does not output the alarm (ALM) signal.

On the other hand, as shown in FIG. 1B, when the synchronization is lost, since the phase difference from the reference signal is large, the pulse width of the first and second control signals for adjusting the phase difference is The output is output from the OR circuit 7-6, and the transistor Tr
, The conduction time of the transistor Tr becomes long, and the resistors R1 and R2 and the capacitor C1
Since the voltage at the connection point (e) falls below the reference voltage Vref, the comparator 7-7 determines that it is out of synchronization, and outputs an alarm (ALM) signal.

The out-of-synchronization detection circuit of the above-described phase locked loop oscillation circuit operates in the locked state based on the first and second control signals output as a pulse width having a length corresponding to the phase difference from the reference signal. Or out of synchronization. However, the waveforms of the first and second control signals output in accordance with the phase difference from the reference signal vary depending on the configuration of the phase comparison circuit, and are not necessarily output as pulse width signals having a length according to the phase difference. Not necessarily.

FIG. 9 shows a configuration example of a phase locked loop oscillation circuit in which the pulse duty ratio of the control signal changes according to the phase difference. This configuration example uses a D-type flip-flop circuit 9-1 as a phase comparison circuit, and outputs an output signal of a voltage controlled oscillator (VCO) 7-3 to a clock input terminal C of the D-type flip-flop circuit 9-1. , And the inverted output XQ of the D-type flip-flop circuit 9-1 is connected to the input terminal D of the D-type flip-flop circuit 9-1. Input to the reset terminal R of the circuit 9-1.

The D-type flip-flop circuit 9-1
Is connected to the charge control terminal (UP) of the charge pump 7-1, and the negative logic output XQ of the D-type flip-flop circuit 9-1 is connected to the discharge control terminal ( DOWN).

FIG. 10 shows an operation waveform timing chart of the above phase locked loop oscillation circuit at the time of synchronous lock. 3A shows a reference clock (input clock) signal as a reference signal, and FIG. 3B shows an inverted signal of the input clock signal, that is, a D-type flip-flop circuit 9-.
1 (c) shows the output signal of the voltage-controlled oscillator (VCO) 7-3, that is, the clock input waveform of the D-type flip-flop circuit 9-1, and FIG. Shows the waveform of the positive logic output Q of the D-type flip-flop circuit 9-1. FIG. 7E shows the waveform of the negative logic output XQ of the D-type flip-flop circuit 9-1, and FIG. Shows the output waveform of the charge pump 7-1, and (g) of the same figure shows the output waveform of the filter 7-2.

At the time of synchronous lock, (c) and (d) of FIG.
As shown in FIG. 10, at the rising edge of the output signal of the voltage controlled oscillator (VCO), the positive logic output Q of the D-type flip-flop circuit becomes high level, and as shown in FIGS. At the falling edge of the inverted clock signal, the positive logic output Q of the D-type flip-flop goes low.

During the period in which the positive logic output Q of the D-type flip-flop circuit shown in FIG. 2D is at a high level, the output of the charge pump shown in FIG. While the positive logic output Q is at a low level (the negative logic output XQ is at a high level), the output of the charge pump is at a low level.

Therefore, at the time of synchronous lock, the first and second control signals applied to the charge control terminal and the discharge control terminal of the charge pump are both output as pulse signals having a duty ratio of 50%, and the phase difference from the input clock is Occurs, the pulse duty ratio of the first and second control signals changes, but the sum of the high-level section of the first control signal and the high-level section of the second control signal has a phase difference Does not change.

Next, FIG. 11 is a timing chart of operation waveforms when the input clock of the phase locked loop oscillation circuit is cut off. The operation waveforms (a) to (g) of FIG. 10 show the same signal waveforms as the signal in FIG. 10, but the input clock signal shown in FIG. And its inverted signal, D shown in FIG.
The reset input of the flip-flop circuit remains high.

Therefore, the D-type flip-flop circuit is not reset by the input clock signal, and its positive logic output Q is, as shown in FIG.
O) is inverted every time the rising edge of the output signal is input, and operates as a simple 1/2 frequency dividing circuit.

For this reason, when the input clock is cut off, the first and second control signals applied to the charge control terminal and the discharge control terminal of the charge pump are pulses having a duty ratio of 50% and a cycle twice as long as the synchronous lock. Signal, and the output of the charge pump also has a waveform in which the high-level period and the low-level period having a cycle twice as long as that of the synchronous lock are output alternately at a rate of 50%. Instead, the voltage controlled oscillator (VCO) runs on its own at the oscillation frequency of the center frequency.

Accordingly, when the out-of-synchronization detecting circuit shown in FIG. 7 detects an out-of-synchronization state such as an input clock disconnection in the phase locked loop oscillation circuit having the configuration shown in FIG. In both cases of locking and out-of-synchronization, the logical sum of the first and second control signals is always a logical level of "1", so that the out-of-synchronization state cannot be detected. Therefore, to detect the out-of-synchronization state of the phase locked loop oscillation circuit having the configuration shown in FIG.
Separately, an out-of-synchronization detection circuit for detecting a pulse duty ratio and a pulse period and comparing the detected value with a reference value must be configured.

[0022]

[Problems to be solved by the invention]

Conventional out-of-sync detection circuit 7-4 shown in FIG.
Is caused by variations in the resistance of the transistor Tr during conduction and variations in the circuit constants of the resistors R1 and R2 and the capacitor C1.
7 changes severely, the reference voltage V
If the setting of ref is not strict, the accuracy of the out-of-synchronization detection deteriorates, and it becomes impossible to perform out-of-synchronization detection reliably.

Further, as in the phase locked loop oscillation circuit shown in FIG. 9, a phase comparison circuit of a type in which the control signal to the charge pump is output equally for the charge control and the discharge control even in the synchronous lock state is used. If so,
The out-of-synchronization detection circuit shown in FIG. 7 cannot detect out-of-synchronization, requires a separate out-of-synchronization detection circuit having a complicated configuration, requires a large number of parts, and requires a small-sized, low-power circuit. There was a problem that cost reduction became difficult.

According to the present invention, out-of-synchronization can be reliably detected without using components having precise circuit constants.
Regardless of the type of the phase lock loop oscillator circuit that outputs a control signal to the charge pump from the phase comparison circuit, out-of-synchronization can be detected with the same circuit configuration, and the clock signal of the oscillation output It is an object of the present invention to provide a phase-locked loop oscillation circuit that can reduce so-called jitter in which the phase shifts back and forth in time from a normal position.

[0026]

According to the present invention, there is provided a phase locked loop oscillating circuit comprising: (1) a charge pump to which a control signal corresponding to a phase difference from a reference signal is input, and charge / discharge control by the charge pump. In a phase-locked loop oscillating circuit including a smoothing filter and a voltage-controlled oscillator to which a voltage output from the smoothing filter is input as a control voltage, a phase-locked loop oscillator connected to the charge pump in parallel with the smoothing filter. A constant current circuit,
A constant current is constantly supplied or sucked to the smoothing filter,
The output voltage of the smoothing filter to which the constant current is constantly supplied or drawn is added as a control voltage of the voltage controlled oscillator.

(2) The phase-locked loop oscillating circuit compares a control voltage output from the smoothing filter and applied to the voltage-controlled oscillator with a reference voltage to detect a loss of synchronization of the phase-locked loop oscillator. It is provided with an off detection circuit.

(3) For the smoothing filter,
A constant current circuit that constantly supplies a constant current or a constant current circuit that constantly draws a constant current is configured to be alternatively connected, and the out-of-synchronization detection circuit compares the control voltage with two reference voltages. And a window comparator for detecting that the control voltage is out of the range of the two reference voltages.

(4) A phase difference avoiding a dead zone in which a control voltage corresponding to the minute phase difference is not output in a section where the phase difference from the reference signal is minute is a steady phase error during the synchronous lock operation. The amount of current supplied or drawn by the constant current circuit is set so that

[0030]

FIG. 1 shows a first embodiment of the present invention. According to the present invention, as shown in the figure, a charge pump 7-1 to which phase control signals (a) and (b) are input,
A loop filter (low-pass filter) 7-2 for smoothing the output voltage of the charge pump 7-1, and a voltage controlled oscillator (VCO) 7 to which a negative feedback control voltage according to the output voltage of the loop filter 7-2 is input. And a constant current circuit (DC current source) 1-1 connected in parallel with the charge pump and 7-1 to the input point (c) of the loop filter 7-2. , The connection point (c)
Is supplied to the voltage controlled oscillator (VCO) via the additional filter 1-2 and the voltage follower 1-3.
7-3.

The control voltage to the voltage controlled oscillator (VCO) 7-3 is observed by the comparator 1-4, and the result of comparison between the control voltage and the reference voltage Vref1 detects the loss of synchronization of the phase locked loop oscillation circuit. Then the alarm (A
LM) signal.

In the embodiment shown in FIG. 1, the loop filter 7- is connected to the input point (c) of the loop filter 7-2 in the same direction as the sink current (discharge current) of the charge pump 7-1.
Constant current circuit 1 that draws current from the second capacitor C1
When the phase-locked loop oscillation circuit is normally locked synchronously, a charge current for supplementing the current drawn by the constant current circuit 1-1 is supplied from the charge pump 7-1. The voltage obtained by smoothing the output voltage of the loop filter 7-2 by the additional filter 1-2 is kept constant.

When the charge of the capacitor C1 of the loop filter 7-2 is sucked by the constant current circuit 1-1 and the voltage drops, the voltage drop is reduced by the additional filter 1.
The control voltage of the voltage controlled oscillator (VCO) 7-3 is reduced through the voltage follower 1-3 and the voltage follower 1-3, and the oscillation frequency is decreased. Therefore, a decrease in the oscillation frequency is detected by the phase comparison circuit and the phase is advanced. This is because the signal is sent to the charge pump 7-1.

However, in the state where the phase locked loop oscillation circuit is out of synchronization lock (state where normal feedback is not applied), current is continuously supplied from the capacitor C1 of the loop filter 7-2 by the constant current circuit 1-1. Because of the extraction, the output voltage of the loop filter 7-2 continues to decrease, and the control voltage of the voltage controlled oscillator (VCO) 7-3 decreases.

FIG. 2 shows an operation waveform timing chart of each part of the phase locked loop oscillation circuit. (A) of FIG.
Shows operation waveforms at the time of synchronization lock, and FIG. 11B shows operation waveforms at the time of loss of synchronization. FIG. 9A shows a first control signal for charge pump charging based on the delay phase difference,
FIG. 9B shows a second control signal for charge pump discharge based on the leading phase difference. FIG. 3C shows the output voltage of the loop filter 7-2, and FIG. 4D shows the output voltage of the additional filter 1-2, that is, the control voltage of the voltage controlled oscillator (VCO) 7-3.

As shown in FIG. 2A, at the time of synchronous lock, the charge pump 7-1 is supplied by the first control signal (a) for supplementing the current drawn by the constant current circuit 1-1.
, A voltage obtained by smoothing the output voltage (c) of the loop filter 7-2 by the additional filter 1-2 becomes constant, and the control voltage of the voltage controlled oscillator (VCO) 7-3 becomes constant. However, the voltage controlled oscillator (VC
O) A steady phase error occurs in the output clock signal of 7-3.

On the other hand, when the synchronous lock of the phase-locked loop oscillation circuit is released, the output of the charge pump 7-1 is an output for performing charging (UP) and discharging (DOWN) at random, and ) Is performed and the output is not performed (DOWN), and conversely, the output is performed only by the discharge (DOWN) and the output is not performed (UP).

FIG. 2B shows a case where the output of the charge pump 7-1 is such that charging (UP) and discharging (DOWN) are performed at random. Charge pump 7-1
When charging and discharging are performed randomly, the loop filter 7-2 is constantly discharged by the constant current circuit 1-1, so that the output voltage (c) of the loop filter 7-2 decreases in the long term. And additional filter 1
-2 output voltage, ie, voltage controlled oscillator (VCO) 7-3
Also gradually decreases the control voltage (d).

In the case where the output of the charge pump 7-1 performs only discharging and does not perform charging, naturally,
The output voltage (c) of the loop filter 7-2 gradually decreases, and the output voltage of the additional filter 1-2, that is, the control voltage (d) of the voltage controlled oscillator (VCO) 7-3 also gradually decreases.

Therefore, in the case where the synchronous lock is lost as described above, the control voltage of the voltage controlled oscillator (VCO) is continuously reduced.
In the case where it is compared with a predetermined reference value Vref1 by -4 and it is detected that the reference value Vref1 or less, the phase lock loop oscillation circuit is determined to be out of synchronization, and an alarm (ALM) signal is output. Just do it.

Note that the reference value Vref1 does not need to be set to a precise value, and in the case of loss of synchronous lock, the control voltage of the voltage controlled oscillator (VCO) continues to drop, so that it always falls below a certain reference value. If the reference value Vref1 is a voltage equal to or lower than the control voltage at the time of synchronous locking, an appropriate voltage value may be set.

As described above, the first embodiment shown in FIG. 1 is a synchronous lock in which the output of the charge pump 7-1 is an output that performs only charging (UP) and does not perform discharging (DOWN). The off state cannot be detected because the control voltage of the voltage controlled oscillator (VCO) does not fall below the reference value Vref1.

Therefore, as in the second embodiment of the present invention shown in FIG. 3, a current is supplied to the capacitor C1 of the loop filter 7-2 in the same direction as the source current (charge current) of the charge pump 7-1. And a control voltage of a voltage controlled oscillator (VCO) is adjusted to a predetermined reference value Vre.
By providing the comparator 3-4 for detecting that f2 has been exceeded, it is possible to detect the synchronization unlock state in the above case.

In the second embodiment, the current is always supplied to the capacitor C1 of the loop filter 7-2 by the constant current circuit 3-1 contrary to the first embodiment. When the phase-locked loop oscillation circuit is locked normally,
A discharge current for discharging the current supplied by the constant current circuit 3-1 is supplied from the charge pump 7-1, and the output voltage of the loop filter 7-2 is reduced by the additional filter 1.
The voltage smoothed at -2 is kept constant.

However, when the phase-locked loop oscillation circuit is out of synchronous lock, the discharging operation is performed even though the current is continuously supplied to the capacitor C1 of the loop filter 7-2 by the constant current circuit 3-1. Is not performed, the output voltage of the loop filter 7-2 keeps increasing, and the control voltage of the voltage controlled oscillator (VCO) 7-3 increases.

Therefore, the rise of the control voltage of the voltage controlled oscillator (VCO) is determined by the comparator 3-4 to a predetermined reference value V.
When it is detected that the reference value Vref2 or more is obtained as compared with ref2, it is determined that the phase lock loop oscillation circuit is out of synchronization, and an alarm (ALM) signal may be output.

It is not necessary to similarly set a fine value for the reference value Vref2. In the case of the above-mentioned out-of-synchronization lock, the control voltage of the voltage controlled oscillator (VCO) keeps increasing, so that there is always a certain value. If the reference value Vref2 is equal to or higher than the control voltage at the time of synchronous locking, an appropriate voltage value may be set.

FIG. 4 shows a circuit configuration example of the constant current circuit. 3A shows the configuration of the constant current circuit used in the first embodiment shown in FIG. 1, and FIG. 3B shows the configuration of the second current circuit shown in FIG.
1 shows a configuration of a constant current circuit used in the embodiment. In this figure, VCC is the power supply voltage, (c) is the input point (c) of the loop filter 7-2 in FIGS. 1 and 3, and VDC is the bias voltage between the base and the emitter of the transistor Tr1. With this constant current circuit, the bias voltage VDC
/ A constant current of (resistance value R).

Charge pump 7-1 and loop filter 7
Care must be taken because adding a circuit to the connection point of -2 directly affects the characteristics of the entire phase locked loop oscillation circuit. FIG. 5 shows characteristics of the phase locked loop oscillation circuit. (A) of the figure shows general characteristics of the phase locked loop oscillation circuit, and (B) of the figure shows a change in operating point when the constant current circuit according to the present invention is added.

The horizontal axes of FIGS. 5A and 5B represent the phase difference between the output clock signal of the voltage controlled oscillator (VCO) and the reference signal, and the vertical axis represents the phase comparison with respect to the phase difference. Voltage controlled oscillator (VCO) output by the circuit after the circuit
Represents the control voltage. The ideal characteristic is that the phase difference and the control voltage have a linear relationship as shown by the solid line in the figure, but as the phase difference becomes smaller, a pulse having a small width according to the phase difference becomes However, since the voltage level does not reach a sufficiently high level due to propagation delay of the device, rounding of the waveform, etc., the control voltage output through the charge pump or the like does not output a very small voltage. The characteristics as shown in the figure, and a phase difference section called a dead zone occurs.

In this dead zone, even if the output frequency of the voltage controlled oscillator (VCO) fluctuates, the phase comparison circuit cannot output a control signal (phase difference correction signal) corresponding to the phase difference. The control voltage to the voltage controlled oscillator (VCO) does not change. As a result, jitter occurs in the output frequency of the voltage controlled oscillator (VCO).

On the other hand, according to the present invention, the addition of the constant current circuit allows the normal operating point in the steady state at the time of the synchronous lock to become the normal operation where the phase difference becomes zero as shown in FIG. Operating point (p) at which some steady phase error occurs
Go to The direction and magnitude of the stationary phase error can be arbitrarily set according to the current direction and current amount of the constant current circuit,
By setting the current direction and the current amount of the constant current circuit so that the steady state operating point (p) is outside the dead zone, it is possible to reduce the occurrence of jitter.

FIG. 6 shows a third embodiment of the present invention. In this embodiment, in order to select whether to set the occurrence of the steady-state phase error on the leading phase side or on the lagging phase side, the generation of the steady phase error is performed in both the current directions on the sink side and the source side of the charge pump. Corresponding constant current circuits are provided, and only one of them is selected and used. In either case, one out-of-synchronization detection circuit can detect out-of-synchronization. , Voltage controlled oscillator (VCO) by window comparator
Is monitored.

Since the configuration of the embodiment shown in FIG. 6 is basically a combination of the first and second embodiments shown in FIGS. 1 and 2, the configuration of the first and second embodiments is different. The same components are denoted by the same reference numerals, and redundant description will be omitted. However, only one of the two constant current circuits 1-1 and 3-1 is a loop filter 7-2.
Switches 6-1 and 6-2 so as to be connected to the input points of
Connect through.

The out-of-synchronization detecting circuit 6-3 constituted by a window comparator has a phase-locked loop oscillating circuit in an out-of-synchronization state.
When detecting that the control voltage of 7-3 is out of the voltage range between the reference voltages VH and VL, the circuit outputs an alarm (ALM) signal.

When the user appropriately sets the direction and magnitude of the stationary phase error, reference voltages VH and VL corresponding to the direction and magnitude of the stationary phase error are provided outside the window comparator. The setting can be performed by the reference voltage generator 6-4, and highly accurate out-of-synchronization detection corresponding to each circuit characteristic can be performed.

Further, when a clock signal synchronized with the received data is generated and used in a data receiving apparatus or the like which performs retiming of the received data with the clock signal, the magnitude and direction of the steady phase error should be appropriately set. Thus, it is possible to generate a clock signal having an optimal phase and perform retiming at the optimal phase.

[0058]

As described above, according to the present invention,
By connecting the constant current circuit to the smoothing filter connected to the charge pump, it is possible to reliably detect the loss of synchronization of the phase locked loop oscillator using a simple comparison circuit, and to output the signal from the phase comparison circuit. Loss of synchronization can be detected no matter what type of phase lock loop oscillation circuit is used as the control signal to the charge pump.

Also, by connecting a constant current circuit to the smoothing filter, it is possible to set an operating point avoiding a dead zone where a phase difference from the reference signal becomes a small phase difference becomes an operating point in a steady state. Thus, the occurrence of jitter can be reduced. To avoid the dead zone, a slight steady phase error will be generated. However, depending on the current amount and the current direction of the constant current circuit, the direction of the steady phase error (leading phase or lagging phase) and the phase error The amount can be set intentionally, and this can be used to properly adjust the steady-state phase error and perform the retiming process on the received data at the optimal phase.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an operation waveform timing chart of each unit of the first embodiment.

FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a diagram illustrating a circuit configuration example of a constant current circuit.

FIG. 5 is a diagram illustrating characteristics of a phase locked loop oscillation circuit.

FIG. 6 is a diagram illustrating a configuration of a third exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional phase locked loop oscillation circuit including an out-of-synchronization detection circuit.

FIG. 8 is a diagram showing an operation waveform timing chart of each part of the conventional phase locked loop oscillation circuit.

FIG. 9 is a diagram illustrating a configuration example of a PLL oscillation circuit that outputs a control signal having a pulse duty ratio according to a phase difference.

FIG. 10 is a diagram showing an operation waveform timing chart at the time of synchronous lock of a PLL oscillation circuit that outputs a control signal of a pulse duty ratio according to a phase difference.

FIG. 11 is a diagram showing an operation waveform timing chart of a PLL oscillation circuit that outputs a control signal of a pulse duty ratio according to a phase difference when an input clock is cut off.

[Explanation of symbols]

 1-1 Constant current circuit (DC current source) 1-2 Additional filter 1-3 Voltage follower 1-4 Comparator 7-1 Charge pump 7-2 Loop filter (low pass filter) 7-3 Voltage controlled oscillator (VCO)

Claims (4)

[Claims] 1. A charge pump to which a control signal corresponding to a phase difference from a reference signal is input, a smoothing filter controlled by the charge pump to charge and discharge, and a voltage output from the smoothing filter is input as a control voltage. A voltage-controlled oscillator, comprising: a constant current circuit connected in parallel to the charge pump with respect to the smoothing filter, wherein the constant current circuit is provided with respect to the smoothing filter. A phase-locked loop oscillation circuit, wherein a constant current is constantly supplied or sucked, and an output voltage of a smoothing filter to which the constant current is constantly supplied or sucked is added as a control voltage of the voltage controlled oscillator. 2. An out-of-synchronization detection circuit for detecting an out-of-synchronization of a phase-locked loop oscillator by comparing a control voltage output from the smoothing filter and applied to the voltage-controlled oscillator with a reference voltage. The phase locked loop oscillation circuit according to claim 1, further comprising: 3. A structure in which a constant current circuit that constantly supplies a constant current or a constant current circuit that constantly draws a constant current is connected to the smoothing filter. 3. The phase locked loop according to claim 2, further comprising a window comparator for comparing the control voltage with two reference voltages to detect that the control voltage is out of the range of the two reference voltages. Oscillator circuit. 4. A phase difference avoiding a dead zone in which a control voltage corresponding to the minute phase difference is not output in a section where the phase difference from the reference signal is minute is a steady phase error at the time of a synchronous lock operation. 4. The phase locked loop oscillation circuit according to claim 1, wherein an amount of current supplied or attracted by said constant current circuit is set.