JP2002305445A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent hang-ups of a PLL circuit generating an output signal, having the phase synchronized with an input signal, after turning the power on. SOLUTION: The PLL circuit comprises a voltage-controlled oscillator 40, a phase detector 10 for comparing the phase of a signal obtained, by multiplying the frequency of an output signal from the voltage controlled oscillator by 1/N fold (N is an integer of 1 or larger) with the phase of an input signal to produce a phase difference signal, a charge pump circuit 20 supplying a current based on the phase difference signal, a loop filter 30 being supplied with a current and generating a control voltage being applied to the voltage controlled oscillator, and a control means 60 for preventing hang-ups, by lowering the loop gain of the PLL circuit for a specified interval after a power supply voltage is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phase Locked Loop) circuit for generating an output signal whose phase is synchronized with an input signal.

[0002]

2. Description of the Related Art FIG. 16 shows the configuration of a general PLL circuit. This PLL circuit compares the phase of an input signal with the phase of a signal obtained by multiplying the frequency of an output signal of a VCO (voltage controlled oscillator) 40 by 1 / N (hereinafter referred to as a frequency-divided signal) to control a voltage of a control voltage. V _C is obtained, and VCO is calculated using the control voltage V _C.
By controlling 40, an output signal whose phase is synchronized with the input signal is generated. Here, N is an integer of 1 or more. When N is 1, the frequency of the input signal becomes equal to the frequency of the output signal. When N is 2 or more, the frequency of the input signal is divided by dividing the output signal by the frequency dividing circuit 50. A multiplied output signal is obtained.

A phase detector 10 compares the phases of an input signal and a frequency-divided signal. The phase difference signal output from the phase detector 10 is integrated by the charge pump circuit 20 and the loop filter 30. That is, the charge pump circuit 20, based on the phase difference signal outputted from the phase detector, by supplying a current I _OUT to the loop filter 30, the control voltage V _C for controlling the VCO40 is obtained. The loop filter 30 includes, for example, a resistor and a capacitor connected in series, and has a low-pass characteristic.

In such a PLL circuit, the output frequency of the VCO 40 may exceed the maximum input frequency of the frequency dividing circuit 50 depending on various conditions at the time of power-on. Then, the frequency dividing circuit 50 stops operating, and continuously outputs a high-level or low-level constant voltage. As a result, the phase detector 10 judges that the lower the output frequency of the VCO 40, the control voltage _{V C} to increase the output frequency of the VCO 40 is applied to the VCO 40. As a result, the PLL circuit keeps outputting a high-frequency output signal irrelevant to the input signal. Such a state is called a hang-up.

[0005] Even when a loop is formed without including the frequency dividing circuit 50, a similar situation occurs if the output frequency of the VCO 40 exceeds the maximum input frequency of the phase detector 10.

[0006]

SUMMARY OF THE INVENTION In view of the above, the present invention provides a PLL circuit that generates an output signal whose phase is synchronized with an input signal, and reliably prevents hang-up after power-on. Aim.

[0007]

In order to solve the above problems, a PLL circuit according to a first aspect of the present invention includes a voltage controlled oscillator for generating an output signal whose frequency changes according to a control voltage, and a voltage controlled oscillator. Output signal frequency 1 / N
A phase detector that compares the phase of a signal obtained by doubling (N is an integer of 1 or more) with the phase of an input signal, and outputs a phase difference signal corresponding to the phase difference between the signals, A charge pump circuit that supplies a current based on the phase difference signal, a loop filter that supplies a current from the charge pump circuit to generate a control voltage to be applied to a voltage controlled oscillator, and a predetermined period after a power supply voltage is supplied. , P
Control means for lowering the loop gain of the LL circuit to prevent hang-up.

According to the first aspect of the present invention, the control means performs control so as to reduce the loop gain during a predetermined period after the supply of the power supply voltage, thereby preventing a hang-up when the power is turned on. be able to.

Here, the control means may stop at least the operation of the charge pump circuit for a predetermined period after the supply of the power supply voltage. Or
The control means may stop at least the operations of the charge pump circuit and the voltage controlled oscillator for a predetermined period after the supply of the power supply voltage. Or, the control means, for a predetermined period after the power supply voltage is supplied,
The control voltage adjusting means may be controlled so as to reduce the absolute value of the control voltage.

The above-mentioned PLL circuit further includes an oscillator adjusting means for changing a voltage control gain which is a ratio of a change in a control voltage to a change in an oscillation frequency in the voltage controlled oscillator, wherein the control means is supplied with a power supply voltage. The oscillator adjusting means may be controlled so as to lower the voltage control gain in the voltage controlled oscillator for a predetermined period after that. Or, further comprising a charge pump adjusting means for changing the input / output gain in the charge pump circuit,
The control means may control the charge pump adjustment means so as to reduce the input / output gain in the charge pump circuit for a predetermined period after the supply of the power supply voltage.

A PLL circuit according to a second aspect of the present invention includes a voltage controlled oscillator for generating an output signal whose frequency changes in accordance with a control voltage, and a 1 / N multiplication of the frequency of the output signal of the voltage controlled oscillator. A signal selecting means for selecting one of the obtained signal (N is an integer of 1 or more) and an input signal; comparing the phase of the signal selected by the signal selecting means with the phase of the input signal; A phase detector that outputs a phase difference signal corresponding to the current, a charge pump circuit that supplies a current based on the phase difference signal output from the phase detector, and a current supplied from the charge pump circuit and applied to the voltage-controlled oscillator. And a control means for controlling the signal selection means so as to select an input signal during a predetermined period after the supply of the power supply voltage.

According to the second aspect of the present invention, the phase detector compares the same signal for a predetermined period after the supply of the power supply voltage, so that the control voltage does not increase.
It is possible to prevent a hang-up when the power is turned on.

Further, a PLL according to a third aspect of the present invention
The circuit inputs a voltage-controlled oscillator that generates an output signal whose frequency changes according to a control voltage, and a phase of a signal (N is an integer of 1 or more) obtained by multiplying the frequency of the output signal of the voltage-controlled oscillator by 1 / N. A phase detector that compares a phase of a signal and outputs a phase difference signal corresponding to the phase difference, a charge pump circuit that supplies current based on the phase difference signal output from the phase detector, and a charge pump circuit A loop filter that generates a control voltage to be applied to the voltage-controlled oscillator when current is supplied thereto, switch means for switching whether or not the input signal is supplied to the phase detector, and a power supply voltage. And control means for controlling the switch means so that the input signal is not supplied to the phase detector for a predetermined period after the start.

According to the third aspect of the present invention, since the input signal is not supplied to the phase detector for a predetermined period after the supply of the power supply voltage, the control voltage does not increase, and the hang-up at power-on is prevented. Can be prevented.

In the above PLL circuit, the control means includes:
The control signal may be activated for a predetermined period after the supply of the power supply voltage. Here, the control means includes:
The control signal may be activated as power is supplied. Further, the control means may count the input signal, and deactivate the control signal when the count value reaches a predetermined value.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same elements are denoted by the same reference numerals and description thereof is omitted. FIG. 1 shows a configuration of a PLL circuit according to the first embodiment of the present invention. This P
The LL circuit controls by comparing the phase of the input signal REF with the phase of a signal (hereinafter, referred to as a frequency-divided signal) FB obtained by multiplying the frequency of the output signal of the VCO (voltage controlled oscillator) 40 by 1 / N. obtains a voltage _{V C,} VCO using the control voltage _{V C}
By controlling 40, an output signal whose phase is synchronized with the input signal is generated. Here, N is an integer of 1 or more. When N is 1, the frequency of the input signal is equal to the frequency of the output signal, and when N is 2 or more, an output signal obtained by multiplying the frequency of the input signal is obtained. As the input signal, for example, a reference clock signal is used.

[0017] VCO40 oscillates at a frequency according to the control voltage V _C to be applied, and outputs the signal obtained by the oscillation as an output signal. The frequency dividing circuit 50 divides the frequency of the output signal of the VCO 40 by 1 / N to generate a frequency divided signal FB. In a case where the frequency of the input signal is always equal to the frequency of the output signal, the frequency dividing circuit 50
Is unnecessary. The phase comparator 10 compares the phase of the input signal REF with the phase of the frequency-divided signal FB, and outputs a phase difference signal corresponding to the phase difference. The phase difference signal output from the phase detector 10 is integrated by the charge pump circuit 20 and the loop filter 30.

The charge pump circuit 20 includes the phase detector 1
The current I _OUT is supplied to the loop filter 30 based on the phase difference signal output from 0. Loop filter 30
Includes a resistor and a capacitor connected in series, and has a low-pass characteristic. In the loop filter 30,
By converting the current _{I OUT} supplied from the charge pump circuit 20 to the voltage, the control voltage _{V C} for controlling the VCO40 is obtained.

On the other hand, the input signal REF is also supplied to the timer 60. When the first power supply voltage V _DD1 is supplied, the timer 60 outputs a high-level control signal PD and starts counting the input signal REF. In the meantime, the second power supply voltage V _DD2 is supplied to the phase detector 10, the charge pump circuit 20, the VCO 40, and the frequency dividing circuit 50.

The control signal PD is supplied to at least the charge pump circuit 20 to control the operation of the charge pump circuit 20. In the present embodiment, the operation of the charge pump circuit 20 stops while the control signal PD is at the high level. Incidentally, as shown in FIG.
Also, the control signal PD may be supplied to the frequency dividing circuit 50.

In the timer 60, the second power supply voltage V
_The count value is set to be a predetermined value after DD2 has sufficiently risen. When the count value reaches a predetermined value, the timer 60 sets the control signal PD to low level. Thereby, the charge pump circuit 20 and the VCO 4
0 starts operation and the entire PLL circuit works. Since the charge pump circuit 20 was not operating during the period when the control signal PD was at the high level, the VCO 40
The control voltage V _C of has a low value, VCO 40 is due to the low oscillation frequencies starts operating, hang-up is avoided.

As described above, the timer 60 functions as control means for preventing a hang-up by reducing the loop gain of the PLL circuit during a predetermined period after the supply of the power supply voltage. Note that a signal that is at a low level for a predetermined period after power-on and then changes to a high level may be used as the control signal.

FIG. 2 shows a configuration of the charge pump circuit in the PLL circuit according to the present embodiment. The up pulse signal UP bar low level from the phase detector is supplied, to increase the output current I _OUT current flows through the P-channel transistor QP11. On the other hand, when the high-level down pulse signal DN is supplied from the phase detector, a current flows through the N-channel transistor QN11 and the output current I
_OUT is reduced. P-channel transistor QP12
N-channel transistor QN12 and the bias voltage _{B P} and _{B N} gate is applied respectively to supply the current to the transistors QP11 and QN11.

In a predetermined period after the power is turned on, a signal PD bar obtained by inverting the control signal PD (hereinafter referred to as a control signal PD)
) Is at a low level, the P-channel transistor QP13 is turned on, and the transistor QP1
Cut off 2. In this period, the control signal PD is at the high level, the N-channel transistor QN13 is turned on, and the transistor QN12
Cut off. Accordingly, during this period, the output of the charge pump circuit 20 is in a high impedance state, and even if the up pulse signal UP is input, the control voltage V
_C does not increase.

FIG. 3 shows the timing of each signal in the PLL circuit according to the present embodiment. First power supply voltage V _DD
When 1 rises, the timer 60 outputs a high-level control signal PD and starts counting the input signal REF. After the second power supply voltage V _DD2 has sufficiently risen,
The count value reaches a predetermined value, and the control signal PD goes low.

While the control signal PD is at the high level, the VCO 40 and the frequency dividing circuit 50 do not operate, so that the frequency divided signal FB is not supplied. On the other hand, the input signal REF is supplied. In this state, even if the phase detector 10 starts operating and outputs the up-pulse signal UP, the charge pump circuit 20 does not operate while the control signal PD is at the high level. V _C does not increase. When the control signal PD is at a low level, the charge pump circuit 20 starts to operate, the control voltage V _C is generated in accordance with the up pulse signal UP and the down pulse signal DN. In this way, the control voltage V
_{Since C} does not increase, hang-up can be prevented.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a PLL circuit according to the present embodiment.
In this embodiment, the control signal PD output from the timer 60, by supplying the control voltage adjustment circuit (N-channel transistors QN20), to vary the control voltage _{V C} applied to the VCO 40. That is, in the predetermined period after the power is turned on, the control signal PD goes high, transistor QN20 is turned on, the control voltage V _C is dropped to the ground potential. Thereby, hang-up can be prevented. According to the present embodiment, the charge pump circuit 20 starts operating before the control signal PD becomes low level, so that the pull-in time of the PLL circuit can be shorter than that of the first embodiment.

Next, a third embodiment of the present invention will be described. FIG. 5 shows a PLL circuit according to the present embodiment.
In the present embodiment, by supplying the control signal PD output from the timer 60 to the oscillator adjustment circuit 70,
The voltage control gain, which is the ratio between the change in the control voltage and the change in the oscillation frequency in the VCO 41, is changed.

FIG. 6 shows the VCO 41 and the oscillator adjusting circuit 7.
0 is shown. The VCO 41 includes an inverter circuit INV
Are connected in series in an odd number of stages to form a ring oscillator. Each of the inverter circuits INV includes a complementary-connected P-channel transistor QP31 and an N-channel transistor QN31. The drain current is supplied from the oscillator adjusting circuit 70 to the transistor of each inverter circuit INV.

The control voltage _{V C} is applied to the gate of N-channel transistors QN32, accordingly, current flows through the series connected transistors QP32 and QN32. P-channel transistors QP32 and QP33 form a current mirror, and a current substantially the same as the current flowing through transistor QP32 also flows through transistor QP33. Similarly, the P-channel transistors QP32 and QP34 also constitute a current mirror, but since the transistor QP35 is connected in series to the transistor QP34, the control signal PD applied to the gate of the transistor QP35 goes low. Only when
A current flows through transistor QP34.

The currents flowing through the transistors QP33 and QP34 are added and supplied to the transistors QP31 and QN31 of the inverter circuit INV. The higher the drain current of the transistors QP31 and QN31, the higher the speed of the operation of the inverter circuit INV, and thus the higher the oscillation frequency of the ring oscillator. Therefore, when the control signal PD becomes low level, the oscillation frequency of the ring oscillator becomes higher, and the ratio between the change of the control voltage and the change of the oscillation frequency (voltage control gain) also becomes larger.

FIG. 7 shows a control voltage V _C in the VCO 41.
And the relationship between the oscillation frequency f. In a predetermined period after the power is turned on, the control signal PD becomes high level and the voltage control gain is small, but after this period, the control signal PD becomes low level and the voltage control gain becomes large.
When the control signal PD is at a high level, when the control voltage _{V C} rises to the supply voltage _{V DD,} the oscillation frequency of the VCO41 is the frequency _{f OS C.} This frequency f
If various conditions are set so that the _OSC is lower than the maximum operable input frequency f _{DIV of the} frequency _dividing circuit 50 (see FIG. 5), it is possible to prevent a hang-up caused by the frequency _dividing circuit not operating. Can be.

When a loop is formed without including the frequency divider, various conditions are set so that the frequency f _OSC becomes lower than the maximum input frequency at which the phase detector 10 (see FIG. 5) can operate. If it is set, it is possible to prevent a hang-up due to the inactivity of the phase detector.

Next, a fourth embodiment of the present invention will be described. FIG. 8 shows a PLL circuit according to the present embodiment.
In the present embodiment, the control signal PD output from the timer 60 is supplied to the charge pump adjustment circuit 80 to change the input / output gain in the charge pump circuit 21.

FIG. 9 shows the configuration of the charge pump circuit 21 and the charge pump adjustment circuit 80. The up pulse signal UP bar low level from the phase detector is supplied, to increase the output current I _OUT current flows through the P-channel transistor QP41. On the other hand, when the high-level down pulse signal DN is supplied from the phase detector, a current flows through the N-channel transistor QN41 and the output current I
_OUT is reduced. P-channel transistor QP42
And N-channel transistors QN42 bias voltage _{B P} and _{B N} gate is applied respectively, for supplying a drain current to the transistor QP41 and QN41.

During a predetermined period from power-on, the control signal PD is at the high level, and the P-channel transistor QP44 and the N-channel transistor QN44 are cut off.
Channel transistor QN43 does not function. After this period, when the control signal PD goes low, the transistor QP44 turns on and the transistor QP44 turns on.
The transistor QP43 is connected in parallel to P42. Similarly, when the control signal PD goes high, the transistor QN44 turns on and the transistor QN4
2, the transistor QN43 is connected in parallel. Therefore,
When the control signal PD goes low, the transistor QP
The drain currents of the charge pump circuit 41 and the QN 41 increase, and the input / output gain of the charge pump circuit 21 increases.

[0037] Figure 10, control the up pulse signal UP bar waveform input to the charge pump circuit 21 voltage _{V C}
Shows the change in During a predetermined period after the power is turned on, the control signal PD becomes high level and the input / output gain is small, but after this period, the control signal PD becomes low level and the input / output gain increases. Accordingly, in a predetermined period after the power-on, since no control voltage V _C varies greatly, it is possible to prevent the hanging up.

Next, a fifth embodiment of the present invention will be described. FIG. 11 shows a PLL circuit according to the present embodiment. In the present embodiment, by supplying the control signal PD bar output from the timer 60 to the selection circuit 90, one of the frequency-divided signal FB and the input signal REF is selected and supplied to the phase comparator 10. . When a loop is formed without using the frequency dividing circuit 50, the selecting circuit 90
Selects one of the output signal OUT and the input signal REF and supplies it to the phase comparator 10.

FIG. 12 shows the timing of each signal in the PLL circuit according to the present embodiment. Here, the dividing ratio N
Is described as 1. After power-on, the timer outputs a low-level control signal PD bar and starts counting the input signal REF. After the power supply voltage _VDD has sufficiently risen, the count value reaches a predetermined value, and the control signal PD goes high.

In a predetermined period after the power is turned on, the control signal PD is at a low level, and the selection circuit selects the input signal REF and outputs it as the selection signal SL. Therefore, since the phase comparator 10 compares the same signal, neither the up pulse signal nor the down pulse signal is output. After a lapse of a predetermined period, the control signal PD goes high, and the selection circuit selects the output signal OUT and outputs it as the selection signal SL. Therefore, the phase comparator 10 outputs an up pulse signal UP corresponding to the phase difference between the input signal REF and the output signal OUT, control voltage V _C is increased. Thus, since there is no increase the control voltage V _C is while the control signal PD is at high level, it is possible to prevent a hang-up.

Next, a sixth embodiment of the present invention will be described. FIG. 13 shows a PLL circuit according to the present embodiment. In the present embodiment, by supplying the control signal PD bar output from the timer 60 to the switch circuit 100, it is switched whether or not to supply the input signal REF to the phase detector 10.

FIG. 14 shows a specific connection example of the switch circuit and the timer in the PLL circuit according to the present embodiment. An input signal REF is input to one input of the AND circuit 110.
Is supplied, and the control signal PD bar is supplied to the other input. Therefore, the AND circuit 110 outputs the input signal REF to the phase detector 1 when the control signal PD is at the high level.
Supply 0.

FIG. 15 shows the timing of each signal in the PLL circuit according to the present embodiment. After the power is turned on, the timer 60 outputs a low-level control signal PD bar and starts counting the input signal REF. After the power supply voltage _VDD has sufficiently risen, the count value reaches a predetermined value, and the control signal PD goes high.

The control signal PD bar is at a low level.
During this time, the output signal SW of the AND circuit 110 is also at the low level.
It has become. Therefore, even if the phase comparator 10
Even if the frequency-divided signal FB is not supplied, the up-pulse signal
There is no output. Control signal PD bar is high level
, The output signal SW of the AND circuit 110 becomes the divided signal.
No. FB. Therefore, the phase comparator 10 receives the input
Up according to the phase difference between signal REF and output signal OUT
A pulse signal UP is output and the control voltage V_CIncrease. This
, The control signal PD bar is at the low level.
Control voltage V _CDoes not increase, preventing hang-up
Can be stopped.

[0045]

As described above, according to the present invention, in a PLL circuit that generates an output signal whose phase is synchronized with an input signal, hang-up after power-on can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a charge pump circuit in the PLL circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing the timing of each signal in the PLL circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a PLL circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a PLL circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a configuration of a VCO and an oscillator adjustment circuit in a PLL circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram illustrating a relationship between a control voltage and an oscillation frequency in the VCO of FIG. 6;

FIG. 8 is a block diagram illustrating a configuration of a PLL circuit according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing configurations of a charge pump circuit and a charge pump adjustment circuit in a PLL circuit according to a fourth embodiment of the present invention.

10 is a diagram showing a waveform of an up-pulse signal input to the charge pump circuit of FIG. 9 and a change in control voltage.

FIG. 11 is a block diagram illustrating a configuration of a PLL circuit according to a fifth embodiment of the present invention.

FIG. 12 is a timing chart illustrating timings of signals in a PLL circuit according to a fifth embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a PLL circuit according to a sixth embodiment of the present invention.

FIG. 14 is a diagram illustrating a specific connection example of a switch circuit and a timer in a PLL circuit according to a sixth embodiment of the present invention.

FIG. 15 is a timing chart showing the timing of each signal in a PLL circuit according to a sixth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Phase detector 20, 21 Charge pump circuit 30 Loop filter 40, 41 VCO 50 Divider circuit 60 Timer 70 Oscillator adjustment circuit 80 Charge pump adjustment circuit 90 Selection circuit 100 Switch circuit 110 AND circuit QP11-QP44 P-channel transistor QN11-QN44 N-channel transistor INV Inverter circuit

Claims (11)

[Claims] 1. A PLL circuit that generates an output signal whose phase is synchronized with an input signal, comprising: a voltage-controlled oscillator that generates an output signal whose frequency changes according to a control voltage; A phase detector that compares the phase of a signal obtained by multiplying 1 / N (N is an integer of 1 or more) with the phase of the input signal, and outputs a phase difference signal according to the phase difference between the signals; A charge pump circuit that supplies a current based on a phase difference signal output from the device; a loop filter that receives a current from the charge pump circuit to generate a control voltage to be applied to the voltage-controlled oscillator; After a predetermined period of time,
Control means for reducing the loop gain of the LL circuit to prevent hang-up. 2. The PLL circuit according to claim 1, wherein said control means stops at least an operation of said charge pump circuit for a predetermined period after supply of a power supply voltage. 3. The PLL circuit according to claim 1, wherein said control means stops at least operations of said charge pump circuit and said voltage controlled oscillator for a predetermined period after a power supply voltage is supplied. 4. A control voltage adjusting means for changing a control voltage generated in the loop filter, wherein the control means controls the control voltage generated in the loop filter for a predetermined period after a power supply voltage is supplied. 2. The PLL circuit according to claim 1, wherein said control voltage adjusting means is controlled so as to reduce the absolute value of the control voltage. 5. An oscillator adjusting means for changing a voltage control gain, which is a ratio of a change in a control voltage to a change in an oscillation frequency in the voltage controlled oscillator, wherein the control means operates after a power supply voltage is supplied. 2. The PLL circuit according to claim 1, wherein said oscillator adjusting means is controlled to reduce a voltage control gain in said voltage controlled oscillator during a predetermined period. 6. The input / output gain of the charge pump circuit according to claim 1, further comprising charge pump adjusting means for changing an input / output gain in the charge pump circuit, wherein the control means controls the input / output gain in the charge pump circuit for a predetermined period after a power supply voltage is supplied. 2. The PLL circuit according to claim 1, wherein the charge pump adjusting means is controlled so as to reduce the voltage. 7. A PLL circuit for generating an output signal whose phase is synchronized with an input signal, comprising: a voltage-controlled oscillator for generating an output signal whose frequency varies according to a control voltage; Signal selection means for selecting one of a signal obtained by multiplying by 1 / N (N is an integer of 1 or more) and the input signal; and a phase of the signal selected by the signal selection means, A phase detector that compares a phase and outputs a phase difference signal according to the phase difference, a charge pump circuit that supplies a current based on the phase difference signal output from the phase detector, and the charge pump circuit And a loop filter that generates a control voltage to be applied to the voltage-controlled oscillator when a current is supplied from the power supply voltage generator, and selects the input signal during a predetermined period after the power supply voltage is supplied. And a control means for controlling the signal selection means. 8. A PLL circuit for generating an output signal whose phase is synchronized with an input signal, comprising: a voltage-controlled oscillator for generating an output signal whose frequency changes according to a control voltage; A phase detector that compares the phase of a signal obtained by multiplying 1 / N (N is an integer of 1 or more) with the phase of the input signal, and outputs a phase difference signal according to the phase difference between the signals; A charge pump circuit that supplies a current based on the phase difference signal output from the device; a loop filter that receives a current from the charge pump circuit and generates a control voltage to be applied to the voltage controlled oscillator; Switch means for switching whether or not to apply the input signal to the phase detector; and for a predetermined period after the power supply voltage is supplied, the input signal is supplied to the phase detector. Control means for controlling the switch means so as not to supply to the phase detector. 9. The PLL circuit according to claim 1, wherein said control means activates a control signal for a predetermined period after a power supply voltage is supplied. 10. The PLL circuit according to claim 9, wherein said control means activates said control signal as power is supplied. 11. The control unit according to claim 9, wherein the control unit counts the input signal, and deactivates the control signal when the count value reaches a predetermined value.
The PLL circuit as described in the above.