JP2002110959A - Solid-state imaging device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device where the increase of resistance of wiring between picture elements can be restrained, while the aperture area of a light-receiving part is secured as large as possible, and to provide a method for manufacturing the device. SOLUTION: This manufacturing method of a solid-state imaging device, the light-receiving part and a transfer region are formed in a substrate includes a plurality of transfer electrodes, to which a transfer voltage of a prescribed clock is applied when charges formed in the light receiving part and swept out to the transfer region are transferred in a prescribed direction, and wirings between electrodes which connects parts between the transfer electrodes and applies a transfer voltage to a plurality of the transfer electrodes are formed on the substrate and a forming process of the transfer electrodes and the wiring between electrodes consists of a process for forming a conducting film turning to the transfer electrodes and the wiring on the substrate, a process for forming an oxidation restraining film on the conducting film, a process for patterning the oxidation restraining film and the conducting film in patterns of the transfer electrodes and the wiring, and a process for forming an oxide film 34 in a side part of the conducting film by oxidizing the conducting film 11a'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CCD (Charge C)
The present invention relates to a solid-state imaging device such as an Oupled Device and a method of manufacturing the same, and more particularly to a solid-state imaging device compatible with miniaturization of a pixel size and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, there is a strong demand for a CCD solid-state imaging device to have a small chip size and a large number of pixels.

However, if the chip is miniaturized with the current pixel size, the number of pixels is reduced and the resolution is reduced. Further, if the number of pixels is increased without changing the current pixel size, the chip size becomes large, which causes an increase in production cost and a decrease in yield. Therefore, in order to realize a smaller chip size and a larger number of pixels, it is necessary to reduce the pixel size from the current state. This makes it possible to reduce the chip size while maintaining the resolution, or increase the number of pixels without increasing the chip size.

FIG. 2 is a plan view of a pixel portion of a CCD solid-state imaging device. As shown in FIG. 2, a light receiving portion 5 for performing photoelectric conversion, a transfer channel region 7a in which a transfer channel for transferring signal charges in a vertical transfer portion is formed, and a channel stopper forming region (channel stopper region) 9a are formed. ing.

The plurality of first pixels connected to the first inter-pixel wiring lines (10a, 10b) are orthogonal to the transfer channel region 7a.
Of vertical transfer electrodes (10A, 10B) are formed, and these first vertical transfer electrodes (10A, 10B) are alternately arranged in the column direction.

The first vertical transfer electrodes (10A, 10A)
On B), a plurality of second vertical transfer electrodes (11A, 11B) connected to the second inter-pixel wirings (11a, 11b) are formed orthogonally to the transfer channel region 7a. Of vertical transfer electrodes (11A, 11B) are alternately arranged in the column direction.

The first vertical transfer electrodes (10A, 10B) and the first inter-pixel wirings (10a, 10b) are made of the same material on the same level, for example, a first polysilicon layer. ing. Further, the second vertical transfer electrodes (11A, 11B) and the second inter-pixel wiring (11a,
11b) is also formed of the same material of the same layer, and is formed of, for example, a second polysilicon layer laminated on the first polysilicon layer with an insulating film interposed therebetween.

The reduction of the pixel size is achieved by the light receiving unit 5 shown in FIG.
Means that the width of the opening, the width of the transfer channel region 7a, and the width of the inter-pixel wiring (10a, 10b, 11a, 11b) also need to be reduced in accordance with the reduction in the pixel size.

When the pixel size is reduced, the amount of light incident per unit area does not change, so that the sensitivity always decreases. In particular, the sensitivity of the imaging lens of the camera equipped with the CCD imaging device is significantly reduced on the open-aperture side (the side where the F value is small) where the aperture is opened. Therefore, efforts have been made to increase the aperture area of the light receiving unit 5 as much as possible to improve the light collecting state.

For example, the opening area of the light receiving portion 5 is increased by changing the width of the transfer channel region 7a or the wiring between pixels (10a, 10a).
b, 11a, 11b). When the width of the transfer channel region 7a is reduced in this manner, there is a problem that the amount of charges handled in the transfer channel is reduced. However, measures are taken by increasing the potential of the transfer channel and improving the conversion efficiency. Further, for example, in order to compensate for a decrease in sensitivity due to a reduction in pixel size, a method of improving conversion efficiency (an index of how many volts one electron can be converted by an output circuit) has been adopted.

FIG. 16 is a sectional view taken along the line AA 'in FIG. As shown in FIG. 16, a p-type silicon substrate or a p-type well (hereinafter referred to as a substrate) 20 formed in the silicon substrate is formed of, for example, an n-type impurity region and has a pn junction between the substrate 20 and the center. The light receiving unit 5 is configured to generate a signal charge by performing photoelectric conversion in the region described above, and accumulate the signal charge for a certain period of time. Further, a channel stopper 9 made of a high-concentration p-type impurity region is formed between the light receiving sections 5 to a deep portion of the substrate 20. The channel stopper 9 is formed on a lattice surrounding the light receiving unit 5 in FIG.

On the substrate 20, a first inter-pixel wiring 10a is provided.
And the second inter-pixel wiring 11a are stacked in a state where they are insulated from each other by an insulating film 30 such as silicon oxide. Further, a light-shielding film 40 made of a metal such as aluminum or tungsten is formed on the second inter-pixel wiring 11a with the insulating film 30 interposed therebetween. Light shielding film 4
0 is open above the light receiving unit 5.

Although not shown, a light-shielding film 40 and an insulating film 30 are coated on the entire surface, for example, PSG (Phospho).
silicate glass), BPSG (Borophosphosilicate gla
ss), an interlayer insulating film made of silicon oxide, silicon nitride, or the like is formed, and the surface of the interlayer insulating film is planarized. The interlayer insulating film may be a laminate of insulating films made of the above materials. An on-chip color filter (OCC) is formed on the flattened surface of the interlayer insulating film.
F), and an on-chip lens (OCL) made of a light transmitting material such as a negative photosensitive resin is arranged on the OCCF. Light received by the lens surface (convex curved surface) of the OCL is collected, a specific wavelength region is selected by the OCCF, and is incident on the light receiving unit 5.

Next, a method of manufacturing the CCD image pickup device will be described, focusing on a method of manufacturing vertical transfer electrodes and inter-pixel wiring. First, steps up to a step shown in FIG. According to a known method, various impurity regions are formed in predetermined portions of the silicon substrate 20 shown in FIG. That is, in the silicon substrate 20, for example, a p-type impurity region is ion-implanted at a high concentration to form the channel stopper 9, and, for example, an n-type impurity is ion-implanted under predetermined conditions to form the light receiving section 5, and the n-type impurity is formed. Impurity ions are implanted under predetermined conditions to form a transfer channel. For example, a p-type impurity is ion-implanted under predetermined conditions to form a read gate portion. Then, a thermal oxidation method or a CVD (Chemical Vapor Depositio) is formed on the surface of the substrate 20 on which the various impurity regions are formed.
An insulating film 31 made of silicon oxide or the like is formed by the method n). On the insulating film 31, a first polysilicon layer doped with impurities and having increased conductivity is deposited by a CVD method.
The polysilicon layer is patterned to form another first inter-pixel wiring and a first vertical transfer electrode in a region (not shown) together with the first inter-pixel wiring 10a shown in FIG. Then, an insulating film 32 made of silicon oxide is formed on the first inter-pixel wiring and the first vertical transfer electrode by a thermal oxidation method.

Next, as shown in FIG. 17B, polysilicon is deposited on the insulating films (31, 32) by a CVD method, for example, phosphorus is diffused into the polysilicon, and impurities are added. Thus, a second polysilicon layer 11 having increased conductivity is formed.

Next, as shown in FIG. 17C, a resist is applied, and a resist film R having a pattern of a second inter-pixel wiring and a second vertical transfer electrode is formed by a photolithography process.

Next, as shown in FIG. 18D, the second polysilicon layer 11 is subjected to, for example, a dry etching method to form a second vertical transfer electrode in a second inter-pixel wiring 11a 'and a region (not shown). And another second inter-pixel wiring (hereinafter referred to as a second inter-pixel wiring and the like).
After that, the resist film R is removed.

Next, as shown in FIG. 18E, the second inter-pixel wiring 11a 'and the like are oxidized to form a silicon oxide film 34.
To form By the oxidation step, the second inter-pixel wiring 1 is formed.
1a and the like are formed. At this time, the second inter-pixel wiring 11a 'and the like are oxidized in the horizontal and vertical directions, so that the cross-sectional area is reduced.

Next, as shown in FIG. 18 (f), in order to secure a withstand voltage between the second inter-pixel wiring and the like and a light shielding film to be formed later and to reduce a parasitic capacitance, silicon oxide is applied to the entire surface by, for example, a CVD method. Deposit. In the figure, the insulating film 31, the insulating film 32, and the insulating film 34 after the silicon oxide film is deposited are shown.
Is shown as an insulating film 30.

As a subsequent step, on the insulating film 30,
For example, a metal film such as tungsten or aluminum is deposited by a sputtering method or a CVD method, and is patterned so as to be opened above the light receiving portion 5 to form a light shielding film 40, so that the CCD imaging device shown in FIG. Can be formed.

In the above-mentioned conventional method for manufacturing a CCD image pickup device, when discussing the wiring between pixels, FIG.
In the oxidation step shown in FIG. 8 (e), the initial second inter-pixel wiring 11a 'is oxidized, so that the second inter-pixel wiring 11a' is compared with immediately after the patterning of the second polysilicon layer 11 by etching. It is necessary to take into consideration that the cross-sectional area becomes smaller. This oxidation step is provided to improve the withstand voltage between the transfer electrode and the inter-pixel wiring, and between the light-shielding film. The silicon oxide film formed by the CVD method for reducing the parasitic capacitance only has a high withstand voltage. This is an indispensable step because it is insufficient.

In the cross-sectional analysis by the SEM, the oxidation process performed after the etching of the second polysilicon layer 11
It has been confirmed that about 20% of the initial thickness of the second polysilicon layer 11 is reduced by oxidation. For example,
When the thickness and width of the second inter-pixel wiring 11a ′ immediately after patterning by etching of the second polysilicon layer 11 are 0.5 μm and 1.0 μm, respectively, the second oxidation Inter-pixel wiring 11
The thickness and width of a are finally 0.4 μm and 0.8 μm.
m. When the cross-sectional area is calculated, the second inter-pixel wiring 11
a is 64 of the initial second inter-pixel wiring 11a 'due to oxidation.
%. Therefore, when the inter-pixel wiring width is reduced in order to reduce the pixel size and the opening area, not only the wiring resistance is increased, but in an extreme case, the second inter-pixel wiring is disconnected in the oxidation step. In some cases, it will.

As shown in FIG. 19, the imaging unit (effective unit) 2
When the transfer clock φV1 is applied from, for example, the electrode pad 14a among the electrode pads 14 formed around the
The transfer clock φV1 is applied to the vertical transfer electrode 11A through the clock wiring layer 12a. At this time, if the resistance of the inter-pixel wiring is high, the transfer clock φV1 applied from both ends is close to the clock wiring layer 12a. In the part A, the waveform is close to the input waveform as shown in FIG. 20A, but as the distance from the clock wiring layer 12a increases, for example, in the part B, as shown in FIG. Becomes dull, and the center part C of the chip
Then, as shown in FIG. 20C, the clock waveform becomes further dull, and the amplitude of the applied voltage decreases.

Due to the above-mentioned problem of the propagation delay, for example, the maximum amount of charge handled in the transfer channel is reduced, the charge transfer in the transfer channel is deteriorated, or the read gate from the light receiving section 5 to the transfer channel is used. At the time of reading the charges, the amplitude of the read voltage applied to the vertical transfer electrode becomes small, so that there is a problem that the signal charges from the light receiving section to the transfer channel cannot be completely read.

In order to solve these problems, the following measures are generally taken. For example, FIG.
By depositing the second polysilicon layer 11 having a larger thickness in the step (b), the second polysilicon layer 11 having a larger thickness than the structure shown in FIG. 16 as shown in FIG. Inter-pixel wirings (11a, 11b) are formed to increase the cross-sectional area of the inter-pixel wiring to suppress an increase in wiring resistance. Also,
In the step shown in FIG. 18F, a silicon oxide film having a larger thickness is deposited by the CVD method, so that the transfer electrode and the pixel are formed as compared with the structure shown in FIG. 16 as shown in FIG. By thickening the insulating film 30 on the inter-wiring,
The parasitic capacitance with the metal light-shielding film 40, which is normally grounded to 0V, is reduced, and the dullness of the transfer clock waveform is suppressed.

[0026]

However, FIG.
As shown in (a), the second inter-pixel wiring 1 having a large film thickness
When 1a and the like are formed, the height of the on-chip lens is increased in spite of the reduced pixel size, so that the position of the on-chip lens is increased, and the condensing state of incident light is deteriorated. In particular, the sensitivity of the image pickup lens of the camera equipped with the CCD image pickup device on the aperture open side (the side where the F value is small) where the aperture is opened is significantly reduced. Therefore, in the case where the pixel size is reduced, the thickness of the second inter-pixel wiring 11a is currently increased to the extent that deterioration in characteristics such as sensitivity reduction can be tolerated.

As shown in FIG. 21B, when the thickness of the insulating film 30 on the transfer electrode and the inter-pixel wiring is increased, the distance between the silicon substrate 20 and the light-shielding film 40 on the light receiving section 5 increases. The oblique light is applied to the silicon substrate 20 and the light shielding film 4.
After multiple reflection occurs between 0, the light is likely to enter the transfer channel, so that the smear characteristics deteriorate. Therefore, as long as the smear characteristic is barely acceptable, the insulating film 3
At present, the film thickness of 0 is increased.

As described above, under the current situation where a reduction in chip size and an increase in the number of pixels are strongly desired, it is necessary to keep the opening area of the light receiving section 5 as much as possible while suppressing an increase in the resistance of the inter-pixel wiring. The situation was very difficult, and new technology was strongly desired.

The present invention has been made in view of the above-mentioned problems. Accordingly, the present invention provides a solid-state device capable of suppressing an increase in resistance of the inter-pixel wiring while securing the opening area of the light receiving portion as much as possible. It is an object to provide an imaging device and a method for manufacturing the same.

[0030]

In order to achieve the above object, a method of manufacturing a solid-state imaging device according to the present invention comprises forming a light receiving section and a transfer area on a substrate, and sweeping the transfer area generated by the light receiving section. A plurality of transfer electrodes to which a transfer voltage of a predetermined clock is applied when transferring the discharged charges in a predetermined direction, and between electrodes connecting between transfer electrodes for applying the transfer voltage to the plurality of transfer electrodes A method for manufacturing a solid-state imaging device in which wiring is formed on a substrate, wherein, in the step of forming the transfer electrode and the inter-electrode wiring, a step of forming a conductive film to be the transfer electrode and the inter-electrode wiring on the substrate Forming an oxidation suppression film on the conductive film, patterning the oxidation suppression film and the conductive film into a pattern of the transfer electrode and the inter-electrode wiring, and oxidizing the conductive film. And a step of forming an oxide film on the conductive film side Te.

For example, prior to the step of forming a conductive film on the substrate, a step of forming a lower conductive film to be a lower transfer electrode and a wiring between lower electrodes on the substrate; Patterning an electrode and a pattern of the lower inter-electrode wiring; and oxidizing the lower conductive film to form a lower oxide film on the lower conductive film, forming a conductive film on the substrate. Forming a conductive film on the substrate and the lower oxide film.

Further, after the step of oxidizing the conductive film,
Forming a light-shielding film covering at least the oxidation suppressing film and the oxide film;

For example, in the step of forming a conductive film on the substrate, a conductive film containing polycrystalline silicon is formed on the substrate.

For example, in the step of forming an oxidation suppressing film on the conductive film, an oxidation suppressing film containing silicon oxide is formed on the conductive film.

For example, in the step of forming an oxidation suppressing film on the conductive film, an oxidation suppressing film containing silicon nitride is formed on the conductive film.

For example, in the step of forming an oxidation suppressing film on the conductive film, the oxidation suppressing film is formed of a multilayer film. For example, the oxidation suppression film is formed of a multilayer film including a silicon oxide film and a silicon nitride film.

According to the present invention, in the formation of the transfer electrode and the inter-electrode wiring, a conductive film to be the transfer electrode and the inter-electrode wiring is formed on the substrate, and the oxidation suppressing film is formed on the conductive film to form the oxidation suppressing film. The film and the conductive film are patterned into a pattern of a transfer electrode and an inter-electrode wiring, and the patterned conductive film is oxidized to form an oxide film on a side of the conductive film. As described above, after the formation of the oxidation suppressing film, the patterning of the transfer electrode and the wiring between the electrodes is performed, and the patterned conductive film is oxidized. Since the amount can be reduced to prevent the cross-sectional area of the conductive film from decreasing, the resistance of the inter-electrode wiring can be reduced. Therefore, it is possible to suppress the propagation delay caused by the decrease in the amplitude of the transfer voltage of the predetermined clock applied to the transfer electrode when transferring the charge generated in the light receiving unit and swept to the transfer region in the predetermined direction.

Further, in order to achieve the above object, a solid-state imaging device according to the present invention includes a light receiving section and a transfer area formed on a substrate, and a light receiving section and a transfer area formed on the substrate generated by the light receiving section. A plurality of transfer electrodes to which a transfer voltage of a predetermined clock is applied when transferring the swept charge in a predetermined direction, and a method for applying the transfer voltage to a plurality of the transfer electrodes formed on a substrate. Having an inter-electrode wiring connecting between the transfer electrodes, an oxidation suppressing film is formed on the conductive film to be the transfer electrode and the inter-electrode wiring, and an oxide film formed on a side portion of the conductive film, It is sufficiently thicker than the oxide film formed thereon.

According to the present invention described above, an oxidation suppressing film is formed on a conductive film to be a transfer electrode and an inter-electrode wiring,
The oxide film formed on the side of the conductive film is sufficiently thicker than the oxide film formed thereon. As described above, the oxidation suppression film formed over the conductive film can reduce the thickness of the oxide film over the conductive film as compared with the side portions, and can prevent a reduction in the cross-sectional area of the conductive film. In addition, the resistance of the inter-electrode wiring can be reduced. Therefore, it is possible to suppress the propagation delay caused by the decrease in the amplitude of the transfer voltage of the predetermined clock applied to the transfer electrode when transferring the charge generated in the light receiving unit and swept to the transfer region in the predetermined direction.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a solid-state imaging device and a manufacturing method according to the present invention will be described below with reference to the drawings, taking a CCD imaging device of an interline transfer system as an example.

First Embodiment FIG. 1 is a block diagram showing a main configuration of a CCD image pickup device according to this embodiment. This CCD imaging device 1
It has an imaging unit 2, a horizontal transfer unit 3, and an output unit 4. Output unit 4
Is, for example, a charge formed by a floating gate −
It has a voltage converter 4a.

The imaging section 2 includes a light receiving section 5 for performing photoelectric conversion,
Pixel 8 comprising read gate unit 6 and vertical transfer unit 7
Are arranged in the form of a planar matrix. Each pixel 8 is separated by a channel stopper (not shown) so as not to cause electrical interference.

The vertical transfer units 7 are shared for each column of the light receiving units 5 and are arranged in a predetermined number. A four-phase vertical transfer clock (φV1,
φV2, φV3, φV4) are input. Horizontal transfer unit 3
The two-phase horizontal transfer clock (φH1,
φH2) is input.

The horizontal transfer section 3 and the vertical transfer section 7 described above.
Are potential wells of minority carriers formed by introducing impurities into the surface side of a semiconductor substrate, and a plurality of electrodes (transfer electrodes) repeatedly formed on a substrate with an insulating film interposed therebetween insulated and separated from each other. It is composed of These transfer units (3, 7) have the transfer clocks (φV1, φV2, φV3, φV4,
Or φH1, φH2) are applied with their phases shifted periodically. The transfer units (3, 7) are controlled by the transfer clock applied to the transfer electrode, the potential distribution of the potential well changes sequentially, and transfers the charges in the potential well in the phase shift direction of the transfer clock. It functions as a so-called shift register. Hereinafter, the vertical transfer unit 7 is set to “V
The register and the horizontal transfer unit 3 are referred to as an “H register”.

FIG. 2 is an enlarged plan view showing part A of FIG. As shown in FIG. 2, an arrangement region 6a of the read gate unit 6, a transfer channel region 7a of the vertical transfer unit 7, and a channel stopper formation region (channel stopper region) 9a are formed.

The arrangement region 6a of the read gate portion refers to a region where a large number of read gate portions 6 are formed in the same column direction in FIG. A p-type impurity region that forms a variable potential barrier of the read gate unit 6 is formed between the light receiving unit 5 and one of the vertical transfer units 7 in the arrangement region 6a of the read gate unit.

The transfer channel area 7a is
In which a transfer channel for transferring the signal charge is formed. A transfer channel mainly composed of an n-type impurity region is formed between the light receiving portions 5 at predetermined distances from the light receiving portions on both sides.

The channel stopper region 9a is
Is a region where a channel stopper 9 made of, for example, a high-concentration p-type impurity region is formed to prevent the signal charges generated in the above from flowing into the different cell side. This channel stopper 9
Are formed in a lattice shape surrounding the periphery of the light receiving section 5.

At right angles to the transfer channel area 7a,
A plurality of first vertical transfer electrodes (10A, 10B) connected to the first inter-pixel wiring (10a, 10b) are formed,
These vertical transfer electrodes (10A, 10B) are alternately arranged in the column direction.

Further, a plurality of second vertical transfer electrodes (11A, 11B) connected to the second inter-pixel wirings (11a, 11b) are formed orthogonal to the transfer channel region 7a. The vertical transfer electrodes (11A, 11B) are alternately arranged in the column direction.

As shown in FIG. 2, the second vertical transfer electrodes (11A, 11B) are arranged in the same direction while partially overlapping the first vertical transfer electrodes (10A, 10B). In addition, the first vertical transfer electrodes (10A, 10A)
B) is a second vertical transfer electrode (11) adjacent in the column direction.
A, 11B) overlap with each other by a predetermined width. The second vertical transfer electrodes (11A, 11B)
Each region (6a, 7a, 9a) has a rectangular shape that substantially covers a portion in each cell.

The first vertical transfer electrodes (10A, 10B) and the first inter-pixel wirings (10a, 10b) are made of the same material on the same level, for example, a first polysilicon layer. ing. Further, the second vertical transfer electrodes (11A, 11B) and the second inter-pixel wiring (11a,
11b) is also composed of the same material at the same level, for example, a second polysilicon layer laminated on the first polysilicon layer with an insulating film interposed.

The transfer clock φV2 is applied to the first vertical transfer electrode 10A, and the transfer clock φV4 is applied to the other first vertical transfer electrode 10B. Further, the transfer clock φV1 is applied to the second vertical transfer electrode 11A,
The transfer clock φV3 is applied to the vertical transfer electrode 11B. As described above, the four vertical transfer electrodes (10A, 10B, 11A, 11B) to which the four-phase transfer clocks are applied are set as a set, and the vertical transfer electrodes are repeatedly arranged on the entire surface of the imaging unit 2 in FIG.

FIG. 3 is a diagram schematically showing an example of the arrangement of the entire chip including the peripheral area of the imaging section. Imaging unit (effective unit)
The vertical transfer electrodes (10A, 10A)
B, 11A, 11B) to the four-phase vertical transfer clock (φV
1, φV2, φV3, φV4) for supplying any of four clock wiring layers (12a, 12b, 12c, 1)
2d) are arranged side by side. Clock wiring layer 12
a indicates that the clock wiring layer 12 is connected to the second vertical transfer electrode 11A.
b denotes the first vertical transfer electrode 10A and the clock wiring layer 12
c is connected to the other second vertical transfer electrode 11B, and the clock wiring layer 12d is connected to the other first vertical transfer electrode 10B via left and right contacts.

The H register 3 is covered with a light shielding film 13 to shield external light and reduce noise. The output unit 4 described above (FIG. 1) is provided on the charge transfer end side of the H register 3.
Is provided. Electrode pads 14 to which wires are bonded for inputting / outputting various signals or power supply voltages are formed on the outer periphery of the chip outside the light-shielding film 13 and the clock wiring layers 12a to 12d of the H register 3.

FIG. 4 is a sectional view taken along the line AA 'of FIG. As shown in FIG. 4, a p-type silicon substrate or a p-type well (hereinafter, referred to as a substrate) 20 formed on the silicon substrate is formed of, for example, an n-type impurity region and has a pn junction between the substrate 20 and the center. The light receiving unit 5 is configured to generate a signal charge by performing photoelectric conversion in the region described above, and accumulate the signal charge for a certain period of time. In addition, between each light receiving section 5,
A channel stopper 9 made of a high-concentration p-type impurity region is formed as deep as the substrate 20. The channel stopper 9 is formed on a lattice surrounding the light receiving unit 5 in FIG.

On the substrate 20, an insulating film 30 such as silicon oxide is formed, and the first inter-pixel wiring 10a and the second
Are inter-insulated by the insulating film 30 and are stacked. Also, on the second inter-pixel wiring 11a,
A light-shielding film 40 made of a metal such as aluminum or tungsten is formed with the insulating film 30 interposed therebetween. The light-shielding film 40 is open above the light receiving section 5.

Although not shown, the entire surface covered with the light shielding film 40 and the insulating film 30, for example, PSG (Phospho
silicate glass), BPSG (Borophosphosilicate gla
ss), an interlayer insulating film made of silicon oxide, silicon nitride, or the like is formed, and the surface of the interlayer insulating film is planarized. The interlayer insulating film may be a laminate of insulating films made of the above materials. An on-chip color filter (OCCF) is disposed on the flattened surface of the interlayer insulating film, and an on-chip lens (OCC) made of a light transmitting material such as a negative photosensitive resin is provided on the OCCF.
L). OCL lens surface (convex curved surface)
The light received in the step (a) is collected, a specific wavelength region is selected by the OCCF, and is incident on the light receiving unit 5.

Next, a method of manufacturing the CCD image pickup device of the present embodiment will be described focusing on a method of manufacturing vertical transfer electrodes and inter-pixel wiring. First, steps up to a step shown in FIG. According to the known method,
Various impurity regions are formed in predetermined portions of the silicon substrate 20 shown in FIG. That is, a channel stopper 9 is formed by ion-implanting, for example, a p-type impurity region at a high concentration in the silicon substrate 20, and a light-receiving unit 5 is formed by ion-implanting, for example, an n-type impurity under predetermined conditions. A transfer channel is formed by ion-implanting a type impurity under predetermined conditions. For example, a read gate portion is formed by ion-implanting a p-type impurity under predetermined conditions. Then, a thermal oxidation method or a CVD (Chemical Vapor) method is applied to the surface of the substrate 20 on which the various impurity regions are formed.
or Deposition) method to form an insulating film 31 made of silicon oxide or the like. A first polysilicon layer doped with impurities and having increased conductivity is deposited on the insulating film 31 by a CVD method, and the first polysilicon layer is patterned to form a first polysilicon layer together with the first inter-pixel wiring 10a. The first vertical transfer electrodes (10A, 10B) and other first
Are formed. Then, an insulating film 32 made of silicon oxide is formed on the first inter-pixel wiring 10a, the first vertical transfer electrodes (10A, 10B) and the other first inter-pixel wiring 10b in a region (not shown) by a thermal oxidation method.
To form

Next, as shown in FIG. 5B, polysilicon is deposited on the insulating films (31, 32) by the CVD method, for example, phosphorus is diffused into the polysilicon, and impurities are added. Thus, a second polysilicon layer 11 having increased conductivity is formed.

Next, as shown in FIG. 5C, a silicon oxide film 33 is formed on the second polysilicon layer 11 by, for example, a CVD method or a thermal oxidation method as an oxidation suppressing film in a later oxidation step. Form. The thickness of the silicon oxide film 33 is set to 1 in consideration of the uniformity on the wafer surface.
0 nm or more.

Next, as shown in FIG. 6D, a resist is applied on the silicon oxide film 33, and a pattern of a second inter-pixel wiring and a second vertical transfer electrode is formed by a photolithography process. A resist film R is formed.

Next, as shown in FIG. 6E, the silicon oxide film 33 is patterned by, for example, dry etching or wet etching to form a silicon oxide film 33a.

Next, as shown in FIG. 7F, using the same resist film R, the second polysilicon layer 11 is formed, for example, by a dry etching method to form a second inter-pixel wiring 11.
a ′ and a second vertical transfer electrode (not shown) and another second vertical transfer electrode
(Hereinafter referred to as a second inter-pixel wiring, etc.). After that, the resist film R is removed. The silicon oxide film 33 on the second polysilicon layer 11
If the thickness of “a” is sufficiently large, after removing the resist film R, the second polysilicon layer 11 may be etched using the silicon oxide film 33a as a mask.

Next, as shown in FIG. 7G, the second inter-pixel wiring 11a 'and the like are oxidized to form a silicon oxide film 34. By the oxidation step, the second inter-pixel wiring 11 is formed.
a and the like are formed. At this time, the second inter-pixel wiring 11
The amount of oxidation in the horizontal direction such as a 'is the same as in the case of the conventional structure. However, the amount of oxidization from above such as the second inter-pixel wiring 11a 'is smaller than that of the conventional structure. This is because the silicon oxide film 33a is provided above the second inter-pixel wiring 11a 'and the like, so that the diffusion of oxygen from above during oxidation is slightly suppressed. In the drawing, the silicon oxide film 33a after the oxidation step is included in the silicon oxide film 34.

Next, as shown in FIG. 7H, in order to secure a withstand voltage between the second inter-pixel wiring and the like and a light-shielding film to be formed later and to reduce a parasitic capacitance, silicon oxide is applied to the entire surface by, for example, a CVD method. Deposit. In the drawing, the insulating film 31, the insulating film 32, and the insulating film 34 after the deposition of the silicon oxide film are referred to as an insulating film 30.

As a subsequent step, on the insulating film 30,
For example, a metal film such as tungsten or aluminum is deposited by a sputtering method or a CVD method, and is patterned so as to be opened above the light receiving section 5 to form a light shielding film 40. Can be formed.

According to the method for manufacturing a CCD image pickup device according to the present embodiment, for example, the thickness and width of the initial second inter-pixel wiring 11a ′ immediately after patterning are each 0.5 μm.
In the case of m and 1.0 μm, the width of the second inter-pixel wiring 11a finally becomes 0.8 μm due to the oxidation step in FIG. 7 (g), but the thickness does not reach the conventional 0.4 μm. Does not decrease. Therefore, the cross-sectional area of the second inter-pixel wiring 11a is not as small as that of the conventional structure, the resistance of the second inter-pixel wiring 11a can be reduced, and the propagation delay of the transfer clock can be suppressed. Further, depending on the resistance value, the thickness of the second polysilicon layer can be reduced. Even when the pixel size is reduced, it is not necessary to increase the thickness of the second polysilicon layer, and it is not necessary to increase the position of the on-chip lens. Sensitivity can be suppressed on the aperture opening side (the side where the F value is small) where the aperture of the imaging lens of the camera is opened. Further, by controlling the thickness of the silicon oxide film 33 to be formed while suppressing an increase in the resistance of the inter-pixel wiring, the second pixel can be formed without changing the distance between the substrate 20 and the light-shielding film 40 in the light receiving section 5. Inter-wiring 11 etc. and light shielding film 40
It is also possible to increase the distance between the second vertical transfer electrode and the second vertical transfer electrode without deteriorating the smear characteristics.
The parasitic capacitance between the inter-pixel wiring 11a and the light shielding film 40 can be reduced, and the propagation delay can be suppressed.

Second Embodiment FIG. 8 is a cross-sectional view of the CCD image pickup device of this embodiment, taken along line AA ′ of FIG. As shown in FIG. 8, the CCD image pickup device according to the present embodiment is basically the same as the first embodiment, except that only a silicon oxide film is used as an oxidation suppressing film on the second inter-pixel wiring 11a. Instead, a silicon nitride film 50a is formed.

Next, a method of manufacturing the CCD image pickup device of the present embodiment will be described focusing on a method of manufacturing vertical transfer electrodes and inter-pixel wiring. First, as shown in FIG. 9A, similarly to the first embodiment, according to a known method,
Various impurity regions are formed at predetermined positions of the silicon substrate 20, an insulating film 31 made of silicon oxide or the like is formed on the surface of the substrate 20, and the first inter-pixel wiring 10a is formed on the insulating film 31 together with the first inter-pixel wiring 10a. A first vertical transfer electrode and another first inter-pixel wiring are formed in the region. And
An insulating film 32 made of silicon oxide is formed on the first inter-pixel wiring 10a, the first vertical transfer electrode in a region (not shown), and the other first inter-pixel wiring by a thermal oxidation method.

Next, as shown in FIG. 9B, polysilicon is deposited on the insulating films (31, 32) by the CVD method, and for example, phosphorus is diffused into the polysilicon to remove impurities. The added second polysilicon layer 11 having an increased conductivity is formed.

Next, as shown in FIG. 9C, a silicon oxide film 33 is formed on the second polysilicon layer 11 by, for example, a CVD method or a thermal oxidation method. In addition,
The thickness of the silicon oxide film 33 is set to 10 nm or more in consideration of uniformity on the wafer surface. Then, a silicon nitride film 50 is further formed on the silicon oxide film 33 by, for example, a CVD method. The silicon nitride film 5
The film thickness of 0 is set to 10 in consideration of the uniformity on the wafer surface.
nm or more.

Next, as shown in FIG. 10D, a resist is applied on the silicon nitride film 50, and a pattern of a second inter-pixel wiring and a second vertical transfer electrode is formed by a photolithography process. A resist film R is formed.

Next, as shown in FIG. 10E, the silicon nitride film 50a and the silicon oxide film 33a are formed by patterning the silicon nitride film 50 and the silicon oxide film 33 by, for example, dry etching or wet etching. .

Next, as shown in FIG. 11F, the second polysilicon layer 11 is formed by using the same resist film R by, for example, a dry etching method.
1a ', patterning is performed on a second vertical transfer electrode (not shown) and another second inter-pixel wiring (hereinafter, referred to as a second inter-pixel wiring and the like). After that, the resist film R is removed. The silicon nitride film 50 on the second polysilicon layer 11
If the thickness of the silicon nitride film 5a is sufficiently large, the resist film R is removed.
0a and the silicon oxide film 33a as a mask,
May be etched.

Next, as shown in FIG. 11G, the second inter-pixel wiring 11a 'and the like are oxidized to form a silicon oxide film 34.
To form By the oxidation step, the second inter-pixel wiring 1 is formed.
1a and the like are formed. At this time, the second inter-pixel wiring 11
The amount of oxidation in the horizontal direction such as a 'is the same as in the case of the conventional structure. However, in addition to the silicon oxide film 33a, the silicon nitride film 5
Since 0a is formed, almost no oxygen from above is passed during oxidation, so that the second inter-pixel wiring 11
The amount of oxidation of a ′ from above is almost zero. In the figure, the silicon oxide film 33 after the oxidation step is shown.
“a” is included in the silicon oxide film 34.

Next, as shown in FIG. 11 (h), as in the first embodiment, for example, in order to secure the breakdown voltage between the second inter-pixel wiring 11a and the like and the light-shielding film formed later and to reduce the parasitic capacitance, Silicon oxide is deposited on the entire surface by a CVD method.
In the figure, the insulating film 31 after the silicon oxide film is deposited,
The insulating film 32 and the insulating film 34 are shown as an insulating film 30.

As a subsequent step, as in the first embodiment, for example, a sputtering method or a CVD method is performed on the insulating film 30.
By depositing a metal film such as tungsten or aluminum by a method and patterning the film so as to open above the light receiving section 5 and forming the light shielding film 40, the CCD image pickup device shown in FIG. 8 can be formed. .

According to the manufacturing method of the CCD image pickup device according to the present embodiment, for example, the thickness and the width of the second
In the case of m and 1.0 μm, the width of the second inter-pixel wiring 11 a finally becomes 0.8 μm but the thickness remains 0.5 μm by the oxidation step in FIG. That is, the cross-sectional area of the second inter-pixel wiring can be reduced to about 80% as compared with immediately after the patterning. For example,
When the cross-sectional area of the second inter-pixel wiring is made the same as that of the conventional product, the thickness of the second polysilicon layer may be reduced to 0.4 μm. As a result, the same effect as in the first embodiment can be obtained.

Third Embodiment FIG. 12 is a cross-sectional view of the CCD image pickup device of the present embodiment, taken along line AA ′ of FIG. As shown in FIG.
The CCD imaging device according to the present embodiment is basically the first
As in the second embodiment, only the silicon nitride film 50a is used as an oxidation suppressing film on the second inter-pixel wiring 11a.

Next, a method of manufacturing the CCD image pickup device according to the present embodiment will be described focusing on a method of manufacturing a vertical transfer electrode and a wiring between pixels. First, as shown in FIG. 13A, similarly to the first embodiment, various impurity regions are formed at predetermined locations on the silicon substrate 20 according to a known method, and the surface of the substrate 20 is made of silicon oxide or the like. An insulating film 31 is formed, and a first vertical transfer electrode and another first inter-pixel wiring are formed on the insulating film 31 in a region (not shown) together with the first inter-pixel wiring 10a. Then, an insulating film 32 made of silicon oxide is formed on the first inter-pixel wiring 10a, the first vertical transfer electrode in a region (not shown), and other first inter-pixel wirings by a thermal oxidation method.

Next, as shown in FIG. 13B, polysilicon is deposited on the insulating films (31, 32) by the CVD method, and for example, phosphorus is diffused into the polysilicon to remove impurities. The added second polysilicon layer 11 having an increased conductivity is formed.

Next, as shown in FIG. 13C, the second polysilicon layer 11 is formed on the second polysilicon layer 11 by, eg, CVD.
A silicon nitride film 50 is formed. The thickness of the silicon nitride film 50 is set to 1 in consideration of the uniformity on the wafer surface.
0 nm or more.

Next, as shown in FIG. 14D, a resist is applied on the silicon nitride film 50, and a pattern of a second inter-pixel wiring and a second vertical transfer electrode is formed by a photolithography process. A resist film R is formed.

Next, as shown in FIG. 14E, the silicon nitride film 50 is patterned by, for example, dry etching or wet etching to form a silicon nitride film 50a.

Next, as shown in FIG. 15F, using the same resist film R, the second polysilicon layer 11 is formed, for example, by the dry etching method to form the second inter-pixel wiring 1.
1a ', patterning is performed on a second vertical transfer electrode and another second inter-pixel wiring (hereinafter, referred to as a second inter-pixel wiring or the like) in a region (not shown). After that, the resist film R is removed. When the thickness of the silicon nitride film 50a on the second polysilicon layer 11 is sufficiently large, after removing the resist film R, the second polysilicon layer 11 is removed using the silicon nitride film 50a as a mask. It may be etched.

Next, as shown in FIG. 15G, the second inter-pixel wiring 11a 'and the like are oxidized to form an oxide film. By the oxidation step, the second inter-pixel wiring 11a and the like are formed. At this time, the amount of oxidation in the horizontal direction of the second inter-pixel wiring 11a 'and the like is the same as in the case of the conventional structure. However, since the silicon nitride film 50a is formed on the upper part of the second inter-pixel wiring 11a 'and the like, almost no oxygen is passed from above during the oxidation, so that the second The amount of oxidization from above of the inter-pixel wiring 11a 'becomes almost zero.

Next, as shown in FIG. 15 (h), as in the first embodiment, for example, in order to secure the breakdown voltage between the second inter-pixel wiring 11a and the like and the light-shielding film formed later and to reduce the parasitic capacitance, Silicon oxide is deposited on the entire surface by a CVD method.
In the figure, the insulating film 31 after the silicon oxide film is deposited,
The insulating film 32 and the insulating film 34 are shown as an insulating film 30.

As a subsequent step, as in the first embodiment, for example, a sputtering method or a CVD method is performed on the insulating film 30.
By depositing a metal film such as tungsten or aluminum by a method and patterning the metal film so as to open above the light receiving section 5, and forming the light shielding film 40, the CCD image pickup device shown in FIG. 12 can be formed. .

According to the method for manufacturing a CCD image pickup device according to the present embodiment, the same effects as in the second embodiment can be obtained.

The solid-state imaging device and the method of manufacturing the same according to the present invention are not limited to the description of the above embodiment. For example, in the present embodiment, a two-layer structure in which the second vertical transfer electrode and the second inter-pixel wiring are provided above the first vertical transfer electrode and the first inter-pixel wiring has been described. It may have a structure or a structure having three or more layers. In addition, the present invention may be applied to the step of forming the lower first vertical transfer electrode and the first inter-pixel wiring. In addition, various changes can be made without departing from the gist of the present invention.

[0092]

According to the present invention, the amount of oxidization of the conductive film in the oxidation step after the patterning of the conductive film can be reduced to prevent a decrease in the cross-sectional area of the conductive film. Thus, it is possible to suppress a propagation delay due to a decrease in the amplitude of the transfer voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a CCD imaging device according to a first embodiment.

FIG. 2 is an enlarged plan view showing a portion A in FIG. 1 of the CCD image pickup device according to the first embodiment.

FIG. 3 is a diagram illustrating a CCD image sensor according to the first embodiment;
FIG. 3 is a diagram schematically illustrating an example of an arrangement of the entire chip including a peripheral region of an imaging unit.

FIG. 4 is a sectional view of the CCD imaging device according to the first embodiment, taken along line AA ′ of FIG. 2;

FIGS. 5A and 5B are cross-sectional views illustrating a manufacturing process in the method for manufacturing the CCD imaging device according to the first embodiment, and FIG.
5A shows the steps up to the step of forming the first vertical transfer electrode and the first inter-pixel wiring, FIG. 5B shows the steps up to the step of forming the second polysilicon layer, and FIG.

FIG. 6 is a cross-sectional view showing a step subsequent to that of FIG. 5, in which (d) shows up to a resist film forming step, and (e) shows up to a silicon oxide film patterning step.

7 is a cross-sectional view showing a step subsequent to that of FIG. 6; FIG. 7 (f) shows a step until the patterning step of the second polysilicon layer, and FIG. 7 (g) shows the oxidation of the patterned second polysilicon layer. (H) shows the process up to the step of forming the second vertical transfer electrode and the second inter-pixel wiring according to (a).

FIG. 8 is a cross-sectional view of the CCD image sensor according to the second embodiment, taken along line AA ′ of FIG.

FIG. 9 is a cross-sectional view illustrating a manufacturing process in a method for manufacturing a CCD imaging device according to the second embodiment, and FIG.
FIG. 5A illustrates a process of forming a first vertical transfer electrode and a first inter-pixel line, FIG. 5B illustrates a process of forming a second polysilicon layer, and FIG. 5C illustrates a process of forming a silicon oxide film and a silicon nitride film. Show.

10 is a cross-sectional view showing a step that follows the step shown in FIG. 9; FIG. 10D shows up to the step of forming a resist film; and FIG. 10E shows up to the step of patterning a silicon nitride film and a silicon oxide film.

11 is a cross-sectional view showing a step subsequent to that of FIG. 10; FIG. 11 (f) shows a step until a second polysilicon layer patterning step, and FIG. 11 (g) shows an oxidation of the patterned second polysilicon layer. (H) shows the process up to the step of forming the second vertical transfer electrode and the second inter-pixel wiring according to (a).

FIG. 12 is a cross-sectional view of the CCD imaging device according to the third embodiment, taken along line AA ′ of FIG. 2;

FIG. 13 is a cross-sectional view illustrating a manufacturing process in a method for manufacturing a CCD imaging device according to a third embodiment;
(A) shows up to the step of forming the first vertical transfer electrode and the first inter-pixel wiring, (b) shows the step of forming the second polysilicon layer, and (c) shows the step of forming the silicon nitride film. .

14 is a cross-sectional view showing a step that follows the step shown in FIG. 13; FIG. 14D shows up to the step of forming a resist film, and FIG. 14E shows up to the step of patterning a silicon nitride film.

FIG. 15 is a sectional view showing a step that follows the step shown in FIG. 14; FIG. 15 (f) shows a step of patterning the second polysilicon layer; FIG. 15 (g) shows the oxidation of the patterned second polysilicon layer; (H) shows the process up to the step of forming the second vertical transfer electrode and the second inter-pixel wiring according to (a).

FIG. 16 is a diagram showing a conventional CCD image pickup device.
FIG. 3 is a sectional view taken along line AA ′ of FIG. 2.

FIG. 17 is a cross-sectional view showing a manufacturing process in a method of manufacturing a CCD image pickup device according to a conventional example, and FIG. 17 (a) shows a process until a first vertical transfer electrode and a first inter-pixel wiring are formed; (B) shows a process of forming a second polysilicon layer;
(C) shows up to the step of forming a resist film.

FIG. 18 is a cross-sectional view showing a step that follows the step shown in FIG. 17; FIG. 18 (d) shows a step until a second polysilicon layer patterning step, and FIG. 18 (e) shows an oxidation of the patterned second polysilicon layer. (F) up to the step of forming the second vertical transfer electrode and the second inter-pixel wiring according to (a).

FIG. 19 is a diagram schematically illustrating an example of an arrangement of the entire chip including a peripheral region of an imaging unit for explaining a problem of a CCD imaging device according to a conventional example.

FIG. 20 illustrates clock waveforms at various parts in FIG. 19;

FIG. 21 shows one means for overcoming the problems of the conventional CCD image pickup device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CCD image sensor (solid-state imaging device), 2 ... Image pick-up part (effective part), 3 ... H register, 4 ... Output part, 4 '... Output circuit, 4a ... Charge-voltage conversion part, 5 ... Light receiving part, 6 ... Read gate part, 6a.
V register (vertical transfer unit), 7a ... transfer channel area,
8: Pixel, 9: Channel stopper, 9a: Arrangement area of channel stopper, 10A, 10B: First vertical transfer electrode, 10a, 10b: First inter-pixel wiring, 11A, 11
B: second vertical transfer electrode, 11a, 11b: second inter-pixel wiring, 12a, 12b, 12c, 12d: clock wiring layer, 13: light shielding film, 14: electrode pad, 20: silicon substrate (substrate), 30 ... insulating film, 31, 32 ... insulating film,
33, 33a ... silicon oxide film (oxidation suppressing film), 34 ...
Silicon oxide film, 40: light shielding film, 50, 50a: silicon nitride film (oxidation suppressing film), R: resist film.

Front page of the continued F-term (reference) 4M118 AA10 AB01 BA13 CA03 CB14 DA20 DB06 DB08 EA01 FA06 FA26 GB11 GD04 5C024 CX13 CY47 GY01 GY05 JX24 JX25 5F033 HH04 HH08 HH19 KK04 MM15 QQ08 QQ09 QQ11 QQ19 QQ28 QQ73 QQ76 RR04 RR06 SS11 SS27 VV00 XX08 XX32

Claims (11)

[Claims] 1. A plurality of light receiving portions and a transfer region are formed on a substrate, and a transfer voltage of a predetermined clock is applied when transferring a charge generated by the light receiving portion and swept out to the transfer region in a predetermined direction. A method for manufacturing a solid-state imaging device, comprising: forming, on a substrate, a transfer electrode for connecting the transfer electrodes for applying the transfer voltage to the plurality of transfer electrodes, and a wiring between the electrodes, the transfer electrode and the electrode Forming a conductive film to be the transfer electrode and the inter-electrode wiring on the substrate; forming an oxidation suppression film on the conductive film; and forming the oxidation suppression film and the conductive film on the substrate. A method of manufacturing a solid-state imaging device, comprising: a step of patterning a film into a pattern of the transfer electrode and the wiring between the electrodes; and a step of oxidizing the conductive film to form an oxide film on a side of the conductive film. 2. A step of forming a lower conductive film to be a lower transfer electrode and a wiring between lower electrodes on the substrate before the step of forming the conductive film on the substrate; Patterning an electrode and a pattern of the lower interelectrode wiring, oxidizing the lower conductive film,
2. The method according to claim 1, further comprising: forming a lower oxide film on the lower conductive film; and forming the conductive film on the substrate by forming a conductive film on the substrate and the lower oxide film. 3. A method for manufacturing a solid-state imaging device. 3. The method for manufacturing a solid-state imaging device according to claim 1, further comprising, after the step of oxidizing the conductive film, a step of forming a light-shielding film covering at least the oxidation suppressing film and the oxide film. 4. The method according to claim 1, wherein in the step of forming the conductive film on the substrate, a conductive film containing polycrystalline silicon is formed on the substrate. 5. The method for manufacturing a solid-state imaging device according to claim 1, wherein in the step of forming an oxidation suppression film on the conductive film, an oxidation suppression film containing silicon oxide is formed on the conductive film. 6. The method for manufacturing a solid-state imaging device according to claim 1, wherein in the step of forming an oxidation suppressing film on the conductive film, an oxidation suppressing film containing silicon nitride is formed on the conductive film. 7. The method according to claim 1, wherein in the step of forming an oxidation suppressing film on the conductive film, the oxidation suppressing film is formed of a multilayer film. 8. The method according to claim 7, wherein the oxidation suppressing film is formed of a multilayer film including a silicon oxide film and a silicon nitride film. 9. A light receiving unit and a transfer region formed on a substrate, and a predetermined clock for transferring charges formed on the substrate and generated by the light receiving unit and swept to the transfer region in a predetermined direction. A plurality of transfer electrodes to which a transfer voltage is applied, and inter-electrode wiring formed on a substrate and connecting the transfer electrodes for applying the transfer voltage to the plurality of transfer electrodes, wherein the transfer An oxidation suppressing film is formed on an electrode and a conductive film serving as the inter-electrode wiring, and an oxide film formed on a side portion of the conductive film has a thickness sufficiently larger than an oxide film formed on the conductive film. Imaging device. 10. The solid-state imaging device according to claim 9, further comprising a light-shielding film covering at least said oxidation suppressing film and said oxide film. 11. The solid-state imaging device according to claim 9, wherein said oxidation suppressing film includes silicon nitride.