JP2002100771A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a trench-type power element of Sic, having dielectric breakdown due to electric field concentration at a corner part of an electrode and having defects of the semiconductor substrate suppressed, with high manufacturing yield. SOLUTION: This device has the semiconductor substrate, a gate-insulating film 6, which is formed on the internal surface of a groove formed on the 1st surface of the substrate, a gate electrode 7 which is formed in the groove across the gate insulating film 6, a 1st conductive layer 4 which is formed on the top surface of the substrate except in the groove, and a 2nd conductive layer 1 formed on the 2nd surface as the reverse surface of the substrate; and a current flowing between the 1st conductive layer 4 and 2nd conductive layer 1 is suppressed by the gate electrode 7; and the depth of the 2nd conductive layer 1 from the 2nd surface is smaller at the part facing the groove than at a part facing the 1st surface, except in the groove.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a power field effect transistor having a trench gate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a MOSFET has been used as a power semiconductor element, and attempts have been made to reduce the resistance of the MOSFET. For example, a MOSFET having a configuration shown in FIG. 6 has been proposed. This device is a vertical device that flows a current in the vertical direction, and is a MOSFET having a trench gate. That is, as shown in this figure, an n ⁻ type semiconductor layer 102 (corresponding to an n type base layer) and a p ⁻ type semiconductor layer 103 are formed on the surface of an n ⁺ type semiconductor substrate 101 (corresponding to a drain layer). (. p-type base layer corresponds) is formed, the p ^- the surface of the type semiconductor layer 103 n ⁺ -type source layer 104 and the p ⁺
A mold contact layer 105 is formed. The n ⁻ type semiconductor layer 102 is a layer formed by epitaxial growth on the surface of the n ⁺ type semiconductor substrate 101.

A groove is formed from the surface of the n ⁺ -type source layer 104 to the n ^-- type semiconductor layer 102 through the p ^-- type semiconductor layer 103, and a gate insulating film is formed in the groove. A gate electrode 107 is buried through a film (oxide film) 106. The source electrode 1 is in contact with the surfaces of the n ⁺ -type source layer 104 and the p ⁺ -type contact layer 105 in contact therewith.
08 is provided, and an n ⁺ type semiconductor substrate 101 is provided.
The drain electrode 109 is provided on the back surface of the substrate.

A channel is formed on the surface (side surface portion of the groove) of the p ⁻ type semiconductor layer 103 corresponding to the gate electrode 107 formed in the groove with the gate insulating film 106 interposed therebetween.

The material of the semiconductor substrate 101 is SiC
The substrate made of this SiC (SiC substrate)
In particular, the trench type power MOSFET formed as described above has the following problems. That is, there is a problem that a SiC substrate, for example, a substrate using an SiC layer formed by epitaxial growth on the substrate surface has many defects, and an electric field is concentrated at a corner portion of the trench. Due to the concentration of the electric field, the insulating film (such as a gate insulating film) formed in the trench is easily broken down, and the insulating breakdown due to defects is also large on the substrate side, so that the element cannot be manufactured with high yield.

[0006]

As described above, the conventional Si
When a trench-type power device is formed on a substrate made of a semiconductor such as C, there are many substrate defects, and an electric field concentration occurs in the trench portion. Therefore, dielectric breakdown easily occurs at the portion, and the device can be manufactured with high yield. could not.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a trench power element in which insulation breakdown in an electric field concentration portion due to a defect in a semiconductor substrate is suppressed with a high production yield. .

[0008]

To solve the above problems, the present invention provides a semiconductor substrate and a gate electrode formed in a groove formed in a first surface of the semiconductor substrate. A first conductive layer formed on a surface other than the groove of the first surface of the semiconductor substrate, and a first conductive layer formed on a second surface that is a back surface with respect to the first surface of the semiconductor substrate. And a current flowing between the first conductive layer and the second conductive layer is controlled by the gate electrode, and the second surface of the second conductive layer is provided. , A portion facing the groove is shallower than a portion facing the first surface other than the groove.

It is desirable that the present invention has the following configuration.

(1) The groove is composed of a plurality of grooves, and the depth of the second conductive layer from the second surface is such that a portion facing the groove faces a first surface between the grooves. Shallower than the part to do.

(2) A first conductivity type body region is formed on the first surface between the trenches of the semiconductor substrate, and the first conductivity type is formed on the surface of the body region as the first conductive layer. Is formed in contact with the groove, and the second conductive layer is a drain region.

(3) The body region and the source region are formed in an epitaxial layer grown on a semiconductor substrate having the drain region.

(4) A gate insulating film is formed on an inner surface of the groove formed on the first surface of the semiconductor substrate, and the gate electrode is formed in the groove via the gate insulating film. That you are.

(5) The semiconductor substrate is made of silicon carbide.

The present invention also relates to a method of manufacturing a semiconductor device in which a current flowing between a gate electrode of a first conductive layer and a gate electrode of a second conductive layer is controlled by the gate electrode. Forming a first groove in the semiconductor substrate, epitaxially growing a semiconductor layer on the first surface of the semiconductor substrate including the groove, and forming a second layer in the portion of the semiconductor layer facing the first groove. Forming the gate electrode in the second groove; and forming the first conductive layer on the first surface of the semiconductor substrate other than the second groove. And a step of forming the second conductive layer on a second surface that is a back surface with respect to the first surface of the semiconductor substrate. provide.

In the present invention, it is preferable that a step of forming a gate insulating film on the inner surface of the second groove is provided, and the gate electrode is formed in the second groove via the gate insulating film. .

(Operation) According to the semiconductor device of the present invention, the second
The depth of the conductive layer from the second surface is smaller at a portion facing the groove formed on the first surface than at a portion facing the first surface other than the groove. It is possible to alleviate the electric field concentration at the corners of the gate electrode, thereby improving the device characteristics.

According to the method of manufacturing a semiconductor device of the present invention, a first groove is formed on a first surface of a semiconductor substrate, and a semiconductor is formed on the first surface of the semiconductor substrate including the first groove. Since the layer is epitaxially grown, defects propagating from the semiconductor substrate to the semiconductor layer (epitaxially grown layer) are expelled toward a portion of the epitaxially grown layer buried in the first groove and a portion immediately above the portion.
Epitaxial growth will be performed. That is, the defects generated in the semiconductor substrate are concentrated on a portion of the epitaxial growth layer buried in the first groove and a portion immediately above the first groove. Therefore, defects in the entire epitaxial growth layer can be reduced, and in particular, defects in a portion of the growth layer formed on the first surface except for the first groove can be significantly reduced.

Therefore, a second groove is formed in the epitaxial growth layer on the first groove to form a gate electrode therein, and an epitaxial growth layer formed on the first surface excluding the first groove is formed in the second groove. By manufacturing the first conductive layer as a current-carrying region, electric field concentration and dielectric breakdown due to defects in the semiconductor substrate are suppressed, mobility and the like are improved, and a semiconductor device excellent in controllability by the gate electrode is manufactured with high yield. It is possible to do.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a SiC trench gate type power MOSFET according to the embodiment. As shown in this figure, an n ⁻ -type semiconductor layer 2 (corresponding to an n-type base layer) and ap ⁻ are provided on the surface of an n ⁺ -type semiconductor substrate 1 (corresponding to a drain layer) in which a groove is formed.
Type (. Corresponding to p-type base layer or p-type body region) semiconductor layer 3 is formed, the p ^- type semiconductor layer 3
Are formed with an n ⁺ type source layer 4 and a p ⁺ type contact layer 5. The n ⁻ type semiconductor layer 2 is a layer formed by epitaxial growth on the surface of the n ⁺ type semiconductor substrate 1. Incidentally, the convex portion of the 1b are n ⁺ -type semiconductor substrate 1 in FIG. 1, 1a is n embedded in the groove of the n ⁺ -type semiconductor substrate 1 ^- indicating the type portion of the semiconductor layer 2.

A groove is formed from the surface of the n ⁺ type source layer 4 to the n ⁻ type semiconductor layer 2 through the p ⁻ type semiconductor layer 3, and a gate insulating film is formed in the groove. A gate electrode 7 is buried through a film (oxide film) 6. The planar shape of the groove is a strip shape (not shown), and a plurality of grooves are arranged in a direction perpendicular to the longitudinal direction (the left-right direction in the figure). A source electrode 8 is provided in contact with the surfaces of the n ⁺ type source layer 4 and the p ⁺ type contact layer 5, and the source layer 4 and the contact layer 5 are short-circuited by the source electrode 8. A drain electrode 9 is provided on the back surface of the n ⁺ type semiconductor substrate 1.

A channel is formed on the surface (side surface portion of the groove) of p ^- type semiconductor layer 3 corresponding to gate electrode 7 formed in the groove with gate insulating film (oxide film) 6 interposed therebetween. .

A plurality of the grooves are arranged in one direction.
These trenches define multiple transistor cells
You. That is, one transistor between each of these grooves
Tace cells are defined and each of these transistor cells
This is n⁺Source layer 4 and a p-type capacitor adjacent to source layer 4
And a source region 4 and a p-type body region.
Region 3 contacts the side surface of the groove to form a vertical MOSFET. p-type
N at the bottom of body region 3 ^-Type semiconductor layer 2
It is provided for the purpose.

A feature of the present invention is an n ⁺ -type semiconductor substrate (drain layer) 1 having irregularities and a gate electrode 7 provided opposite thereto. That is, the depth of the drain layer 1 from the surface on the side of the drain electrode 9 is shallower at the portion facing the gate electrode 7 than at the portion 1b facing the surface other than the gate electrode 7 (the portion of the p-type body region 3). . With such a configuration of the vertical MOSFET of the present embodiment, it is possible to alleviate the electric field concentration at the corner of the gate electrode 7 at the time of reverse bias, thereby improving the element characteristics.

Next, a method of manufacturing the above-described vertical MOSFET will be described with reference to FIGS.

As shown in FIG. 2A, an n ⁺ type semiconductor substrate 1 is made of n ⁺ doped, for example, 4
Since it is an H-SiC substrate and has many crystal defects such as micropipes and minute defects, the substrate itself is not suitable for forming a semiconductor device.

First, as shown in FIG. 2A, a groove is formed in an n ⁺ type semiconductor substrate 1 by RIE (reactive ion etching). 1b represents a portion other than the groove.
Next, as shown in FIG. 2B, an n ^- doped SiC layer is formed as an n ^- type semiconductor layer 2 by an epitaxial process. In this process, silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as source gases, and nitrogen (N ₂ ) is used as an n-type dopant. As a pretreatment, for example, when the surface is lightly etched with hydrogen, crystal defects can be reduced. In the process of epitaxial growth, underlying crystal defects propagate to the epitaxial layer or are newly generated during growth. However, the defect moves to the end of the groove and disappears at the end, so that the number of defects, particularly in the epitaxial layer region on the n ⁺ type semiconductor substrate 1b, is smaller than that in a case where the defect is directly grown on a SiC wafer without a groove. Become smaller.

Next, as shown in FIG.^-Doped SiC
The layers are formed by an epitaxial process. This
In process, silane (SiH_Four) And propane
(C_ThreeH ₈) Is used, and TMA (Al (C
H_Three)_Three) Is used. p^-Doped SiC layer is p-type body region
3 is obtained. Where n^-Doped SiC layer, p^-Do
Subsequent to the epitaxial SiC layer.
Instead of forming^-Dope layer epitaxially
After formation by the process, ion implantation of p-type impurities
Alternatively, a laminated structure may be formed.

Next, as shown in FIG. 3A, an n ⁺ -type source layer 4 and ap ⁺ -type contact layer 5 serving as a contact region of a body portion are formed by ion implantation. Then
As shown in FIG. 3B, a trench is formed by RIE according to the unevenness of the substrate before the epitaxial process.
That is, a trench is formed in a portion of the p ⁻ -doped SiC layer 3 facing the groove of the n ⁺ type semiconductor substrate. This trench is n
^The source layer 4 is formed so as to penetrate the p ⁻ -doped SiC layer 3 and reach the n ⁻ -doped SiC layer 2.

Next, after the trench is formed, gate oxidation is performed to form a gate insulating film (oxide film) 6. Further, polycrystalline silicon is buried in the trench to form a gate electrode 7 as a trench gate.

Next, as shown in FIG. 3C, for example, a titanium film and an aluminum film are successively deposited by a sputtering method, and an electrode and a wiring layer are formed on both surfaces of the substrate by patterning. can get. In this figure, 8 is a source electrode and 9 is a drain electrode.
Thereafter, the semiconductor device is completed through a passivation film forming step and the like in the same manner as in the conventional semiconductor device manufacturing method.

As described above, according to the method for manufacturing a vertical MOSFET of the present embodiment, a groove is formed on the surface of the n ⁺ type semiconductor substrate 1 on the side of the drain electrode 9, and a semiconductor layer is formed on the surface of the substrate 1 including the groove. Is epitaxially grown, so that epitaxial growth is performed while defects propagating from the substrate 1 to the epitaxial growth layer are expelled toward the portion 1a embedded in the first groove and the portion immediately above the portion 1a in the epitaxial growth layer. . That is, the defects generated in the substrate 1 are concentrated on the portion 1a of the epitaxial growth layer and a portion immediately above the portion 1a. Therefore, defects in the entire epitaxial growth layer can be reduced, and in particular, the defect density in the growth layer portion formed on the substrate portion 1b can be significantly reduced.

Therefore, the epitaxial growth layer portion 1
A trench is formed in the growth layer portion on the substrate a, and a gate electrode 7 is formed therein, and an n ⁺ -type source layer 4 is formed as a conduction region in the growth layer portion formed on the substrate portion 1b. By doing so, dielectric breakdown due to electric field concentration and defects in the semiconductor substrate is suppressed, mobility and the like are improved, and a semiconductor device excellent in controllability by the gate electrode 7 can be manufactured with high yield.

(Second Embodiment) Next, an embodiment in which the present invention is applied to an SIT (static induction thyristor) will be described.

FIG. 4 is a block diagram of a second embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a configuration of an IT. As shown in this figure, an n ⁻ -type semiconductor layer 42 (corresponding to an n-type base layer) is formed on the surface of an n ⁺ -type semiconductor substrate 41 (corresponding to a drain layer) in which a groove is formed. The n ⁺ type source layer 44 is formed on the surface of the n ⁻ type semiconductor layer 42. The n ⁻ type semiconductor layer 42 is a layer formed by epitaxial growth on the surface of the n ⁺ type semiconductor substrate 41. In FIG. 1, reference numeral 41b denotes a convex portion of the n ⁺ type semiconductor substrate 41, and reference numeral 41a denotes a portion of the n ⁻ type semiconductor layer 42 embedded in the groove of the n ⁺ type semiconductor substrate 41.

A groove is formed from the surface of the n ⁺ type source layer 44 to the n ⁻ type semiconductor layer 42, and a gate electrode is formed in the groove via a gate insulating film (oxide film) 46. 47 is embedded. The planar shape of the groove is a strip shape (not shown), and a plurality of grooves are arranged in a direction perpendicular to the longitudinal direction (the left-right direction in the figure). A source electrode 48 is provided on the surface of the n ⁺ -type source layer 44 in contact therewith, and a drain electrode 49 is provided on the back surface of the n ⁺ -type semiconductor substrate 41.

When the gate electrode 47 formed in the groove is negatively biased with respect to the n ⁺ -type source layer 44, the portion of the n ⁻ -type semiconductor layer 42 facing the gate electrode 47 (adjacent gate electrode 47). Gate insulating film 4)
The depletion layer extends from the interface with the gate electrode 6 and is connected to the depletion layer extending from the adjacent gate electrode 47 in the same manner, so that the current from the n ⁺ -type source layer 44 to the drain electrode 49 is cut off and the switch is turned off. Done. On the other hand, when the gate electrode 47 is biased positive or 0 with respect to the n ⁺ -type source layer 44, the above-described depletion layer does not extend, and a current flows from the n ⁺ -type source layer 44 to the drain electrode 49, and the element Is turned on.

A plurality of the grooves are arranged in one direction, and a plurality of transistor cells are defined by these grooves. That is, one transistor cell is defined between each of these trenches, and each of these transistor cells includes an n ⁺ -type source layer 44 and a source layer 44.
Is in contact with the side surface of the groove to form a vertical element. The n ⁻ type semiconductor layer 42 is provided for improving the breakdown voltage.

The feature of the present invention is an n ⁺ -type semiconductor substrate (drain layer) 41 having irregularities and a gate electrode 47 provided to face the same. That is, the depth of the drain layer 41 from the surface on the side of the drain electrode 49 is smaller at a portion facing the gate electrode 47 than at a portion 41b facing the surface other than the gate electrode 47 (the portion of the n ⁺ -type source layer 44). ing. With such a configuration of the vertical element of the present embodiment, it is possible to reduce the electric field concentration at the corner portion of the gate electrode 47, thereby improving the element characteristics.

Further, the method for manufacturing such a vertical element is described in the first aspect.
It is possible to use the same method as the embodiment. That is, a trench is formed in the growth layer portion on the epitaxial growth layer portion 41a and the gate electrode 47 is formed therein, and the growth layer portion formed on the substrate portion 41b has an n ⁺ -type as an energization region. By forming the source layer 44, electric field concentration and dielectric breakdown due to defects in the semiconductor substrate are suppressed, mobility and the like are improved, and the gate electrode 47 is formed.
It is possible to manufacture a semiconductor device having excellent controllability with good yield.

(Third Embodiment) Next, another embodiment of the SIT (static induction thyristor) will be described.

FIG. 5 is a block diagram of a third embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a configuration of an IT. In this figure, the same parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description will be omitted. The element of the present embodiment differs from the element of the second embodiment in that a gate using a pn junction is used instead of the insulated gate of FIG. That is, as shown in FIG. 5, a p ⁺ type semiconductor layer 57 is buried in the trench as a gate instead of the gate insulating film 46 and the gate electrode 47.

When the semiconductor layer 57 formed in the trench is negatively biased with respect to the n ⁺ -type source layer 44, the portion of the n ⁻ -type semiconductor layer 42 facing the semiconductor layer 57 (adjacent semiconductor layer 57). A depletion layer extends from the interface with the semiconductor layer 57 at the interface between the n ⁺ -type source layer 44 and the drain electrode 49. Is cut off and the switch is turned off. On the other hand, when the semiconductor layer 57 is biased positive or 0 with respect to the n ⁺ type source layer 44,
The depletion layer does not extend as described above, and a current flows from the n ⁺ -type source layer 44 to the drain electrode 49 to turn on the device.

In the SIT of the present embodiment, the same effects as in the second embodiment can be obtained. That is, it is possible to reduce the electric field concentration at the corner portion of the semiconductor layer 57, thereby improving the element characteristics. In addition, dielectric breakdown due to electric field concentration and defects in the semiconductor substrate is suppressed, and mobility and the like can be improved, and a semiconductor device excellent in controllability by the semiconductor layer 57 can be manufactured with high yield.

The present invention is not limited to the above embodiment. For example, in this embodiment, the power MOSF
Although ET and SIT have been described, the present invention can be similarly applied to an IGBT (insulated gate bipolar transistor) by reversing the conductivity type of the substrate impurity on the drain side of the power MOSFET. is there. In this case, the same effect as in the above embodiment can be obtained.

Further, in addition to using the power MOSFET, SIT, IGBT, etc. alone, a planar type field effect transistor,
The same effects as those of the present embodiment can be obtained when used as a part of a semiconductor device including other active elements such as bipolar transistors or passive elements such as resistors and inductors and capacitors. Further, the same effect can be obtained when an SOI substrate is used as the substrate.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0049]

According to the present invention, the electric field concentration at the corner of the trench is reduced, and the device characteristics are improved. Also, defects in the epitaxial layer on the substrate can be reduced,
The production yield of the device is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a trench power MOSFET according to a first embodiment of the present invention.

FIG. 2 is a process sectional view illustrating a manufacturing process of the MOSFET illustrated in FIG. 1;

FIG. 3 is a process sectional view following FIG. 2;

FIG. 4 is a sectional view showing a configuration of an SIT according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a configuration of an SIT according to a third embodiment of the present invention.

FIG. 6 shows a conventional trench type power MOSF.
Sectional drawing which shows the structure of ET.

[Explanation of symbols]

1 ... n ⁺ -type semiconductor substrate (drain layer) 1a ... n ⁺ -type semiconductor n embedded in the groove of the substrate 1 ^- -type semiconductor layer 2 parts 1b ... n ⁺ -type convex portion of the semiconductor substrate 1 (the groove 2 ... n ^- type semiconductor layer (n-type base layer) 3 ... p ^- type semiconductor layer (p-type base layer or p-type body region) 4 ... n ⁺ -type source layer 5 ... p ⁺ -type Contact layer 6 ... gate insulating film 7 ... gate electrode 8 ... source electrode 9 ... drain electrode

Claims (8)

[Claims] A semiconductor substrate; a gate electrode formed in a groove formed on a first surface of the semiconductor substrate; and a gate electrode formed on a surface of the first surface of the semiconductor substrate other than the groove. A first conductive layer, and a second conductive layer formed on a second surface, which is a back surface with respect to the first surface of the semiconductor substrate, wherein the first conductive layer and the second conductive layer The current flowing between the second conductive layer and the second conductive layer is controlled by the gate electrode, and the depth of the second conductive layer from the second surface is:
A semiconductor device, wherein a portion facing the groove is shallower than a portion facing the first surface other than the groove. 2. The groove comprises a plurality of grooves, and a depth of the second conductive layer from the second surface is such that a portion facing the groove faces a first surface between the grooves. 2. The semiconductor device according to claim 1, wherein said portion is shallower than said portion. 3. A first conductivity type body region is formed on a first surface between the trenches of the semiconductor substrate, and a first conductivity type body region is formed on the surface of the body region as the first conductive layer. 3. The semiconductor device according to claim 2, wherein a source region is formed in contact with said groove, and said second conductive layer is a drain region.
13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 3, wherein said body region and said source region are formed in an epitaxial layer grown on a semiconductor substrate provided with said drain region. 5. A gate insulating film is formed on an inner surface of the groove formed on the first surface of the semiconductor substrate, and the gate electrode is formed in the groove via the gate insulating film. The semiconductor device according to claim 1, wherein: 6. The semiconductor device according to claim 1, wherein said semiconductor substrate is made of silicon carbide. 7. A method of manufacturing a semiconductor device in which a current flowing between a first conductive layer and a second conductive layer gate electrode is controlled by the gate electrode, wherein a first surface of the semiconductor substrate is provided with a first surface. Forming a groove, a step of epitaxially growing a semiconductor layer on a first surface of the semiconductor substrate including the groove, and forming a second groove in a portion of the semiconductor layer facing the first groove. Forming, forming the gate electrode in the second groove, and forming the first conductive layer on the first surface of the semiconductor substrate other than the second groove. A method of manufacturing a semiconductor device, comprising: a step of forming a second conductive layer on a second surface, which is a back surface with respect to a first surface of the semiconductor substrate. 8. The method according to claim 1, further comprising the step of forming a gate insulating film on an inner surface of the second groove, wherein the gate electrode is formed in the second groove via the gate insulating film. Item 8. The method for manufacturing a semiconductor device according to Item 7.