JP2002100718A - Lead frame for semiconductor device, manufacturing method thereof, and semiconductor device using the lead frame - Google Patents

Lead frame for semiconductor device, manufacturing method thereof, and semiconductor device using the lead frame

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Publication number
JP2002100718A
JP2002100718A JP2000286725A JP2000286725A JP2002100718A JP 2002100718 A JP2002100718 A JP 2002100718A JP 2000286725 A JP2000286725 A JP 2000286725A JP 2000286725 A JP2000286725 A JP 2000286725A JP 2002100718 A JP2002100718 A JP 2002100718A
Authority
JP
Japan
Prior art keywords
semiconductor device
lead frame
tin
layer
silver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000286725A
Other languages
Japanese (ja)
Other versions
JP3417395B2 (en
Inventor
Takashi Kuhara
隆 久原
Hisahiro Tanaka
久裕 田中
Matsuo Masuda
松夫 舛田
Takeshi Tokiwa
剛 常盤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000286725A priority Critical patent/JP3417395B2/en
Priority to US09/953,915 priority patent/US6646330B2/en
Publication of JP2002100718A publication Critical patent/JP2002100718A/en
Application granted granted Critical
Publication of JP3417395B2 publication Critical patent/JP3417395B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a lead frame for semiconductor devices, a manufacturing method thereof, and a semiconductor device using the lead frame which has proper solder wettability, a strong jointing strength, and which is low cost, and contains no lead which is one among the harmful substances. SOLUTION: A lead frame 1 for semiconductor device has an inner lead portion 3, provided with a surface processing layer (A) made of silver or an alloy containing silver, and has an outer lead portion 2 provided with a surface processing layer (B) made of silver or an alloy which contains copper and tin of a body-centered tetragonal structure, and further, uses as its base material a plate-form raw material formed of nickel, copper, iron, or an alloy which contains one or more kinds of nickel, copper, and iron. Moreover, in the lead frame 1, a tin oxide layer is formed on the uppermost surface of the surface processing layer B, where the ratio of oxygen to tin is 0.5-1.8, and its thickness is 1-20 nm.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、環境有害物質のひ
とつである鉛を含まない半導体装置用リードフレーム、
及び、鉛を含まない半導体装置用リードフレームを用い
て形成される半導体装置及びその製造方法及びそれを用
いた半導体装置に関するものである。The present invention relates to a lead frame for a semiconductor device which does not contain lead which is one of environmentally harmful substances,
Also, the present invention relates to a semiconductor device formed using a lead frame for a semiconductor device containing no lead, a method of manufacturing the same, and a semiconductor device using the same.

【０００２】[0002]

【従来の技術】近年、環境問題が重要視されており、そ
の中でＩＣパッケージに使用される部品についても環境
有害物質を含まない材質を用いることが検討されてい
る。2. Description of the Related Art In recent years, environmental issues have been regarded as important, and among them, the use of materials that do not contain environmentally harmful substances has been studied for components used in IC packages.

【０００３】半導体装置用リードフレームに用いられる
材料の中で、環境に対して特に有害とされる物質に半田
に使用される鉛がある。鉛は放置すると半田から溶け出
て、人体及び他の生物に悪影響を及ぼすため、電子業界
では鉛を使用しない半田又は半田ペースト等の開発が進
められている。[0003] Among materials used for lead frames for semiconductor devices, lead used for solder is a substance that is particularly harmful to the environment. Since lead melts out of the solder when left unattended and adversely affects the human body and other organisms, the electronics industry has been developing solder or solder paste that does not use lead.

【０００４】鉛含有半田の代替えとしてパラジウムを全
面メッキしたリードフレームが実用化されているが、パ
ラジウムは単体ではダイアタッチ工程やワイヤボンド工
程で熱がかかると、半田の濡れ性が劣化し、表面実装時
の半田付けの信頼性に問題があった。このため、近年、
パラジウムの表面に金を保護膜として薄くメッキしたリ
ードフレームが提案されているが、最表面に金のフラッ
シュメッキを行うと、モールド樹脂とリードフレームの
密着性が低下するため、金との密着性を改善した、コス
トの高いモールド樹脂を使用する必要がある。また、パ
ラジウムの供給国は限られており、供給不足のため価格
が高騰することで、コストが高くなり、さらに、金を保
護膜として使用するとコストがさらに高くなるという問
題を有している。As a substitute for lead-containing solder, lead frames plated with palladium on the entire surface have been put into practical use. However, when palladium alone is heated in a die attach step or a wire bonding step, the wettability of the solder deteriorates, and There was a problem in the reliability of soldering during mounting. For this reason, in recent years,
A lead frame in which the surface of palladium is thinly plated with gold as a protective film has been proposed, but flash plating of gold on the outermost surface reduces the adhesion between the mold resin and the lead frame. It is necessary to use a high-cost mold resin which is improved. In addition, the supply countries of palladium are limited, and there is a problem that the cost rises due to a rise in price due to a shortage of supply, and that the cost is further increased when gold is used as a protective film.

【０００５】また、パラジウムを全面にメッキした半導
体装置用リードフレームはＩＣの組み立て工程時のモー
ルド樹脂によりＩＣを封止する工程でバリが発生し易
く、このバリを除去する工程を追加しなければならない
ため、コストが高くなるという問題を有している。ま
た、パラジウムを全面メッキしたリードフレームでは、
パラジウムとリードフレーム基材である金属との間に大
きな電位差が生じるため、パラジウムと基材との間にニ
ッケルやパラジウムニッケル合金を介在させなければな
らない。このとき、基材にニッケル又はニッケル合金、
又は、鉄又は鉄合金を使用した場合は、腐食が起こると
いう問題が生じるため、現状では基材として銅又は銅合
金を使用したものにしか対応できないという問題を有し
ている。Also, a lead frame for a semiconductor device in which palladium is plated on the entire surface is likely to generate burrs in a step of sealing the IC with a mold resin in an IC assembling step, and a step of removing the burrs must be added. Therefore, there is a problem that the cost increases. In addition, in lead frames that are entirely plated with palladium,
Since a large potential difference occurs between palladium and the metal that is the lead frame base material, nickel or a palladium nickel alloy must be interposed between the palladium and the base material. At this time, nickel or nickel alloy on the substrate,
Alternatively, when iron or an iron alloy is used, there is a problem that corrosion occurs. Therefore, at present, there is a problem that only a substrate using copper or a copper alloy can be used.

【０００６】パラジウム以外の材料を用いた鉛を使用し
ない半田又は半田ペーストとしては、錫−鉛系半田の鉛
の代わりに、インジウム、ビスマス、亜鉛等の金属を添
加して、鉛を使用しない半田又は半田ペーストにより表
面処理層を形成することが提案されている。[0006] As a solder or solder paste not using lead using a material other than palladium, a metal such as indium, bismuth, zinc or the like is added instead of lead of a tin-lead solder, and a lead-free solder is used. Alternatively, it has been proposed to form a surface treatment layer with a solder paste.

【０００７】リフローソルダリング用の半田や半田ペー
ストでは錫の他に２種類以上の金属を含む３元系、４元
系の合金が提案されているが、メッキ用の半田として
は、電気メッキの際にメッキ液において３元系、４元系
の合金の析出組成を制御することは困難なので、錫と他
に１種類の金属を添加した２元系の合金が多く用いられ
る。しかし、錫にインジウムを添加したものは、インジ
ウムのコストが高く実用化困難である。錫にビスマスを
添加したものは、融点を低くできるが、硬く脆くなりや
すいため加工性が悪く、曲げ加工を含むリードフレーム
に使用することは困難であり、また、錫にビスマスを添
加したものは、半田濡れ性が悪いため接合強度が弱く、
熱疲労強度が弱く、ビスマスが界面に析出し易いため表
面実装時に半田からＩＣが浮いてリフトオフ現象が発生
するという問題を有している。錫に亜鉛を添加したもの
は、錫−鉛系半田に近い融点を有し、亜鉛のコストも低
いが、亜鉛は空気中で酸化しやすいため、ＩＣの組み立
て工程で熱履歴がかかると酸化して半田濡れ性が劣化す
るという問題を有している。For solder and solder paste for reflow soldering, ternary and quaternary alloys containing two or more metals in addition to tin have been proposed. At this time, it is difficult to control the precipitation composition of the ternary and quaternary alloys in the plating solution, so binary alloys to which tin and one other metal are added are often used. However, those obtained by adding indium to tin are difficult to put into practical use because of the high cost of indium. Although the melting point of bismuth added to tin can be lowered, the workability is poor because it is easily hard and brittle, and it is difficult to use it for lead frames including bending. , Due to poor solder wettability, weak bonding strength,
Since the thermal fatigue strength is weak and bismuth is easily deposited on the interface, there is a problem that the IC floats from the solder during surface mounting and a lift-off phenomenon occurs. Tin-added zinc has a melting point close to that of tin-lead solders, and the cost of zinc is low. However, zinc is easily oxidized in the air. Therefore, the solder wettability deteriorates.

【０００８】そこで、近年、鉛を使用しない半田又は半
田ペーストとして、錫に銀を添加した合金、及び、錫に
銅を添加した合金が提案されている。Therefore, in recent years, as a solder or a solder paste not using lead, an alloy in which silver is added to tin and an alloy in which copper is added to tin have been proposed.

【０００９】従来の、錫に銀を添加した合金でメッキさ
れた半導体装置用リードフレームとしては、特願平８−
２７３９５４号公報（以下、イ号公報と呼ぶ）に「非シ
アンの錫−銀合金電気メッキ浴から、皮膜中の銀含有量
が０．１％〜１０％で、皮膜厚さが０．１〜１００μｍ
である光沢を有した錫−銀合金メッキ皮膜を施したこと
を特徴とする電気・電子回路部品」が開示されている。A conventional lead frame for a semiconductor device plated with an alloy obtained by adding silver to tin is disclosed in Japanese Patent Application No. Hei.
No. 273954 (hereinafter referred to as “A”) states that “from a non-cyanide tin-silver alloy electroplating bath, the silver content in the coating is 0.1% to 10%, and the coating thickness is 0.1 to 10%. 100 μm
An electrical / electronic circuit component having a glossy tin-silver alloy plating film ".

【００１０】また、従来の、錫に銀を添加した合金又は
錫に銅を添加した合金でメッキされた半導体装置用リー
ドフレームとしては、特願平１０−３３５４１６号公報
（以下、ロ号公報と呼ぶ）に「ニッケル又はニッケル合
金、銅又は銅合金、鉄又は鉄合金で形成されるリードフ
レームにおいて、インナーリード部に銀又は銀を含む合
金の表面処理層を設け、アウターリード部に少なくと
も、銀及び（１０１）面及び／又は（２１１）面に優先
配向した体心正方構造の錫を含む合金の表面処理層を設
けたことを特徴とするリードフレームを用いた半導体装
置」が開示されている。A conventional lead frame for a semiconductor device plated with an alloy obtained by adding silver to tin or an alloy obtained by adding copper to tin is disclosed in Japanese Patent Application No. 10-335416. In the lead frame formed of nickel or a nickel alloy, copper or a copper alloy, iron or an iron alloy, a surface treatment layer of silver or an alloy containing silver is provided on an inner lead portion, and at least silver is provided on an outer lead portion. And a (101) plane and / or a (211) plane provided with a surface treatment layer of an alloy containing tin having a body-centered square structure preferentially oriented, wherein a semiconductor device using a lead frame is disclosed. .

【００１１】[0011]

【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置用リードフレームは、以下のような課題
を有していた。However, the above-mentioned conventional lead frame for a semiconductor device has the following problems.

【００１２】（１）イ号公報に記載のリードフレーム
は、ゼロクロスタイムが２．３秒以上と長く、半導体装
置に使用するリードフレームとしては満足できる特性を
有していないという課題を有していた。(1) The lead frame described in the Japanese Patent Publication No. A has a problem that the zero cross time is as long as 2.3 seconds or more, and the lead frame used in a semiconductor device does not have satisfactory characteristics. Was.

【００１３】（２）イ号公報に記載のリードフレーム
は、光沢を上げるため光沢剤を添加すると、メッキ皮膜
中に有機物が入り、耐熱後に表面が酸化して変色し、半
田濡れ性が劣化しゼロクロスタイムが長くなるという課
題を有していた。(2) When a brightener is added to the lead frame described in the Japanese Patent Publication (A) to increase the gloss, organic substances enter the plating film, and after heat resistance, the surface is oxidized and discolored, and the solder wettability deteriorates. There was a problem that the zero cross time was long.

【００１４】（３）ロ号公報に記載のリードフレーム
は、電気メッキによりメッキする工程において、使用可
能な電流密度の範囲が２０〜２４Ａ／ｄｍ2であるため
メッキ速度が小さく、さらに量産性を高めるために十分
なメッキ速度を確保する必要があるという課題を有して
いた。(3) In the lead frame described in Japanese Patent Application Publication No. H11-207, in the step of plating by electroplating, the range of usable current density is 20 to 24 A / dm 2 , so that the plating speed is low and the mass productivity is further reduced. There was a problem that it was necessary to ensure a sufficient plating rate to increase the plating rate.

【００１５】本発明は上記従来の課題を解決するもの
で、環境有害物質の一つである鉛を含まない半導体装置
用リードフレームであって、半田濡れ性が良く、接合強
度が強く、低コストの半導体装置用リードフレームを提
供することを目的とする。The present invention solves the above-mentioned conventional problems, and is a lead frame for a semiconductor device which does not contain lead which is one of the environmentally harmful substances. The lead frame has good solder wettability, high bonding strength, and low cost. It is an object of the present invention to provide a semiconductor device lead frame.

【００１６】また、本発明は上記従来の課題を解決する
もので、環境有害物質の一つである鉛を含まない半導体
装置用リードフレームを製造方法であって、半田濡れ性
が良く、接合強度が強く、低コストの半導体装置用リー
ドフレームの製造方法を提供することを目的とする。Another object of the present invention is to provide a method for manufacturing a lead frame for a semiconductor device which does not contain lead, which is one of the environmentally harmful substances. It is an object of the present invention to provide a method for manufacturing a lead frame for a semiconductor device, which is strong and inexpensive.

【００１７】また、本発明は上記従来の課題を解決する
もので、環境有害物質の一つである鉛を含まない半導体
装置用リードフレームを使用した半導体装置であって、
半田濡れ性が良く、接合強度が強く、低コストの半導体
装置用リードフレームを使用した半導体装置を提供する
ことを目的とする。Another object of the present invention is to provide a semiconductor device using a lead frame for a semiconductor device which does not contain lead which is one of environmentally harmful substances.
An object of the present invention is to provide a semiconductor device using a low-cost semiconductor device lead frame having good solder wettability, high bonding strength, and low cost.

【００１８】[0018]

【課題を解決するための手段】上記課題を解決するため
に本発明の半導体装置用リードフレームは、銀又は銀を
含む合金の表面処理層Ａを設けたインナーリード部と、
銀又は銅と体心正方構造の錫とを含む合金の表面処理層
Ｂを設けたアウターリード部と、を有し、ニッケル、
銅、鉄、又はニッケル、銅、鉄のうち１以上を含む合金
で形成された板状素材を基材とした半導体装置用リード
フレームであって、前記表面処理層Ｂの最表面に、錫に
対する酸素の比が０．５から１．８で、かつ、厚さが１
〜２０ｎｍの錫の酸化層が形成されている構成を有して
いる。According to the present invention, there is provided a lead frame for a semiconductor device, comprising: an inner lead portion provided with a surface treatment layer A of silver or an alloy containing silver;
An outer lead portion provided with a surface treatment layer B of an alloy containing silver or copper and tin having a body-centered square structure, and nickel,
Copper, iron, or a lead frame for a semiconductor device based on a plate-like material formed of an alloy containing at least one of nickel, copper, and iron. The ratio of oxygen is 0.5 to 1.8 and the thickness is 1
It has a configuration in which a tin oxide layer of about 20 nm is formed.

【００１９】この構成により、環境有害物質の一つであ
る鉛を含まない半導体装置用リードフレームであって、
半田濡れ性が良く、接合強度が強く、低コストの半導体
装置用リードフレームを提供することができる。According to this structure, a lead frame for a semiconductor device that does not contain lead, which is one of environmentally harmful substances, is provided.
A lead frame for a semiconductor device having good solder wettability, high bonding strength, and low cost can be provided.

【００２０】また、上記課題を解決するために本発明の
半導体装置用リードフレームの製造方法は、前記アウタ
ーリード部の表面に設けられた前記表面処理層Ｂの最表
面に、錫に対する酸素の比が０．５から１．８で、か
つ、厚さが２０ｎｍ以下の錫の酸化層を形成するため
に、前記酸化層を水酸化ナトリウム又は三燐酸ナトリウ
ムを含む処理剤によって膨潤する工程と、電気化学的な
方法によりエッチング処理する工程と、を備えた構成を
有している。According to another aspect of the present invention, there is provided a method for manufacturing a lead frame for a semiconductor device, comprising the steps of: providing a surface treatment layer B provided on the surface of the outer lead portion with an oxygen to tin ratio at the outermost surface; Swelling the oxide layer with a treating agent containing sodium hydroxide or sodium triphosphate so as to form a tin oxide layer having a thickness of 0.5 to 1.8 and a thickness of 20 nm or less; And a step of performing an etching process by a chemical method.

【００２１】この構成により、環境有害物質の一つであ
る鉛を含まない半導体装置用リードフレームの製造方法
であって、半田濡れ性が良く、接合強度が強く、低コス
トの半導体装置用リードフレームの製造方法を提供する
ことができる。According to this structure, there is provided a method of manufacturing a lead frame for a semiconductor device which does not contain lead, which is one of the environmentally harmful substances, and which has good solder wettability, high bonding strength and low cost. Can be provided.

【００２２】また、上記課題を解決するために本発明の
半導体装置は、銀又は銀を含む合金の表面処理層Ａを設
けたインナーリード部と、銀又は銅と体心正方構造の錫
とを含む合金の表面処理層Ｂを設けたアウターリード部
と、を有し、ニッケル、銅、鉄、又はニッケル、銅、鉄
のうち１以上を含む合金で形成された板状素材を基材と
した半導体装置用リードフレームを用いて形成される半
導体装置であって、前記表面処理層Ｂの最表面に、錫に
対する酸素の比が０．５から１．８で、かつ、厚さが１
〜２０ｎｍの錫の酸化層が形成されていることを特徴と
する半導体装置用リードフレームを用いて形成される構
成を有している。According to another aspect of the present invention, there is provided a semiconductor device comprising: an inner lead portion provided with a surface treatment layer A of silver or an alloy containing silver; and silver or copper and tin having a body-centered square structure. And an outer lead portion provided with a surface treatment layer B of an alloy containing nickel, copper, iron, or a plate-shaped material formed of an alloy containing at least one of nickel, copper, and iron. A semiconductor device formed by using a semiconductor device lead frame, wherein a ratio of oxygen to tin is 0.5 to 1.8 and a thickness is 1 on the outermost surface of the surface treatment layer B.
It has a configuration formed using a lead frame for a semiconductor device, in which a tin oxide layer of about 20 nm is formed.

【００２３】この構成により、環境有害物質の一つであ
る鉛を含まない半導体装置用リードフレームを用いて形
成される半導体装置であって、半田付け性が良く、接合
強度が強く、低コストの半導体装置を提供することがで
きる。According to this structure, the semiconductor device is formed using a lead frame for a semiconductor device that does not contain lead, which is one of the environmentally harmful substances, and has good solderability, high bonding strength, and low cost. A semiconductor device can be provided.

【００２４】[0024]

【発明の実施の形態】本発明の請求項１に記載の半導体
装置用リードフレームは、銀又は銀を含む合金の表面処
理層Ａを設けたインナーリード部と、銀又は銅と体心正
方構造の錫とを含む合金の表面処理層Ｂを設けたアウタ
ーリード部と、を有し、ニッケル、銅、鉄、又はニッケ
ル、銅、鉄のうち１以上を含む合金で形成された板状素
材を基材とした半導体装置用リードフレームであって、
表面処理層Ｂの最表面に、錫に対する酸素の比が０．５
から１．８で、かつ、厚さが１〜２０ｎｍの錫の酸化層
が形成されている構成を有している。DETAILED DESCRIPTION OF THE INVENTION A lead frame for a semiconductor device according to the first aspect of the present invention has an inner lead portion provided with a surface treatment layer A of silver or an alloy containing silver, and a silver or copper and body-centered square structure. An outer lead portion provided with a surface treatment layer B of an alloy containing tin, and a plate-like material formed of nickel, copper, iron, or an alloy containing at least one of nickel, copper, and iron. A semiconductor device lead frame as a base material,
On the outermost surface of the surface treatment layer B, the ratio of oxygen to tin is 0.5
From 1.8 to 1.8 and a thickness of 1 to 20 nm.

【００２５】この構成により、以下のような作用を有す
る。This configuration has the following operation.

【００２６】（１）錫に対する酸素の比を０．５から
１．８とすることで、酸化層に溶融温度の高い安定した
ＳｎＯ2が生じることを防ぐことができるので、半田濡
れ性の劣化を防ぐことができる。(1) By setting the ratio of oxygen to tin to 0.5 to 1.8, it is possible to prevent the generation of stable SnO 2 having a high melting temperature in the oxide layer, so that the solder wettability is deteriorated. Can be prevented.

【００２７】（２）錫の酸化層の厚さを１〜２０ｎｍと
することで、酸化層は島状構造か島状構造に近い層状構
造となり、表面処理層の錫が表面に露出するか、また
は、露出に近い状態となっているため、溶融半田からの
拡散や共晶温度での溶融が容易に起こるので、半田濡れ
性を向上させることができる。(2) By setting the thickness of the tin oxide layer to 1 to 20 nm, the oxide layer has an island structure or a layer structure close to the island structure, and whether the tin of the surface treatment layer is exposed on the surface or not. Alternatively, since the state is close to the exposure, diffusion from the molten solder and melting at the eutectic temperature easily occur, so that the solder wettability can be improved.

【００２８】本発明の請求項２に記載の発明は、請求項
１に記載の半導体装置用リードフレームであって、アウ
ターリード部に設けられた表面処理層Ｂの銀含有率が１
〜８ｗｔ％、又は、銅含有率が０．１〜２ｗｔ％とする
構成を有している。According to a second aspect of the present invention, there is provided the semiconductor device lead frame according to the first aspect, wherein the surface treatment layer B provided on the outer lead portion has a silver content of 1%.
-8 wt%, or a copper content of 0.1-2 wt%.

【００２９】この構成により、請求項１の作用に加え、
以下のような作用を有する。With this configuration, in addition to the function of the first aspect,
It has the following functions.

【００３０】（１）表面処理層において、錫のウイスカ
が発生することを防止することができる。(1) The generation of tin whiskers in the surface treatment layer can be prevented.

【００３１】（２）表面処理層Ｂが銀と体心正方構造の
錫を含む合金で形成されていれば、ＩＣ駆動時におい
て、銀のエレクトロマイグレーションの発生を防ぐこと
ができる。(2) If the surface treatment layer B is formed of an alloy containing silver and tin having a body-centered square structure, electromigration of silver can be prevented during IC driving.

【００３２】本発明の請求項３に記載の発明は、請求項
１又は２に記載の半導体装置用リードフレームであっ
て、アウターリード部に設けられた表面処理層Ｂの厚さ
が３〜１５μｍに形成されている構成を有している。According to a third aspect of the present invention, there is provided the semiconductor device lead frame according to the first or second aspect, wherein the surface treatment layer B provided on the outer lead portion has a thickness of 3 to 15 μm. It has the configuration formed in.

【００３３】この構成により、請求項１又は２の作用に
加え、以下のような作用を有する。With this configuration, the following operation is obtained in addition to the operation of the first or second aspect.

【００３４】（１）リードフレーム基材の影響で半田濡
れ性が劣化することを防ぐことができる。(1) Deterioration of solder wettability due to the influence of the lead frame base material can be prevented.

【００３５】（２）アウターリード部に設けられる表面
処理層Ｂは柔らかい錫合金により形成されているので、
リードフレームをモールドする際のバリの発生を防止す
ることができる。(2) Since the surface treatment layer B provided on the outer lead portion is formed of a soft tin alloy,
Burrs at the time of molding the lead frame can be prevented.

【００３６】本発明の請求項４に記載の発明は、請求項
１乃至３の内いずれか１項に記載の半導体装置用リード
フレームであって、アウターリード部の表面に設けられ
た表面処理層Ｂが、白金、イリジウム、タンタル、ロジ
ウム、ルテニウム、又はこれらの酸化物のうち１以上を
含む不溶解性電極を陽極電極に用いた電気メッキにより
形成されたものであることを特徴とする構成を有してい
る。According to a fourth aspect of the present invention, there is provided the lead frame for a semiconductor device according to any one of the first to third aspects, wherein the surface treatment layer is provided on the surface of the outer lead portion. B is platinum, iridium, tantalum, rhodium, ruthenium, or a configuration characterized by being formed by electroplating using an insoluble electrode containing at least one of these oxides as an anode electrode. Have.

【００３７】この構成により、請求項１乃至３の内いず
れか１項の作用に加え、以下の作用を有する。According to this configuration, the following operation is obtained in addition to the operation of any one of the first to third aspects.

【００３８】（１）溶解性電極を陽極電極に用いた場合
に比べ、電極の交換を頻繁に行う必要がないので、量産
性を向上させることができる。(1) Compared to the case where a soluble electrode is used as the anode electrode, it is not necessary to replace the electrode frequently, so that mass productivity can be improved.

【００３９】（２）半田液中に含まれる酸化防止剤等の
分解を抑止することで、４価の酸化錫の発生を防止する
ため、安定した表面処理層Ｂを形成することができる。(2) A stable surface treatment layer B can be formed in order to prevent the generation of tetravalent tin oxide by suppressing the decomposition of the antioxidant and the like contained in the solder liquid.

【００４０】本発明の請求項５に記載の発明は、請求項
１乃至４の内いずれか１項に記載の半導体装置用リード
フレームであって、アウターリード部の表面に設けられ
た表面処理層Ｂの最表面に形成された酸化層は、水酸化
ナトリウム又は三燐酸ナトリウムを含む処理剤によって
膨潤され、電気化学的な方法によりエッチング処理され
て形成された構成を有している。According to a fifth aspect of the present invention, there is provided the lead frame for a semiconductor device according to any one of the first to fourth aspects, wherein the surface treatment layer is provided on the surface of the outer lead portion. The oxide layer formed on the outermost surface of B has a configuration formed by being swollen by a processing agent containing sodium hydroxide or sodium triphosphate and etched by an electrochemical method.

【００４１】この構成により、請求項１乃至４の内いず
れか１項の作用に加え、以下のような作用を有する。According to this configuration, the following operation is obtained in addition to the operation of any one of the first to fourth aspects.

【００４２】（１）電気メッキにより表面処理層が形成
された後に表面が酸化されて形成される疎で厚い酸化層
を取り除くことができるので、その後に密で均一な酸化
層を形成させることができ、半田濡れ性を向上させるこ
とができる。(1) Since a sparse and thick oxide layer formed by oxidizing the surface after the surface treatment layer is formed by electroplating can be removed, a dense and uniform oxide layer can be formed thereafter. Therefore, solder wettability can be improved.

【００４３】（２）電気メッキにより表面処理層が形成
された後に表面が酸化されて形成される疎で厚い酸化層
を取り除くことができるので、疎で厚い酸化層がモール
ド時に金型へ付着することを防止することができる。(2) Since the sparse and thick oxide layer formed by oxidizing the surface after the surface treatment layer is formed by electroplating can be removed, the sparse and thick oxide layer adheres to the mold during molding. Can be prevented.

【００４４】ここで、電気化学的な方法としては、コハ
ク酸イミド等や非コハク酸タイプの処理剤を用いて、ニ
ッケル、銅、鉄の酸化還元電位を高くし、酸化層を還元
する方法等が用いられる。Here, as an electrochemical method, a method of reducing the oxide layer by increasing the oxidation-reduction potential of nickel, copper, or iron using a succinimide or the like or a non-succinic acid type treating agent is used. Is used.

【００４５】本発明の請求項６に記載の半導体装置用リ
ードフレームの製造方法は、アウターリード部の表面に
設けられた表面処理層Ｂの最表面に、錫に対する酸素の
比が０．５から１．８で、かつ、厚さが２０ｎｍ以下の
錫の酸化層を形成するために、酸化層を水酸化ナトリウ
ム又は三燐酸ナトリウムを含む処理剤によって膨潤する
工程と、電気化学的な方法によりエッチング処理する工
程を備えた構成を有している。According to a sixth aspect of the present invention, in the method of manufacturing a lead frame for a semiconductor device, the outermost surface of the surface treatment layer B provided on the surface of the outer lead portion has an oxygen to tin ratio of 0.5 to 0.5. A step of swelling the oxide layer with a treating agent containing sodium hydroxide or sodium triphosphate to form a tin oxide layer having a thickness of 1.8 nm or less and etching by an electrochemical method It has a configuration provided with a processing step.

【００４６】この構成により、以下のような作用を有す
る。This configuration has the following operation.

【００４７】（１）電気メッキにより表面処理層が形成
された後に表面が酸化されて形成される疎で厚い酸化層
を取り除くことができるので、その後に密で均一な酸化
層を形成させることができ、半田濡れ性を向上させるこ
とができる。(1) Since a sparse and thick oxide layer formed by oxidizing the surface after the surface treatment layer is formed by electroplating can be removed, a dense and uniform oxide layer can be formed thereafter. Therefore, solder wettability can be improved.

【００４８】本発明の請求項７に記載の半導体装置は、
請求項１乃至５に記載の半導体装置用リードフレームを
用いて形成される構成を有している。A semiconductor device according to a seventh aspect of the present invention comprises:
The semiconductor device has a configuration formed using the semiconductor device lead frame according to the first to fifth aspects.

【００４９】この構成により、以下のような作用を有す
る。With this configuration, the following operations are provided.

【００５０】（１）錫に対する酸素の比を０．５から
１．８とすることで、酸化層に溶融温度の高い安定した
ＳｎＯ2が生じることを防ぐことができるので、半田濡
れ性の劣化を防ぐことができ、半田付け性を向上させる
ことができる。(1) By setting the ratio of oxygen to tin to 0.5 to 1.8, it is possible to prevent the generation of stable SnO 2 having a high melting temperature in the oxide layer, so that the solder wettability is deteriorated. Can be prevented, and the solderability can be improved.

【００５１】（２）錫の酸化層の厚さを２０ｎｍ以下と
することで、酸化層は島状構造か島状構造に近い層状構
造となり、表面処理層の錫が表面に露出するため、溶融
半田からの拡散や共晶温度での溶融が容易に起こるの
で、半田濡れ性を向上させることができ、半田付け性を
向上させることができる。(2) By setting the thickness of the tin oxide layer to 20 nm or less, the oxide layer has an island structure or a layer structure close to the island structure, and tin of the surface treatment layer is exposed on the surface. Since diffusion from the solder and melting at the eutectic temperature easily occur, the solder wettability can be improved, and the solderability can be improved.

【００５２】（３）表面処理層において、錫のウイスカ
が発生することを防止することができるので、半導体装
置の錫のウイスカの発生による短絡事故を防ぐことがで
きる。(3) Since the generation of tin whiskers in the surface treatment layer can be prevented, a short circuit accident due to the generation of tin whiskers in the semiconductor device can be prevented.

【００５３】（４）ＩＣ駆動時の銀のエレクトロマイグ
レーションの発生を防ぐことができるので、モールド樹
脂内における短絡事故を防止することができるという作
用を有する。(4) Since the occurrence of silver electromigration at the time of driving the IC can be prevented, a short circuit accident in the mold resin can be prevented.

【００５４】（５）モールド樹脂の封止工程で金型の隙
間から樹脂が漏出することを防ぐことができるので、確
実に、モールド樹脂によりＩＣの封止を行うことがで
き、リードフレームをモールド封止する工程に発生する
バリを除去する工程を省略することができる。(5) Since the resin can be prevented from leaking out of the gap of the mold in the molding resin sealing step, the IC can be securely sealed with the molding resin, and the lead frame can be molded. The step of removing burrs generated in the step of sealing can be omitted.

【００５５】（６）溶解性電極を陽極電極に用いた場合
に比べ、電極の交換を頻繁に行う必要がないので、量産
性を向上させることができるという作用を有する。(6) Compared to the case where a dissolvable electrode is used as the anode electrode, it is not necessary to replace the electrode more frequently, so that there is an effect that the mass productivity can be improved.

【００５６】（７）電気メッキにより表面処理層が形成
された後に表面が酸化されて形成される疎で厚い酸化層
を取り除くことができるので、その後に密で均一な酸化
層を形成させることができ、半田濡れ性を向上させるこ
とができ、半田付け性を向上させることができる。(7) Since the surface is oxidized after the surface treatment layer is formed by electroplating and the sparse and thick oxide layer formed can be removed, a dense and uniform oxide layer can be formed thereafter. Accordingly, solder wettability can be improved, and solderability can be improved.

【００５７】以下に本発明の一実施の形態について説明
する。Hereinafter, an embodiment of the present invention will be described.

【００５８】（実施の形態１）図１は本発明の実施の形
態１におけるリードフレームの平面図であり、図２は本
発明の実施の形態１におけるリードフレームの模式断面
図である。(Embodiment 1) FIG. 1 is a plan view of a lead frame according to Embodiment 1 of the present invention, and FIG. 2 is a schematic cross-sectional view of the lead frame according to Embodiment 1 of the present invention.

【００５９】図１及び図２において、１は本実施の形態
１における半導体装置用リードフレーム、２はアウター
リード部、３はインナーリード部、４は集積回路が載置
されるパッド、５はリードフレーム基材、６はインナー
リード部３の表面に設けられた銀の表面処理層であるＡ
ｇ層、７はアウターリード部２の表面に設けられた銀及
び錫を含む表面処理層であるＳｎ−Ａｇ層、７ａはＳｎ
−Ａｇ層７の表面に形成された酸化層である。1 and 2, reference numeral 1 denotes a lead frame for a semiconductor device according to the first embodiment, 2 denotes an outer lead portion, 3 denotes an inner lead portion, 4 denotes a pad on which an integrated circuit is mounted, and 5 denotes a lead. The frame base material 6 is a silver surface treatment layer A provided on the surface of the inner lead portion 3.
g layer, 7 is a Sn-Ag layer which is a surface treatment layer containing silver and tin provided on the surface of the outer lead portion 2, and 7a is Sn
-An oxide layer formed on the surface of the Ag layer 7;

【００６０】ここで、本実施の形態１におけるリードフ
レーム基材５は、プレス工程により、アロイ１９４合金
の薄板をリードフレームの形状に加工し、洗浄工程を経
て、必要に応じて熱処理工程により、プレス工程におい
てプレスで打ち抜いたときに生じた変形を修正し、形成
される。Here, the lead frame base material 5 according to the first embodiment is formed by processing a thin plate of an alloy 194 alloy into a lead frame shape by a pressing step, passing through a cleaning step, and optionally performing a heat treatment step. It is formed by correcting the deformation caused by punching in the press process.

【００６１】以上のように構成された半導体装置用リー
ドフレームについて、以下その製造方法について説明す
る。A method of manufacturing the semiconductor device lead frame configured as described above will be described below.

【００６２】まず、プレス工程や熱処理工程においてリ
ードフレーム基材５に付着した油性分を、アルカリ脱脂
剤等による浸漬法又は電気的な方法の併用又は単独使用
により除去した後、銅下地メッキを０．２μｍ以上形成
する。銅の下地メッキは、シアン化銅浴をもちいて、浴
温４０℃、電流密度１５Ａ／ｄｍ2で行った。First, the oily components adhering to the lead frame base material 5 in the pressing step or the heat treatment step are removed by a dipping method using an alkaline degreasing agent or the like or by an electric method, or the copper base plating is removed. 2 .mu.m or more. The copper base plating was performed at a bath temperature of 40 ° C. and a current density of 15 A / dm 2 using a copper cyanide bath.

【００６３】その後、銀のメッキ工程によりインナーリ
ード部３に、銀メッキによりＡｇ層６を８μｍ形成す
る。銀メッキは、シアン化銀浴をもちいて、浴温４０
℃、電流密度３０Ａ／ｄｍ2で行った。Thereafter, an Ag layer 6 of 8 μm is formed on the inner lead portion 3 by silver plating in a silver plating step. Silver plating uses a silver cyanide bath, bath temperature 40
C. and a current density of 30 A / dm 2 .

【００６４】銀メッキを行いＡｇ層６を形成した後、ア
ウターリード部２と、その表面に形成される銀及び錫を
含むＳｎ−Ａｇ層７と、の密着性を向上させるため、塩
酸、硝酸、硫酸の内１種又は２種以上から選択された処
理剤によって、アウターリード部２の表面をエッチング
処理する。本実施の形態においては、塩酸を１０ｇ／Ｌ
含む３０℃の処理剤により１５秒間、表面に付着した不
純物を除去するとともに、表面をエッチングする。これ
により、アンカー効果によって、アウターリード部２
と、銀及び錫を含むＳｎ−Ａｇ層７と、の密着性を改善
する。After silver plating is performed to form the Ag layer 6, hydrochloric acid, nitric acid, and the like are used to improve the adhesion between the outer lead portion 2 and the Sn—Ag layer 7 containing silver and tin formed on the outer lead portion 2. The surface of the outer lead portion 2 is etched with a treating agent selected from one or more of sulfuric acid. In the present embodiment, hydrochloric acid is added at 10 g / L.
Impurities adhering to the surface are removed for 15 seconds using a treating agent at 30 ° C. and the surface is etched. Thereby, the outer lead portion 2 is formed by the anchor effect.
And the Sn—Ag layer 7 containing silver and tin is improved in adhesion.

【００６５】この処理の後に、アウターリード部２にＳ
ｎ−Ａｇ層７を電気メッキにより形成する。メッキ液の
組成としては、酸が５０〜２００ｇ／Ｌ、錫金属が２０
〜６０ｇ／Ｌ、銀金属が０．５〜３ｇ／Ｌの範囲で用い
る。なお、酸としては、アルカンスルホン酸、アルカノ
ールスルホン酸、及びスルファミン酸より任意に選択で
き、錫塩としては、メタンスルホン酸錫、ＳｎＯより任
意に選択でき、銀塩としては、メタンスルホン酸銀、Ａ
ｇ2Ｏより任意に選択できる。本実施の形態において
は、酸としてメタンスルホン酸１５０ｇ／Ｌを使用し、
ＳｎＯの濃度は金属錫の量にして４０ｇ／Ｌとなるよう
にし、Ａｇ2Ｏの濃度は金属銀の量にして１．５ｇ／Ｌ
となるようにした。After this processing, the outer lead portion 2
The n-Ag layer 7 is formed by electroplating. The composition of the plating solution is such that the acid is 50 to 200 g / L and the tin metal is 20 g / L.
６０60 g / L and silver metal in the range of 0.5 to 3 g / L. The acid can be arbitrarily selected from alkanesulfonic acid, alkanolsulfonic acid, and sulfamic acid, the tin salt can be arbitrarily selected from tin methanesulfonate, SnO, and the silver salt is silver methanesulfonate, A
It can be arbitrarily selected from g 2 O. In the present embodiment, methanesulfonic acid 150 g / L is used as the acid,
The concentration of SnO was set to be 40 g / L in the amount of metallic tin, and the concentration of Ag 2 O was set to 1.5 g / L in the amount of metallic silver.
It was made to become.

【００６６】添加剤としては、少なくとも、銀の安定剤
として、硫黄化合物、チオアミド化合物、チオール化合
物、チオ硫酸塩の内１種又は２種以上添加し、錫の安定
剤として、カルボン酸、スルファミン酸、ピロリン酸
塩、キレート剤の内１種又は２種以上添加し、結晶調整
剤として、芳香族スルホン酸塩、脂肪族スルホン酸塩、
ヒダトイン化合物、システイン化合物、芳香族有機アミ
ン、脂肪族アルデヒド、芳香族アルデヒド、非イオン界
面活性剤、両性イオン界面活性剤、アニオン界面活性剤
の内１種又は２種以上を添加できる。本実施の形態で
は、銀の安定剤として２アミノベンゼンチオール３ｇ／
Ｌ、錫の安定剤としてナフタレンスルホン酸モノポリエ
チレングリコールエーテル５ｇ／Ｌ、結晶調整剤として
ビスフェノールＡジポリエチレングリコールエーテル８
０ｇ／Ｌを添加した。特に、銀の安定剤である２アミノ
ベンゼンチオールは４ｇ／Ｌ以上添加すると結晶配向性
が不安定になり、表面の光沢が失われ、黄色に変色し、
半田濡れ性の低下が起こり、１ｇ／Ｌ以下の添加である
とメッキ液の安定性が損なわれ、銀、銅がメタルとなっ
て沈殿する、という現象が起こる。As additives, at least one or more of a sulfur compound, a thioamide compound, a thiol compound and a thiosulfate are added as a silver stabilizer, and a carboxylic acid, a sulfamic acid is used as a tin stabilizer. , Pyrophosphate, one or more chelating agents are added, and as a crystal modifier, an aromatic sulfonate, an aliphatic sulfonate,
One or more of a hydatoin compound, a cysteine compound, an aromatic organic amine, an aliphatic aldehyde, an aromatic aldehyde, a nonionic surfactant, a zwitterionic surfactant and an anionic surfactant can be added. In the present embodiment, 3 g of 2 aminobenzenethiol /
5 g / L of naphthalenesulfonic acid monopolyethylene glycol ether as a stabilizer for L and tin, and 8 g of bisphenol A dipolyethylene glycol ether as a crystal modifier
0 g / L was added. In particular, when 4 g / L or more of 2 aminobenzenethiol, which is a silver stabilizer, is added, the crystal orientation becomes unstable, the surface gloss is lost, and the color changes to yellow,
If the addition is less than 1 g / L, the stability of the plating solution will be impaired and silver and copper will precipitate as metals.

【００６７】メッキ方法は、スパージャを使用した噴流
メッキを行い、メッキ液の流量を４００Ｌ／ｍｉｎと
し、メッキ液の液温２５℃とした。また、電流密度は６
０Ａ／ｄｍ2とした。陽極電極は、白金、イリジウム、
タンタル、ロジウム、ルテニウム、又はその酸化物のう
ち一つ以上を含む不溶解性電極から任意に選択できる。
本実施の形態においては、陽極電極として、チタンの生
地に酸化イリジウムと酸化タンタルの混合物を被覆した
不溶解性電極を使用した。本実施の形態では、銀含有率
２．５％で８μｍのＳｎ−Ａｇ層を形成した。The plating method was jet plating using a sparger, the flow rate of the plating solution was 400 L / min, and the temperature of the plating solution was 25 ° C. The current density is 6
It was set to 0 A / dm 2 . The anode electrode is platinum, iridium,
It can be arbitrarily selected from an insoluble electrode containing one or more of tantalum, rhodium, ruthenium, or an oxide thereof.
In this embodiment, an insoluble electrode in which a mixture of iridium oxide and tantalum oxide is coated on a titanium material is used as the anode electrode. In the present embodiment, a Sn-Ag layer having a silver content of 2.5% and a thickness of 8 μm was formed.

【００６８】以上のようにして、アウターリード部２の
表面にＳｎ−Ａｇ層７が形成される。As described above, the Sn—Ag layer 7 is formed on the surface of the outer lead portion 2.

【００６９】続いて、Ｓｎ−Ａｇ層７の最表面に形成さ
れた酸化層７ａをエッチングするための工程を説明す
る。まず、前処理として水酸化ナトリウムを含む処理液
か、または、三燐酸ナトリウムを含む処理液で処理す
る。具体的には、濃度が１２０ｇ／Ｌ、液温が６０℃の
三燐酸ナトリウムに３０秒間浸漬して、Ｓｎ−Ａｇ層７
の最表面の酸化層を膨潤させる処理を行う。Next, a process for etching the oxide layer 7a formed on the outermost surface of the Sn-Ag layer 7 will be described. First, as a pretreatment, a treatment liquid containing sodium hydroxide or a treatment liquid containing sodium triphosphate is used. Specifically, the Sn—Ag layer 7 was immersed in sodium triphosphate having a concentration of 120 g / L and a liquid temperature of 60 ° C. for 30 seconds.
Is performed to swell the oxide layer on the outermost surface.

【００７０】つぎに、Ｓｎ−Ａｇ層７の最表面の酸化層
を、コハク酸イミド又は非コハク酸タイプの処理剤を用
い、ニッケル、銅、鉄等の酸化還元電位を高くし、酸化
層７ａを還元しエッチング処理する。これにより、Ｓｎ
−Ａｇ層７の最表面に形成された酸化層７ａの厚さを１
〜２０ｎｍとすることができる。Next, the oxidation-reduction potential of nickel, copper, iron or the like is increased by using a succinimide or non-succinic acid type treating agent to form an oxide layer 7a on the outermost surface of the Sn—Ag layer 7. Is reduced and etched. Thereby, Sn
The thickness of the oxide layer 7a formed on the outermost surface of the Ag layer 7 is 1
２０20 nm.

【００７１】さらに、Ｓｎ−Ａｇ層７の最表面の有機不
純物を取り除く工程を設ける。具体的には、液温が４０
℃の１０％硫酸に１５秒間浸漬して、有機不純物及び酸
化物を除去し、その後、窒素系の有機物によりＳｎ−Ａ
ｇ層７の酸化を防止するためのアミン系有機物コート処
理を行った。Further, a step of removing organic impurities on the outermost surface of the Sn—Ag layer 7 is provided. Specifically, when the liquid temperature is 40
The substrate was immersed in 10% sulfuric acid at 15 ° C. for 15 seconds to remove organic impurities and oxides.
An amine organic material coating treatment for preventing oxidation of the g layer 7 was performed.

【００７２】ここで、以上のようにして形成された本実
施の形態の半導体装置用リードフレームのＳｎ−Ａｇ層
７の深さ方向の組成を、図を用いて説明する。Here, the composition in the depth direction of the Sn-Ag layer 7 of the semiconductor device lead frame of the present embodiment formed as described above will be described with reference to the drawings.

【００７３】図４は本発明の実施の形態１における酸化
層の組成とその深さとの関係を示した関係図で、オージ
ェ電子分光法によりＳｎ−Ａｇ層７の最表面に形成され
た酸化層７ａの組成を分析し、その深さとの関係を示し
た図である。FIG. 4 is a relationship diagram showing the relationship between the composition of the oxide layer and its depth in the first embodiment of the present invention. The oxide layer formed on the outermost surface of Sn—Ag layer 7 by Auger electron spectroscopy. FIG. 7 is a diagram showing the relationship between the composition and the depth of the composition 7a.

【００７４】図４において、縦軸は組成を全体に対する
各元素の原子の個数比で示し、横軸は酸化層７ａの深さ
を・で示した。In FIG. 4, the vertical axis indicates the composition by the number ratio of the atoms of each element to the whole, and the horizontal axis indicates the depth of the oxide layer 7a.

【００７５】これにより、酸化層７ａは深さ５０・まで
は組成が一定であり、深さ１００・では酸素が著しく少
なく、酸化層７ａが形成されていないことが分かる。From this, it can be seen that the composition of the oxide layer 7a is constant up to a depth of 50. The oxygen content is extremely small at a depth of 100. The oxide layer 7a is not formed.

【００７６】以上のようにして製造された本実施の形態
の半導体装置用リードフレームの、Ｓｎ−Ａｇ層７の半
田濡れ性の測定方法を説明する。A method for measuring the solder wettability of the Sn—Ag layer 7 of the lead frame for a semiconductor device of the present embodiment manufactured as described above will be described.

【００７７】まず、表面処理層を形成した半導体装置用
リードフレーム１のアウターリード部２のみを切断して
半田濡れ試験装置に装着し、ＪＩＳ Ｃ ００５３規定
の平衡法による半田濡れ試験方法により、初期及び１７
５℃２４時間耐熱後のゼロクロスタイムを測定した。半
田濡れ試験装置は、タルチン製のＳＷＥＴ１００を用
い、条件としては、半田浴温度を２３０℃、降下スピー
ドを１０ｍｍ／ｓｅｃ、上昇スピードを４ｍｍ／ｓｅ
ｃ、浸漬時間を０．２ｓｅｃとして測定した。半田は錫
−鉛（Ｈ６３Ｓ）半田を用い、フラックスはＲ−１００
−４０（非ハロゲン）を用いた。First, only the outer lead portion 2 of the lead frame 1 for a semiconductor device on which the surface treatment layer is formed is cut and mounted on a solder wetting test device, and the initial condition is determined by the solder wetting test method according to the equilibrium method specified in JIS C 0053. And 17
The zero cross time after heat resistance at 5 ° C. for 24 hours was measured. The solder wetting test device used was SWET100 made of Tartin, and the conditions were a solder bath temperature of 230 ° C., a descent speed of 10 mm / sec, and a rising speed of 4 mm / sec.
c, The immersion time was measured at 0.2 sec. The solder used is tin-lead (H63S) solder, and the flux is R-100.
-40 (non-halogen) was used.

【００７８】この測定結果を（表１）に試験例１として
示す。この試験例１は、本実施の形態の半導体装置用リ
ードフレーム１は、初期及び１７５℃２４時間耐熱後の
ゼロクロスタイムが０．５秒を下回っており、十分な半
田濡れ性を有していることを示す。The measurement results are shown in Table 1 as Test Example 1. In Test Example 1, the lead frame 1 for a semiconductor device of the present embodiment has a zero cross time of less than 0.5 seconds at the initial stage and after heat resistance at 175 ° C. for 24 hours, and has sufficient solder wettability. Indicates that

【００７９】[0079]

【表１】 [Table 1]

【００８０】（比較例１）比較例１の半導体装置用リー
ドフレームについて説明する。(Comparative Example 1) A lead frame for a semiconductor device of Comparative Example 1 will be described.

【００８１】本比較例では、アロイ１９４合金をリード
フレーム基材５として用い、プレス工程によりリードフ
レームの形状に加工され、洗浄工程を経て、必要に応じ
て熱処理工程により、プレス工程においてプレスで打ち
抜いたときに生じた変形を修正し、形成される。In this comparative example, an alloy 194 alloy was used as the lead frame base material 5, processed into the shape of a lead frame by a pressing step, passed through a cleaning step, and if necessary, by a heat treatment step, and punched out by a press in the pressing step. The deformation that occurs when it is corrected is formed.

【００８２】つぎに、プレス工程や熱処理工程において
リードフレーム基材５に付着した油性分を、アルカリ脱
脂剤等による浸漬法又は電気的な方法の併用又は単独使
用により除去した後、実施の形態１と同様の方法によ
り、銅下地メッキを０．２μｍ以上形成し、続いてイン
ナーリード部の表面に銀メッキによりＡｇ層６を８μｍ
形成する。Next, in the pressing step and the heat treatment step, the oily components adhering to the lead frame base material 5 were removed by a dipping method using an alkaline degreasing agent or the like, or by using an electric method together or independently. In the same manner as described above, a copper base plating is formed to a thickness of 0.2 μm or more.
Form.

【００８３】Ａｇ層６を形成した後、アウターリード部
２と、その表面に形成される銀及び錫を含むＳｎ−Ａｇ
層７と、の密着性を向上させるため、塩酸、硝酸、硫酸
の内１種又は２種以上から選択された処理剤によって、
実施の形態１と同様の方法によりアウターリード部２の
表面をエッチング処理する。After the Ag layer 6 is formed, the outer lead portion 2 and a Sn-Ag containing silver and tin formed on its surface are formed.
In order to improve the adhesion with the layer 7, by using a treatment agent selected from one or more of hydrochloric acid, nitric acid, and sulfuric acid,
The surface of the outer lead portion 2 is etched by the same method as in the first embodiment.

【００８４】続いて、アウターリード部２にＳｎ−Ａｇ
層７を電気メッキにより形成する。メッキ液は、酸とし
てメタンスルホン酸１５０ｇ／Ｌを使用し、ＳｎＯの濃
度は金属錫の量にして４０ｇ／Ｌとなるようにし、Ａｇ
2Ｏの濃度は金属銀の量にして１．５ｇ／Ｌとなるよう
にした。Subsequently, Sn-Ag is applied to the outer lead portion 2.
The layer 7 is formed by electroplating. The plating solution used was 150 g / L of methanesulfonic acid as an acid, and the concentration of SnO was adjusted to be 40 g / L in terms of the amount of metallic tin.
The concentration of 2 O was adjusted to 1.5 g / L in terms of the amount of metallic silver.

【００８５】添加剤としては、銀の安定剤としてアミノ
フェニルジスルフィド５ｇ／Ｌ、錫の安定剤としてナフ
タレンスルホン酸モノポリエチレングリコールエーテル
５ｇ／Ｌ、結晶調整剤としてビスフェノールＡジポリエ
チレングリコールエーテル８０ｇ／Ｌを添加した。陽極
電極は、チタンの生地に酸化イリジウムと酸化タンタル
の混合物を被覆した不溶解性電極を使用した。As additives, 5 g / L of aminophenyl disulfide as a silver stabilizer, 5 g / L of naphthalene sulfonic acid monopolyethylene glycol ether as a stabilizer of tin, and 80 g / L of bisphenol A dipolyethylene glycol ether as a crystal modifier were used. Was added. As the anode electrode, an insoluble electrode in which a mixture of iridium oxide and tantalum oxide was coated on a titanium fabric was used.

【００８６】メッキ方法は、スパージャを使用した噴流
メッキを行い、メッキ液の流量を４００Ｌ／ｍｉｎと
し、メッキ液の液温２５℃とした。また、電流密度は２
０Ａ／ｄｍ2とした。また、本比較例では、銀含有率
２．５％で８μｍのＳｎ−Ａｇ層７を形成した。The plating method was jet plating using a sparger, the flow rate of the plating solution was 400 L / min, and the temperature of the plating solution was 25 ° C. The current density is 2
It was set to 0 A / dm 2 . In this comparative example, the Sn—Ag layer 7 having a silver content of 2.5% and a thickness of 8 μm was formed.

【００８７】ここで、Ｓｎ−Ａｇ層７の表面に形成され
た酸化層７ａをエッチングする工程を省略し、Ｓｎ−Ａ
ｇ層７を変色防止剤に浸漬した後、洗浄し乾燥させて、
仕上げた。Here, the step of etching the oxide layer 7a formed on the surface of the Sn-Ag layer 7 is omitted, and the Sn-Ag layer 7 is omitted.
g layer 7 is immersed in a discoloration inhibitor, washed and dried,
Finished.

【００８８】以上のようにして形成された本比較例の半
導体装置用リードフレームのＳｎ−Ａｇ層７の深さ方向
の組成を、図を用いて説明する。The composition in the depth direction of the Sn—Ag layer 7 of the semiconductor device lead frame of the comparative example formed as described above will be described with reference to the drawings.

【００８９】図５は比較例１における酸化層の組成とそ
の深さとの関係を示した関係図で、オージェ電子分光法
によりＳｎ−Ａｇ層の最表面に形成された酸化層の組成
を分析し、その深さとの関係を示した図である。FIG. 5 is a relationship diagram showing the relationship between the composition of the oxide layer and the depth in Comparative Example 1. The composition of the oxide layer formed on the outermost surface of the Sn—Ag layer was analyzed by Auger electron spectroscopy. FIG. 4 is a diagram showing a relationship between the depth and the depth.

【００９０】図５において、縦軸は組成を全体に対する
各元素の原子の個数比で示し、横軸は酸化層７ａの深さ
を・で示した。In FIG. 5, the vertical axis indicates the composition by the number ratio of atoms of each element to the whole, and the horizontal axis indicates the depth of the oxide layer 7a.

【００９１】これにより、酸化層７ａが深さ３００・近
傍まで形成されていることが分かる。Thus, it can be seen that the oxide layer 7a is formed to a depth of about 300.

【００９２】以上のように構成された本比較例の半導体
装置用リードフレーム１のアウターリード部２に設けら
れた表面処理層の半田濡れ性の測定は実施の形態１と同
様の方法により行われる。The measurement of the solder wettability of the surface treatment layer provided on the outer lead portion 2 of the semiconductor device lead frame 1 of the comparative example having the above-described configuration is performed by the same method as in the first embodiment. .

【００９３】この測定結果を（表１）に比較例１として
示す。この比較例１は、本比較例の半導体装置用リード
フレーム１は、初期ゼロクロスタイムが１秒を上回って
いる上、１７５℃２４時間耐熱後のゼロクロスタイムが
５秒と劣化が著しく、十分な半田濡れ性を有していない
ことを示す。The measurement results are shown in Table 1 as Comparative Example 1. In Comparative Example 1, the lead frame 1 for a semiconductor device of this comparative example had an initial zero-cross time exceeding 1 second, and the zero-cross time after heat resistance at 175 ° C. for 24 hours was 5 seconds. Indicates that it does not have wettability.

【００９４】半田濡れ性は１．０秒以下であれば十分で
あると考えられるので、（表１）から分かるように、試
験例１は半導体装置用リードフレーム１として良好であ
り、比較例１は不良であることを示す。また、比較例１
の半導体装置用リードフレーム１は、耐熱後の劣化が著
しく、耐熱性が要求される半導体装置用リードフレーム
１として不良である。すなわち、Ｓｎ−Ａｇ層７を形成
した後で、その表面を処理することにより、錫に対する
酸素の比を０．５から１．８とし、厚さを２０ｎｍ以下
とした酸化層７ａを形成することで、半田濡れ性及び耐
熱性を向上させた半導体装置用リードフレーム１が得ら
れることが分かる。Since it is considered that the solder wettability of 1.0 second or less is sufficient, as can be seen from Table 1, Test Example 1 is good as the lead frame 1 for a semiconductor device, and Comparative Example 1 Indicates a failure. Comparative Example 1
The semiconductor device lead frame 1 significantly deteriorates after heat resistance, and is defective as a semiconductor device lead frame 1 requiring heat resistance. That is, after forming the Sn—Ag layer 7, the surface thereof is treated to form an oxide layer 7a having an oxygen to tin ratio of 0.5 to 1.8 and a thickness of 20 nm or less. It can be seen that the lead frame 1 for a semiconductor device with improved solder wettability and heat resistance can be obtained.

【００９５】なお、本実施の形態では、インナーリード
部３のみにＡｇ層６を形成したが、これはパッド４の一
部にを覆っても良く、パッド４全体を覆っても良い。In the present embodiment, the Ag layer 6 is formed only on the inner lead portion 3. However, the Ag layer 6 may cover a part of the pad 4 or may cover the entire pad 4.

【００９６】また、本実施の形態では、電気メッキによ
りＳｎ−Ａｇ層７を形成したが、これは、物理蒸着、ス
パッタリング、ＣＶＤ等の方法で形成しても良い。In the present embodiment, the Sn—Ag layer 7 is formed by electroplating, but may be formed by a method such as physical vapor deposition, sputtering, or CVD.

【００９７】以上のように本実施の形態によれば、アウ
ターリード部２のＳｎ−Ａｇ層７の最表面に形成される
酸化層７ａを、エッチング処理することにより、錫に対
する酸素の比が０．５から１．８で、かつ、厚さが２０
ｎｍ以下となるように形成することにより、錫の酸化層
に溶融温度の高い安定したＳｎＯ2が生じることを防ぐ
ことができるので、半田濡れ性の劣化を防ぐことがで
き、また、酸化層７ａは島状構造か島状構造に近い層状
構造となり、表面処理層の錫が表面に露出するため、溶
融半田からの拡散や共晶温度での溶融が容易に起こるの
で、半田濡れ性を向上させることができる。As described above, according to the present embodiment, the oxide layer 7a formed on the outermost surface of the Sn—Ag layer 7 of the outer lead portion 2 is etched to reduce the ratio of oxygen to tin to 0. 0.5 to 1.8 and a thickness of 20
When the thickness is set to be equal to or less than nm, it is possible to prevent generation of stable SnO 2 having a high melting temperature in the tin oxide layer, so that deterioration of solder wettability can be prevented, and the oxide layer 7a can be prevented. Has an island structure or a layer structure similar to an island structure, and since tin of the surface treatment layer is exposed on the surface, diffusion from molten solder and melting at a eutectic temperature easily occur, thereby improving solder wettability. be able to.

【００９８】（実施の形態２）図３は、本発明の実施の
形態２における半導体装置の模式断面図である。(Embodiment 2) FIG. 3 is a schematic sectional view of a semiconductor device according to Embodiment 2 of the present invention.

【００９９】図３において、２はアウターリード部、３
はインナーリード部、４はパッド、５はリードフレーム
基材、６はＡｇ層、７はＳｎ−Ａｇ層であり、これらは
実施の形態１で説明したものと同様であり、同一の符号
を付して説明を省略する。８は本実施の形態における半
導体装置、９は集積回路であるＩＣチップ、１０は導電
性の高い金属線によって形成されるボンディングワイヤ
ー、１１はＩＣチップ９を封止するためのモールド樹脂
である。In FIG. 3, reference numeral 2 denotes an outer lead portion;
Is an inner lead portion, 4 is a pad, 5 is a lead frame base material, 6 is an Ag layer, and 7 is an Sn-Ag layer. These are the same as those described in Embodiment 1, and are denoted by the same reference numerals. And the description is omitted. Reference numeral 8 denotes a semiconductor device according to the present embodiment, 9 denotes an IC chip as an integrated circuit, 10 denotes a bonding wire formed by a highly conductive metal wire, and 11 denotes a mold resin for sealing the IC chip 9.

【０１００】なお、半導体装置用リードフレームには実
施の形態１と同様のものを使用する。Note that the same lead frame as that of the first embodiment is used for the semiconductor device lead frame.

【０１０１】以上のように構成された本実施の形態の半
導体装置について、以下その製造方法を説明する。The method of manufacturing the semiconductor device having the above-described structure according to the present embodiment will be described below.

【０１０２】まず、実施の形態１と同様の半導体装置用
リードフレーム１のパッド４にダイアタッチ樹脂を塗布
し、ＩＣチップ９をパッド４に載置し接着して、そのま
まオーブンにより２００℃で２時間乾燥し、固定する。
つぎに、ボンディングワイヤー１０により、インナーリ
ード部３とＩＣチップ９の所定の箇所を電気的に接続
し、続いて、モールド樹脂１１によりＩＣチップ９を封
止し、金型により形成、固化して、半導体装置８を形成
する。First, a die attach resin is applied to the pads 4 of the semiconductor device lead frame 1 similar to that of the first embodiment, and the IC chip 9 is mounted on the pads 4 and adhered. Dry and fix for hours.
Next, a predetermined portion of the inner lead portion 3 and the IC chip 9 are electrically connected by the bonding wire 10, and then the IC chip 9 is sealed with the mold resin 11 and formed and solidified by a mold. The semiconductor device 8 is formed.

【０１０３】以上のように本実施の形態によれば、半導
体装置用リードフレーム１のアウターリード部２のＳｎ
−Ａｇ層７の最表面に形成される酸化層７ａを、エッチ
ング処理することにより、錫に対する酸素の比が０．５
から１．８で、かつ、厚さが２０ｎｍ以下となるように
形成し、錫の酸化層７ａに溶融温度の高い安定したＳｎ
Ｏ2が生じることを防ぐことができるので、半田濡れ性
の劣化を防ぐことができ、すなわち、それを用いて製造
された半導体装置８の半田付け性を向上させることがで
きる。As described above, according to the present embodiment, the Sn of the outer lead portion 2 of the lead frame 1 for a semiconductor device is
The oxide layer 7a formed on the outermost surface of the Ag layer 7 is subjected to an etching treatment so that the ratio of oxygen to tin is 0.5
From 1.8 to a thickness of 20 nm or less, and a stable Sn having a high melting temperature is formed on the tin oxide layer 7a.
Since generation of O 2 can be prevented, deterioration of solder wettability can be prevented, that is, solderability of the semiconductor device 8 manufactured using the same can be improved.

【０１０４】また，酸化層７ａは島状構造か島状構造に
近い層状構造となり、表面処理層の錫が表面に露出する
ため、溶融半田からの拡散や共晶温度での溶融が容易に
起こるので、半田濡れ性を向上させ、すなわち、それを
用いて製造された半導体装置８の半田付け性を向上させ
ることができる。The oxide layer 7a has an island structure or a layer structure close to the island structure, and since tin of the surface treatment layer is exposed on the surface, diffusion from the molten solder and melting at the eutectic temperature easily occur. Therefore, the solder wettability can be improved, that is, the solderability of the semiconductor device 8 manufactured using the same can be improved.

【０１０５】また、従来はモールド樹脂１１によりＩＣ
チップ９を封止した後に、アウターリード部２の表面の
酸化層７ａを除去し、半田をメッキして、半田濡れ性を
向上させるための表面処理層を形成していたが、この工
程が必要無く、半導体装置８の製造工程が簡素化され
る。Conventionally, the IC is conventionally formed by the molding resin 11.
After the chip 9 was sealed, the oxide layer 7a on the surface of the outer lead portion 2 was removed, and solder was plated to form a surface treatment layer for improving solder wettability. Therefore, the manufacturing process of the semiconductor device 8 is simplified.

【０１０６】さらに、Ｓｎ−Ａｇ層７において銀の含有
率を１〜８ｗｔ％とすることで、アウターリード部２の
表面において、錫のウイスカが発生することを防止する
ことができ、半導体装置８の錫のウイスカの発生による
短絡事故を防ぐことができる。Further, by setting the silver content in the Sn—Ag layer 7 to 1 to 8 wt%, it is possible to prevent the generation of tin whiskers on the surface of the outer lead portion 2. A short circuit accident due to the generation of tin whiskers can be prevented.

【０１０７】なお、本実施の形態においては、アウター
リード部２の表面にＳｎ−Ａｇ層７が形成され、その表
面が処理された半導体装置用リードフレーム１を用いて
半導体装置８を形成したが、Ｓｎ−Ａｇ層７の形成及び
その表面の処理は、モールド樹脂１１によりＩＣチップ
９を封止した後に行っても良い。すなわち、プレス工程
によりリードフレームの形状に加工し、形成して、付着
した油性分を除去したものに、銅下地メッキを形成し、
インナーリード部３の表面に銀メッキによりＡｇ層６を
形成したリードフレーム基材を用いて半導体装置８を製
造し、その後にＳｎ−Ａｇ層７を形成し、その表面の処
理を行ってもよい。In the present embodiment, the Sn-Ag layer 7 is formed on the surface of the outer lead portion 2, and the semiconductor device 8 is formed using the semiconductor device lead frame 1 whose surface is treated. The formation of the Sn—Ag layer 7 and the surface treatment may be performed after the IC chip 9 is sealed with the mold resin 11. In other words, processed into the shape of the lead frame by the pressing process, formed, and formed to remove the attached oily component, copper base plating,
The semiconductor device 8 may be manufactured using a lead frame base material having the Ag layer 6 formed on the surface of the inner lead portion 3 by silver plating, and then the Sn-Ag layer 7 may be formed and the surface may be treated. .

【０１０８】[0108]

【発明の効果】以上のように、本発明の半導体装置用リ
ードフレームによれば、以下のような有利な効果が得ら
れる。As described above, according to the lead frame for a semiconductor device of the present invention, the following advantageous effects can be obtained.

【０１０９】本発明の請求項１に記載の発明によれば、 （１）錫に対する酸素の比を０．５から１．８とするこ
とで、酸化層に溶融温度の高い安定したＳｎＯ2が生じ
ることを防ぐことができるので、半田濡れ性の劣化を防
ぐことができる半導体装置用リードフレームを提供する
ことができる。According to the first aspect of the present invention, (1) By setting the ratio of oxygen to tin to 0.5 to 1.8, stable SnO 2 having a high melting temperature can be added to the oxide layer. Therefore, it is possible to provide a semiconductor device lead frame that can prevent deterioration of solder wettability.

【０１１０】（２）錫の酸化層の厚さを２０ｎｍ以下と
することで、酸化層は島状構造か島状構造に近い層状構
造となり、表面処理層の錫が表面に露出するため、溶融
半田からの拡散や共晶温度での溶融が容易に起こるの
で、半田濡れ性を向上させることができる半導体装置用
リードフレームを提供することができる。(2) By setting the thickness of the tin oxide layer to 20 nm or less, the oxide layer has an island structure or a layer structure close to the island structure, and tin of the surface treatment layer is exposed on the surface. Since diffusion from the solder and melting at the eutectic temperature easily occur, a lead frame for a semiconductor device capable of improving the solder wettability can be provided.

【０１１１】本発明の請求項２に記載の発明によれば、
請求項１の効果に加え、以下のような有利な効果が得ら
れる。According to the second aspect of the present invention,
In addition to the effects of the first aspect, the following advantageous effects can be obtained.

【０１１２】（１）表面処理層において、錫のウイスカ
が発生することを防止することができる半導体装置用リ
ードフレームを提供することができる。(1) It is possible to provide a semiconductor device lead frame which can prevent the generation of tin whiskers in the surface treatment layer.

【０１１３】（２）銀のエレクトロマイグレーションの
発生を防ぐことができる半導体装置用リードフレームを
提供することができる。(2) It is possible to provide a semiconductor device lead frame capable of preventing the occurrence of silver electromigration.

【０１１４】本発明の請求項３に記載の発明によれば、
請求項１又は２の効果に加え、リードフレーム基材の影
響で半田濡れ性が劣化することを防ぐことができる半導
体装置用リードフレームを提供することができる。According to the third aspect of the present invention,
In addition to the effects of the first and second aspects, it is possible to provide a semiconductor device lead frame that can prevent the solder wettability from being deteriorated by the influence of the lead frame base material.

【０１１５】本発明の請求項４に記載の発明によれば、
請求項１乃至３の内いずれか１項の効果に加え、溶解性
電極を陽極電極に用いた場合に比べ、電極の交換を頻繁
に行う必要がないので、量産性を向上させることができ
る半導体装置用リードフレームを提供することができ
る。According to the invention described in claim 4 of the present invention,
In addition to the effect of any one of claims 1 to 3, a semiconductor that can improve mass productivity because it is not necessary to replace the electrode more frequently than when a soluble electrode is used as an anode electrode. An apparatus lead frame can be provided.

【０１１６】本発明の請求項５に記載の発明によれば、
請求項１乃至４の内いずれか１項の効果に加え、以下の
ような有利な効果が得られる。According to the fifth aspect of the present invention,
The following advantageous effects are obtained in addition to the effects of any one of the first to fourth aspects.

【０１１７】（１）電気メッキにより表面処理層が形成
された後に表面が酸化されて形成される疎で厚い酸化層
を取り除くことができるので、その後に密で均一な酸化
層を形成させることができ、半田濡れ性を向上させるこ
とができる半導体装置用リードフレームを提供すること
ができる。(1) Since a sparse and thick oxide layer formed by oxidizing the surface after the surface treatment layer is formed by electroplating can be removed, a dense and uniform oxide layer can be formed thereafter. Accordingly, it is possible to provide a lead frame for a semiconductor device capable of improving solder wettability.

【０１１８】本発明の請求項６に記載の発明によれば、
以下のような有利な効果が得られる。According to the sixth aspect of the present invention,
The following advantageous effects can be obtained.

【０１１９】（１）電気メッキにより表面処理層が形成
された後に表面が酸化されて形成される疎で厚い酸化層
を取り除くことができるので、その後に密で均一な酸化
層を形成させることができ、半田濡れ性を向上させるこ
とができる半導体装置用リードフレームの製造方法を提
供することができる。(1) The sparse and thick oxide layer formed by oxidizing the surface after the surface treatment layer is formed by electroplating can be removed, so that a dense and uniform oxide layer can be formed thereafter. Accordingly, it is possible to provide a method for manufacturing a lead frame for a semiconductor device, which can improve solder wettability.

【０１２０】本発明の請求項７に記載の発明によれば、
以下のような有利な効果が得られる。According to the seventh aspect of the present invention,
The following advantageous effects can be obtained.

【０１２１】（１）錫に対する酸素の比を０．５から
１．８とすることで、酸化層に溶融温度の高い安定した
ＳｎＯ2が生じることを防ぐことができるので、半田濡
れ性の劣化を防ぐことができ、半田付け性を向上させる
ことができる半導体装置を提供することができる。(1) By setting the ratio of oxygen to tin to 0.5 to 1.8, it is possible to prevent the generation of stable SnO 2 having a high melting temperature in the oxide layer, so that the solder wettability is deteriorated. And a semiconductor device capable of improving solderability can be provided.

【０１２２】（２）錫の酸化層の厚さを２０ｎｍ以下と
することで、酸化層は島状構造か島状構造に近い層状構
造となり、表面処理層の錫が表面に露出するため、溶融
半田からの拡散や共晶温度での溶融が容易に起こるの
で、半田濡れ性を向上させることができ、半田付け性を
向上させることができる半導体装置を提供することがで
きる。(2) By setting the thickness of the tin oxide layer to 20 nm or less, the oxide layer has an island structure or a layer structure close to the island structure, and the tin of the surface treatment layer is exposed on the surface. Since diffusion from the solder and melting at the eutectic temperature easily occur, it is possible to provide a semiconductor device capable of improving solder wettability and improving solderability.

【０１２３】（３）表面処理層において、錫のウイスカ
が発生することを防止することができるので、半導体装
置の錫のウイスカの発生による短絡事故を防ぐことがで
きる半導体装置を提供することができる。(3) Since the generation of tin whiskers in the surface treatment layer can be prevented, a semiconductor device capable of preventing a short circuit accident due to the generation of tin whiskers in a semiconductor device can be provided. .

【０１２４】（４）ＩＣ駆動時の銀のエレクトロマイグ
レーションの発生を防ぐことができるので、モールド樹
脂内において短絡事故を防止することができる半導体装
置を提供することができる。(4) Since the occurrence of silver electromigration at the time of driving the IC can be prevented, a semiconductor device capable of preventing a short circuit accident in the mold resin can be provided.

【０１２５】（５）モールド樹脂の封止工程で金型の隙
間から樹脂が漏出することを防ぐことができ、モールド
樹脂に発生したバリを除去する工程を省略することがで
きる半導体装置を提供することができる。(5) To provide a semiconductor device which can prevent the resin from leaking from the gap of the mold in the molding resin sealing step and can omit the step of removing burrs generated in the molding resin. be able to.

【０１２６】（６）溶解性電極を陽極電極に用いた場合
に比べ、電極の交換を頻繁に行う必要がないので、量産
性を向上させることができる半導体装置を提供すること
ができる。(6) Compared to the case where a dissolvable electrode is used as the anode electrode, it is not necessary to change the electrode frequently, so that a semiconductor device which can improve mass productivity can be provided.

【０１２７】（７）電気メッキにより表面処理層が形成
された後に表面が酸化されて形成される疎で厚い酸化層
を取り除くことができるので、その後に密で均一な酸化
層を形成させることができ、半田濡れ性を向上させるこ
とができ、半田付け性を向上させることができる半導体
装置を提供することができる。(7) Since the surface is oxidized after the surface treatment layer is formed by electroplating and the sparse and thick oxide layer formed can be removed, a dense and uniform oxide layer can be formed thereafter. Accordingly, it is possible to provide a semiconductor device capable of improving solder wettability and improving solderability.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態１における半導体装置リー
ドフレームの平面図FIG. 1 is a plan view of a semiconductor device lead frame according to a first embodiment of the present invention.

【図２】本発明の実施の形態１における半導体装置リー
ドフレームの模式断面図FIG. 2 is a schematic cross-sectional view of a semiconductor device lead frame according to the first embodiment of the present invention.

【図３】本発明の実施の形態２における半導体装置の模
式断面図FIG. 3 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention;

【図４】本発明の実施の形態１における酸化層の組成と
その深さとの関係を示した関係図FIG. 4 is a relationship diagram showing a relationship between a composition of an oxide layer and a depth thereof according to the first embodiment of the present invention.

【図５】比較例１における酸化層の組成とその深さとの
関係を示した関係図FIG. 5 is a relationship diagram showing the relationship between the composition of an oxide layer and its depth in Comparative Example 1.

【符号の説明】[Explanation of symbols]

１ 半導体装置用リードフレーム ２ アウターリード部 ３ インナーリード部 ４ パッド ５ リードフレーム基材 ６ Ａｇ層 ７ Ｓｎ−Ａｇ層 ７ａ 酸化層 ８ 半導体装置 ９ ＩＣチップ １０ ボンディングワイヤー １１ モールド樹脂 DESCRIPTION OF SYMBOLS 1 Lead frame for semiconductor devices 2 Outer lead part 3 Inner lead part 4 Pad 5 Lead frame base material 6 Ag layer 7 Sn-Ag layer 7a Oxide layer 8 Semiconductor device 9 IC chip 10 Bonding wire 11 Mold resin

───────────────────────────────────────────────────── フロントページの続き (72)発明者 舛田 松夫 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 常盤 剛 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F067 AA09 DC12 DC13 DC16 DC17 EA01 EA02 EA04  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Matsuo Masuda 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. Term (reference) 5F067 AA09 DC12 DC13 DC16 DC17 EA01 EA02 EA04

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】銀又は銀を含む合金の表面処理層Ａを設け
たインナーリード部と、銀又は銅と体心正方構造の錫と
を含む合金の表面処理層Ｂを設けたアウターリード部
と、を有し、ニッケル、銅、鉄、又はニッケル、銅、鉄
のうち１以上を含む合金で形成された板状素材を基材と
した半導体装置用リードフレームであって、前記表面処
理層Ｂの最表面に、錫に対する酸素の比が０．５から
１．８で、かつ、厚さが１〜２０ｎｍの錫の酸化層が形
成されていることを特徴とする半導体装置用リードフレ
ーム。1. An inner lead portion provided with a surface treatment layer A of silver or an alloy containing silver, and an outer lead portion provided with a surface treatment layer B of an alloy containing silver or copper and tin having a body-centered square structure. A lead frame for a semiconductor device, comprising a base material made of a plate-shaped material formed of nickel, copper, iron, or an alloy containing at least one of nickel, copper, and iron, wherein the surface treatment layer B A lead frame for a semiconductor device, wherein a tin oxide layer having an oxygen to tin ratio of 0.5 to 1.8 and a thickness of 1 to 20 nm is formed on the outermost surface of the lead frame. 【請求項２】前記アウターリード部の表面に設けられた
前記表面処理層Ｂの銀含有率が１〜８ｗｔ％、又は、銅
含有率が０．１〜２ｗｔ％とすることを特徴とする請求
項１に記載の半導体装置用リードフレーム。2. The surface treatment layer B provided on the surface of the outer lead portion has a silver content of 1 to 8 wt% or a copper content of 0.1 to 2 wt%. Item 2. A lead frame for a semiconductor device according to item 1. 【請求項３】前記アウターリード部の表面に設けられた
前記表面処理層Ｂの厚さが３〜１５μｍに形成されてい
ることを特徴とする請求項１又は２に記載の半導体装置
用リードフレーム。3. The lead frame for a semiconductor device according to claim 1, wherein the thickness of the surface treatment layer B provided on the surface of the outer lead portion is 3 to 15 μm. . 【請求項４】前記アウターリード部の表面に設けられた
前記表面処理層Ｂが、白金、イリジウム、タンタル、ロ
ジウム、ルテニウム、又はこれらの酸化物のうち１以上
を含む不溶解性電極を陽極電極に用いた電気メッキによ
り形成されたものであることを特徴とする請求項１乃至
３の内いずれか１項に記載の半導体装置用リードフレー
ム。4. The method according to claim 1, wherein the surface treatment layer B provided on the surface of the outer lead portion comprises an insoluble electrode containing platinum, iridium, tantalum, rhodium, ruthenium, or at least one of these oxides. 4. The lead frame for a semiconductor device according to claim 1, wherein the lead frame is formed by electroplating. 5. 【請求項５】前記アウターリード部の表面に設けられた
前記表面処理層Ｂの最表面に形成された前記酸化層は、
水酸化ナトリウム又は三燐酸ナトリウムを含む処理剤に
よって膨潤され、電気化学的な方法によりエッチング処
理されて形成されたことを特徴とする請求項１乃至４の
内いずれか１項に記載の半導体装置用リードフレーム。5. The oxide layer formed on the outermost surface of the surface treatment layer B provided on the surface of the outer lead portion,
The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is formed by being swollen by a treatment agent containing sodium hydroxide or sodium triphosphate and being etched by an electrochemical method. Lead frame. 【請求項６】前記アウターリード部の表面に設けられた
前記表面処理層Ｂの最表面に、錫に対する酸素の比が
０．５から１．８で、かつ、厚さが２０ｎｍ以下の錫の
酸化層を形成するために、前記酸化層を水酸化ナトリウ
ム又は三燐酸ナトリウムを含む処理剤によって膨潤する
工程と、電気化学的な方法によりエッチング処理する工
程を備えたことを特徴とする半導体装置用リードフレー
ムの製造方法。6. The outermost surface of the surface treatment layer B provided on the surface of the outer lead portion, wherein tin having a ratio of oxygen to tin of 0.5 to 1.8 and a thickness of 20 nm or less is provided. A step of swelling the oxide layer with a treating agent containing sodium hydroxide or sodium triphosphate to form an oxide layer, and a step of etching by an electrochemical method. Lead frame manufacturing method. 【請求項７】請求項１乃至５に記載の半導体装置用リー
ドフレームを用いて形成されることを特徴とする半導体
装置。7. A semiconductor device formed using the semiconductor device lead frame according to claim 1.
JP2000286725A 2000-09-21 2000-09-21 Lead frame for semiconductor device, method of manufacturing the same, and semiconductor device using the same Expired - Fee Related JP3417395B2 (en)

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