JP2002100676A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in micronization. SOLUTION: There are provided a trench 3 formed in an element separation region which is so formed as to enclose an element formation region on a semiconductor substrate 1, and insulating films 4 and 5 which, formed with the same width as a trench width on the trench 3, form a void 50 in the trench 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention is excellent in miniaturization,
The present invention relates to a semiconductor device without deteriorating element isolation characteristics and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated,
The spacing between transistors is becoming increasingly smaller. Conventionally, the LOCOS method, which has been adopted as an element isolation method, has a limit in miniaturization of an isolation width, and a shallow trench isolation method has been used to solve the problem. Although this shallow trench isolation is suitable for miniaturization, an unnecessary leak current is generated because stress of an embedded oxide film causes crystal defects.

Therefore, in order to relieve this stress,
By forming the side wall of the groove to have a tapered shape, a slight leakage current can be suppressed a little, but this hinders miniaturization and becomes more and more problematic in the 100 nm era. Hereinafter, the conventional shallow trench isolation method will be described.

First, as shown in FIG. 18A, a silicon nitride film 102 (for example, having a thickness of 100 to 200 nm) serving as a mask film is laminated on a semiconductor substrate 101 by a CVD method, and photolithography and etching techniques are used. Patterning. Next, using the silicon nitride film 102 as a mask, the semiconductor substrate 101 is etched to form the trench 10.
3 (groove depth, for example, 200 to 500 nm).

The trench 103 separates elements from each other and has a width of, for example, 150 to 500 nm. At this time, a silicon oxide film may be formed below the silicon nitride film 102 and used as a mask film.
In this step, the etching conditions are optimized and the trench 103 is formed so as to have a tapered side wall.

Next, as shown in FIG. 18B, a silicon oxide film 104 is formed on the inner wall of the trench 103 by a thermal oxidation method.
(For example, a thickness of 10 to 20 nm). next,
A silicon oxide film 105 is stacked by the CVD method, and the trench 103 is buried. At this time, the thickness of the silicon oxide film 105 formed needs to be at least half the width of the trench 103 to be buried.

Next, as shown in FIG. 18C, the silicon oxide film 105 is etched and flattened by a polishing method or an etch-back method, and the silicon oxide film 105 is left only inside the trench 103. Next, as shown in FIG. 19A, the silicon oxide film 105 is etched by a wet etching method using hydrofluoric acid until the surface thereof is substantially the same as the semiconductor substrate 101. Next, the silicon nitride film 102 is removed by etching with hot phosphoric acid or the like. With the above steps, the step of forming the element isolation region is completed.

Next, a transistor is formed. First, as shown in FIG.
Gate insulating film 106 (for example, 2 to 50 n) made of a silicon oxide film, a silicon nitride film or a metal oxide film
m thickness). Next, a polysilicon, metal, or metal nitride film (having a thickness of, for example, 150 to 300 nm) is stacked, and the gate electrode 107 is formed in a desired pattern by lithography and etching.

Next, for example, arsenic or phosphorus is used for the NMISFET and boron is used for the PMISFET by using the gate electrode 7 as a mask.
Doping of about 4E14 / cm ² , and heat treatment (for example, 80
(0 to 950 ° C., 1 to 30 minutes) to form the activated first impurity diffusion layer 108.

Next, as shown in FIG. 19C, a silicon oxide film, a silicon nitride film, or a multilayer film thereof is laminated by a CVD method, and a side wall 109 is formed by anisotropic etching. Next, the side wall 109
Then, impurities are implanted by an ion implantation method using the gate electrode 107 as a mask. For example, in the case of an NMISFET, arsenic or phosphorus is doped in the case of a PMISFET, and in the case of a PMISFET, boron is doped at about 1E15 to 1E16 / cm ² , and activated by heat treatment (800 to 950 ° C., 1 to 30 minutes) to form a second impurity diffusion layer. Form 110.

The thus formed gate electrode 107
Extend to form wiring. In this case, the structure is such that the device is connected to an adjacent transistor or connected to a power supply across the upper part of the trench separating the elements.

In the conventional semiconductor device formed as described above, since the silicon oxide film is buried in the trench, the silicon oxide film and silicon have different coefficients of thermal expansion inside the trench. Crystal defects may occur in the semiconductor substrate due to stress in a heat treatment step (for example, a heat step after impurity implantation) or stress inherent in the silicon oxide film itself when the silicon oxide film is formed.

Such crystal defects cause unnecessary leak current, hinder device operation, and greatly reduce the yield of non-defective products. In order to prevent this, a configuration is adopted in which the trench shape is tapered to reduce stress.

Another conventional semiconductor device is proposed in, for example, Japanese Patent Application Laid-Open No. Hei 8-37230. FIG.
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 8-37230. FIG. 20 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. In the figure,
The same parts as those in the conventional case are denoted by the same reference numerals, and description thereof will be omitted.

In this conventional method of manufacturing a semiconductor device, first, a gate insulating film 106 and a gate electrode 107 are formed on a semiconductor substrate 101, and a first impurity diffusion layer 108 is formed. Next, a sidewall 109 is formed, and a second impurity diffusion layer 110 is formed. Next, a patterned resist film 200 is formed, and the semiconductor substrate 101 is etched to form a trench 103 (FIG. 20).
(A)).

Next, an insulating film 212 made of an organic solvent of silanol or polyimide resin is formed on the upper surface of the trench 103.
To form a sealed space 211 in the trench 103 (FIG. 20B). Next, on the insulating film 212, an interlayer insulating film 213 is formed as a protective film for the insulating film 212. Next, a patterned resist film 201 is formed (FIG. 20C), and the insulating film 212 and the interlayer insulating film 2 are formed.
13 is patterned to form an element isolation region and a transistor as shown in FIG.

In this conventional semiconductor device, a sealed space 211 is formed inside the trench 103 to prevent crystal defects and the like, and to prevent unnecessary leak current and hinder device operation.

[0018]

In the conventional semiconductor device configured as described above, the trench is tapered, and a sealed space 211 is formed inside the trench 103 to prevent crystal defects and the like. Although it prevents unwanted leakage current from hindering device operation, the former requires a tapered shape,
Further, in the latter, there is a problem that the patterning technique of the gate above the trench 103 is difficult, which hinders miniaturization, that is, hinders high integration.

Also, there is a large difference in height between the location where the gate electrode is formed and the location where the trench 103 (element isolation region) is formed, making it difficult to accurately perform wiring patterning in a later step. There was a problem of becoming.

The present invention has been made to solve the above-described problems, and provides a semiconductor device excellent in miniaturization and excellent in flatness, and a method of manufacturing the semiconductor device.

[0021]

Means for Solving the Problems Claim 1 according to the present invention.
A trench formed in an element isolation region formed so as to surround an element formation region on a semiconductor substrate;
An insulating film is formed on the trench with substantially the same width as the trench width and forms an air gap in the trench.

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, further comprising a trench formed with a desired width on at least one side near the element forming region, which is an element isolation region. Things.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, when trenches are formed on both sides near the element formation region in the element isolation region, A protective film is provided on the semiconductor substrate in the element isolation region sandwiched between the respective insulating films formed in the above.

According to a fourth aspect of the present invention, there is provided a semiconductor device according to any one of the first to third aspects, wherein the upper surface of the gate electrode formed on the element formation region and the upper surface of the insulating film are substantially identical. They are formed at the same height.

According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the bottom of the insulating film is formed in an overhang shape.

According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the insulating film is formed to extend on the inner wall of the trench.

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the insulating film is formed to extend over the entire inner wall of the trench.

According to a eighth aspect of the present invention, in the method of manufacturing a semiconductor device, a mask film patterned in a desired pattern is formed on the semiconductor substrate, and the semiconductor substrate is formed at a predetermined depth using the mask film as a mask. Etching is performed to form a trench, an insulating film that covers the mask film and covers the upper portion of the trench and forms a void in the trench is stacked, the insulating film stacked on the mask film is removed, and only in the pattern of the mask film. An insulating film is left on the substrate.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the mask film is removed, a gate insulating film is formed on the semiconductor substrate, and the conductive film is formed so as to cover the insulating film. Are stacked, the conductive film stacked on the insulating film is removed, the conductive film is left only in a region sandwiched between the insulating films, and the conductive film is patterned to form a gate electrode.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device, the trench is formed in the element isolation region surrounding the element formation region on the semiconductor substrate,
In the case where the mask film is formed with a desired width on both sides in the vicinity of the element formation region, which is an element isolation region, the step of removing the mask film according to claim 9 is performed by removing only the mask film on the element formation region. Then, a mask film on the element isolation region is left to form a protective film sandwiched between insulating films.

According to the present invention, there is provided a method of manufacturing a semiconductor device according to any one of claims 8 to 10, wherein the step of forming the insulating film comprises the steps of: Is formed, and then a second insulating film is laminated so as to cover the mask film and close the trench inside the upper end of the trench, and form the insulating film using the first and second insulating films. Things.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the eighth to tenth aspects, the step of forming the insulating film comprises the steps of: Laminating a thin first insulating film on the exposed surface of the film, and then laminating a second insulating film covering the mask film and closing the trench in the pattern of the mask film above the trench, An insulating film is formed by the first and second insulating films.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the eighth to tenth aspects, the mask film is formed of a silicon film.
The step of forming the insulating film is performed by forming a first insulating film on the inner wall of the trench and on the exposed surface of the mask film by a thermal oxidation method, and then covering the mask film and in a pattern of the mask film above the trench. A second insulating film is stacked so as to cover the trench, and the first and second insulating films form an insulating film.

According to a fourteenth aspect of the present invention, in the method of the thirteenth aspect, a protective insulating film is formed between the mask film and the semiconductor substrate. Is used, and the protective insulating film remaining after removing the mask film is used as a gate insulating film.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described. 1 to 5 are cross-sectional views showing the steps of manufacturing the semiconductor device according to the first embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to these drawings. First, FIG.
As shown in FIG. 1, a mask film 2 is laminated on a semiconductor substrate 1 with a thickness of 250 to 400 nm using, for example, a silicon nitride film. Thereafter, the mask film 2 is patterned by photolithography and an etching method while leaving a desired region.

Next, as shown in FIG. 1B, the mask film 2
Using the mask as a mask, the semiconductor substrate 1 is etched to form a trench 3 (groove depth, for example, 200 to 600 nm depth). Next, as shown in FIG. 1C, a first insulating film 4 made of a silicon oxide film is formed by a thermal oxidation method on a wall where the semiconductor substrate 1 is exposed by the trench 3 (hereinafter, this portion will be referred to as a trench). (Referred to as an inner wall). Next, CV
By a method D, for example, a silicon oxide film is laminated as the second insulating film 5 so as to cover the mask film 2 and close the upper part of the trench 3.

At this time, the second insulating film 5 is formed under the condition that the bottom has an overhang shape. As the method, for example, as the temperature of the CVD reaction becomes higher, the surface reaction is controlled from the diffusion control to the diffusion control, and the overhang shape is formed under the diffusion control condition. Further, instead of using a high temperature, it is also possible to form the same by a plasma CVD method.

Further, the bottom surface of the second insulating film 5 is formed to be lower than the surface of the semiconductor substrate 1 (inside the trench 3). Thereby, an insulating film is formed by the first insulating film 4 and the second insulating film 5 formed on the side walls of the trench 3,
This insulating film is formed continuously. When formed in this way, as shown in FIG. 1C, a void 50 surrounded by the insulating films (the first insulating film 4 and the second insulating film 5) is formed in the trench 3.

Next, as shown in FIG. 2A, the second insulating film 5 on the mask film 2 is removed by, for example, a polishing method or an etch-back method, and the second insulating film 5 is formed only in the pattern of the mask film 2. The insulating film 5 is left. Next, as shown in FIG. 2B, the mask film 2 is removed by, for example, wet etching using hot phosphoric acid or dry etching. Through the above steps, the formation of the element isolation region is completed. The insulating film on the trench thus formed is patterned with the same mask film as the pattern mask film of the trench, and the trench width is formed to be substantially the same on the trench.

Next, as shown in FIG. 3A, for example, a silicon oxide film, a silicon nitride film, a BST film, Hf, Z
An oxide film of r, Al, Ti or the like is laminated in a thickness of 2 to 50 nm. Next, a conductive film 7 such as a polysilicon film or a titanium nitride film is formed to a thickness of 250 to 400 nm by a CVD method.

Next, as shown in FIG. 3B, the conductive film 7 is etched by, for example, a chemical mechanical polishing method or an etching method until the surface of the second insulating film 5 is exposed. The upper surface and the upper surface of the conductive film 7 are formed at substantially the same height. Next, as shown in FIG. 4A, the conductive film 7 is patterned by photolithography and etching to form a gate electrode 8. Therefore, the upper surfaces of the second insulating film 5 and the gate electrode 8 are formed at substantially the same height.

Next, for example, NMI
In the case of an SFET, arsenic or phosphorus, and PMIS
In the case of FET, boron is 1E13-4E14 / cm ^2.
Doping and heat treatment (800-950 ° C, 1-30
) To form the first impurity diffusion layer 9. Next, as shown in FIG. 4B, an insulating film, for example, a silicon oxide film, a silicon nitride film, or a laminated structure film thereof is laminated to a thickness of, for example, 20 to 100 nm by a CVD method, and is anisotropically etched. The sidewall 10 is formed.

Next, impurities such as arsenic or phosphorus in the case of a MISFET and PM
In the case of ISFET, boron is 1E15 to 1E16 / c
m ² about dope, heat treatment (at 800 to 950 ° C.,. 1 to
30 minutes), the second impurity diffusion layer 11 serving as a source / drain region of the transistor.
To form Through the above steps, a transistor is formed.

Next, as shown in FIG. 5A, an interlayer insulating film 25, for example, a silicon oxide film is laminated to a thickness of 500 to 1000 nm by a CVD method or the like. Next, the surface is flattened by etch back or polishing. Next, FIG.
As shown in (b), an electrode wiring 26 to the gate electrode 8 and the source / drain region (second impurity diffusion region) is formed (only the wiring to the gate electrode 8 is shown in the figure).
For example, a metal film of aluminum alloy, copper, tungsten, or the like, a metal silicide, a metal nitride film, or a stacked film thereof is formed with a thickness of 100 to 500 nm.

In the semiconductor device according to the first embodiment configured as described above, since a void is provided inside the trench in the element isolation region, the generation of crystal defects due to thermal stress can be prevented. Needless to say, since the gap can be formed by an insulating film having substantially the same width as the trench width, the element isolation region can be formed with substantially the same width as the trench width, and a configuration suitable for miniaturization is provided. Have.

The first insulating film is formed of a thermal oxide film, has a good film quality, and can obtain good separation characteristics without forming unnecessary interface states. Further, since the upper surface of the insulating film over the trench and the upper surface of the gate electrode are formed at substantially the same height, a semiconductor device with excellent planarization can be formed.

In the first embodiment, the example in which the first insulating film 4 is formed on the inner wall of the trench 3 has been described. However, the present invention is not limited to this, and the first insulating film 4 may be formed on the inner wall of the trench 3. Even if the trench is not formed, if the bottom of the second insulating film 5 is surely located below the upper end of the trench 3, a void 50 will be formed in the trench 3, and the function as an element isolation region will be obtained. Can be fulfilled.

Embodiment 2 In the first embodiment, the second
When the insulating film 5 is formed, it is necessary to set a film forming condition such that the insulating film 5 has an overhang shape and the bottom thereof enters the inside of the trench 3. Here, a case where the condition that the bottom portion enters the inside of the trench 3 is not required will be described.

First, a trench 3 is formed as shown in FIG. 1B through the same steps as in the method of manufacturing a semiconductor device according to the first embodiment. Next, as shown in FIG.
The insulating film 12 is formed by stacking a silicon oxide film or a silicon nitride film with a thickness of 10 to 50 nm by, for example, a CVD method.
Before forming the first insulating film 12, a silicon oxide film having a thickness of 5 to 20 nm may be formed on the inner wall of the trench 3 by thermal oxidation.

Next, as shown in FIG. 6B, a second insulating film 13 having an overhang shape is formed, for example, by stacking a silicon oxide film or a silicon nitride film so as to cover the mask film 2. , First insulating film 12 and second insulating film 1
At 3, an insulating film that covers the upper part of the trench 3 is formed. In this case, the bottom of the second insulating film 13 does not need to be positioned lower than the upper end of the trench 3, but may be formed in a shape that enters the pattern of the mask film 2.

This is because the first insulating film 12 is formed on the side wall of the mask film 2 continuously from the inner wall of the trench 3. When formed in this manner, as shown in FIG. 6B, a gap 51 surrounded by the insulating films (the first insulating film 14 and the second insulating film 13) is formed in the trench 3.
Is formed.

Next, as shown in FIG. 7A, the first insulating film 12 and the second insulating film 13 on the mask film 2 are removed by etching, for example, by a polishing method or an etch-back method. Only in the pattern of the film 2, that is, in the trench 3
The first insulating film 12 and the second insulating film 13 are left only on the upper and inner regions.

Next, as shown in FIG. 7B, the mask film 2 is removed by, for example, a wet or dry etching method.
Through the above steps, the formation of the element isolation region is completed. The insulating film on the trench thus formed is patterned with the same mask film as the pattern mask film of the trench, and the trench width is formed to be substantially the same on the trench. Hereinafter, through the same steps as in the first embodiment,
As shown in FIG. 8, a transistor can be formed. Further, although not shown, it goes without saying that the upper wiring and the like can be formed in the same manner through the same steps as in the first embodiment.

The semiconductor device of the second embodiment configured as described above has the same effect as that of the first embodiment, and the first insulating film is formed on the inner wall of the trench and the pattern of the mask film. Since the second insulating film is formed after being stacked thereon, the condition for forming the second insulating film is relaxed to the condition that the bottom of the second insulating film only needs to be within the pattern of the mask film. And the formation of voids can be easily performed.

In the second embodiment, an example has been described in which the first insulating film 12 is formed on the inner wall of the trench 3 and the entire exposed portion of the mask film 2. However, the present invention is not limited to this. When the first insulating film 12 is formed by the method described above, even if the first insulating film 12 is not formed in a part such as the bottom of the trench 3, the trench 3 is formed from the bottom of the second insulating film 13.
It is sufficient that the first insulating film 12 is formed surely at a position up to the upper end of the gap 5.
1 is reliably formed, and can function as an element isolation region.

Embodiment 3 In each of the above embodiments, an example in which an insulating film is used as the mask film 2 has been described. However, the present invention is not limited to this, and a silicon film may be used. Hereinafter, a method of manufacturing the semiconductor device according to the third embodiment using the silicon film will be described with reference to FIGS.

First, as shown in FIG. 9A, a mask film 14 is formed on the semiconductor substrate 1 by a silicon film made of, for example, polysilicon or an amorphous silicon film for 250 to 400 nm.
and a thickness of m. After that, the mask film 14 is patterned by photolithography and an etching method while leaving a desired region. Thereafter, the trench 3 (groove depth, for example, 200 to 600) is formed on the semiconductor substrate 1 using the mask film 14 as a mask.
to a depth of nm).

Next, as shown in FIG. 9B, a first insulating film 15 made of a silicon oxide film is formed on the exposed surface of the mask film 14 and the inner wall of the trench 3 by, for example, a thermal oxidation method. It is formed with a thickness of 30 nm. At this time, since the thermal oxidation method is used, an oxide film can be formed on the inner wall of the trench 3 and the exposed surface of the mask film 14 easily and with good coverage as compared with the CVD method.

Next, as shown in FIG. 10A, a second insulating film 13 having an overhang shape, for example, a silicon oxide film or a silicon nitride film is laminated and formed so as to cover the mask film 14. The first insulating film 15 and the second insulating film 13 form an insulating film that covers an upper portion of the trench 3.
In this case, the bottom of the second insulating film 13 is
It is not necessary to be positioned lower than the upper end of the mask film 14, and it is sufficient that the mask film 14 be formed in a shape that enters the inside of the pattern.

This is because even the side wall of the mask film 14
This is because the first insulating film 15 is formed continuously from the inner wall of the trench 3. When formed in this way, as shown in FIG. 10A, a void 52 surrounded by the insulating films (the first insulating film 15 and the second insulating film 13) is formed in the trench 3.

Next, as shown in FIG. 10B, the first insulating film 15 and the second insulating film 13 on the mask film 14 are removed by etching, for example, by a polishing method or an etch-back method. The first insulating film 15 and the second insulating film 13 are left only in the pattern of the film 2, that is, only in the region on and above the inner wall of the trench 3.

Next, as shown in FIG. 10C, the mask film 14 is removed by, for example, a wet or dry etching method. Through the above steps, the formation of the element isolation region is completed. The insulating film on the trench thus formed is patterned with the same mask film as the pattern mask film of the trench, and the trench width is formed to be substantially the same on the trench. Hereinafter, a transistor can be formed as shown in FIG. 11 through steps similar to those of the above embodiments. Further, although not shown, it is needless to say that the upper wiring and the like can be formed in the same manner through the same steps as in the above embodiments.

The semiconductor device according to the third embodiment configured as described above has the same effects as those of the above-described embodiments, and the mask film is formed of a silicon film.
Since the first insulating film can be formed of a thermal oxide film on the inner wall of the trench and on the exposed surface of the mask film, the first insulating film can be surely formed in the pattern of the mask film as compared with the case where it is formed by the CVD method. Thus, a void can be reliably formed in the trench.

Embodiment 4 When a silicon film is used as a mask film as in the third embodiment, the upper surface of a semiconductor substrate made of single crystal silicon may be roughened when the mask film is removed. A fourth embodiment for solving this will be described with reference to FIGS.

First, as shown in FIG. 12A, a protective insulating film 140 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1 between the mask film 14 and the semiconductor substrate 1 by 10 nm.
And a mask film 14 made of, for example, polysilicon or an amorphous silicon film is
It is formed by laminating with a thickness of 400 nm. After that, the mask film 14 and the protective insulating film 140 are patterned by photolithography and an etching method while leaving a desired region.
Next, as shown in FIG. 12B, the semiconductor substrate 1 is etched using the mask film 14 as a mask to form a trench 3 (groove depth, for example, 200 to 600 nm depth).

Next, as shown in FIG. 12C, the first insulating film 15 is formed to a thickness of, for example, 10 to 30 nm on the exposed surface of the mask film 14 and the inner wall of the trench 3 by, for example, a thermal oxidation method. Formed. At this time, since the thermal oxidation method is used, CV
An oxide film can be formed on the inner wall of the trench 3 and on the exposed surface where the mask film 14 is exposed, with better coverage than in the method D.

Next, as shown in FIG. 13A, a second insulating film 13 having an overhanging shape, for example, a silicon oxide film or a silicon nitride film is laminated and formed so as to cover the mask film 14. First insulating film 15, protective insulating film 14
An insulating film that covers the upper part of the trench 3 is formed by the 0 and the second insulating film 13. At this time, the second insulating film 1
The bottom of the trench 3 does not need to be positioned lower than the top of the trench 3, but may be formed in such a shape as to enter into the pattern of the mask film 14.

This is because even the side wall of the mask film 14
This is because the first insulating film 15 and the protective insulating film 140 are formed continuously from the inner wall of the trench 3. When formed in this manner, as shown in FIG. 13A, an insulating film (the first insulating film 15, the protective insulating film 140) is formed in the trench 3.
And a void 53 surrounded by the second insulating film 13).

Next, as shown in FIG. 13B, the first insulating film 15 and the second insulating film 13 on the mask film 14 are removed by etching, for example, by a polishing method or an etch-back method. The first insulating film 15 and the second insulating film 13 are left only in the pattern of the film 2, that is, only in the region on and above the inner wall of the trench 3.

Next, as shown in FIG. 13C, the mask film 14 is removed by, for example, a wet or dry etching method, and the protective insulating film 140 remains. Through the above steps, the formation of the element isolation region is completed. The insulating film on the trench thus formed is patterned with the same mask film as the pattern mask film of the trench, and the trench width is formed to be substantially the same on the trench. Less than,
By using the remaining protective insulating film 140 as the gate insulating film 6 and performing the other steps in the same manner as in the above embodiments, a transistor can be formed as shown in FIG. Further, although not shown, it is needless to say that the upper wiring and the like can be formed in the same manner through the same steps as in the above embodiments.

According to the semiconductor device of the fourth embodiment configured as described above, the same effects as those of the above-described embodiments can be obtained, and the protective insulation between the mask film 14 and the semiconductor substrate 1 can be obtained. Since the film 140 has been formed, the mask film 14
During the removal, the semiconductor substrate 1 is covered with the protective insulating film 140, so that the etching of the semiconductor substrate 1 made of single crystal silicon due to a decrease in the etching selectivity can be prevented. Further, the remaining protective insulating film 140 can be used as the gate insulating film 6.

In the fourth embodiment, an example in which the protective insulating film 140 is formed of a silicon oxide film has been described. However, the present invention is not limited to this and can be used as a gate insulating film in a later step. If it is a membrane, for example,
If a silicon nitride film, a silicon oxynitride film, or the like is formed of a single-layer film or a multilayer film thereof, it can be formed in the same manner as in the fourth embodiment, and it goes without saying that the same effect is obtained.

Embodiment 5 In each of the above embodiments, when the upper surface of the insulating film is planarized, a polishing method or an etch-back method is used. Of these, when polishing is performed, if the width of the trench 3 serving as an element isolation region is large, dishing occurs in which the central portion of the trench 3 is dented. In the case of etch back, if the width of the trench 3 serving as an element isolation region is large, the upper surface of the insulating film is formed to reflect the shape of the trench 3, and in the etch back, etching is performed while reflecting the shape. Therefore, it is difficult to cover the upper surface of the trench 3 with good flatness.

In any method, if the width of the trench 3 is large, it becomes difficult to secure the flatness on the upper surface of the insulating film. Hereinafter, a fifth embodiment for solving this will be described.
The method of manufacturing the semiconductor device will be described with reference to FIGS.

First, as shown in FIG. 15A, for example, a silicon nitride film is laminated as a mask film 20 on the semiconductor substrate 1. Next, the mask film 20 is patterned by lithography and etching while leaving a pattern in a desired region. In the figure, A is an element isolation region, B is a transistor (element) formation region, and the transistor formation region B is interposed between the element isolation regions A.

Here, it is assumed that the width of the element isolation region A is large (for example, several μm or more), and a predetermined amount of width is provided on both sides of the element isolation region A and in the vicinity of the transistor formation region B. For example, a trench pattern having a width of 20 to 100 nm or less is formed. If the trench pattern is formed only in the vicinity, the function as the element isolation region can be sufficiently achieved. However, needless to say, it can be similarly formed at other places other than the boundary part.

In the fifth embodiment, a trench in an element isolation region having the same structure as that of each of the above embodiments and a structure on the trench are appropriately applied to a portion near the element formation region. is there. In the fifth embodiment, a case will be described in which the first embodiment is applied. However, it is needless to say that the same can be applied to other embodiments.

Next, as shown in FIG. 15B, a trench 18 is formed in the semiconductor substrate 1 using the mask film 20 as a mask. Next, as shown in FIG. 15C, the first insulating film 4 made of a silicon oxide film by thermal oxidation
It is formed on the inner wall of the trench 18 with a thickness of 10 nm. Next, the mask film 20 is covered with, for example, a silicon oxide film as the second insulating film 19 by the CVD method and the trench 1 is formed.
8 so as to cover the upper part.

At this time, the method of forming the second insulating film 19 is as follows.
This is performed under the condition that the bottom has an overhang shape. As the method, for example, as the temperature of the CVD reaction becomes higher, the transition from the surface reaction rate-limiting to the diffusion rate-limiting is performed. In addition, instead of using a high temperature, it can be formed in the same manner by forming by a plasma CVD method.

Further, the bottom surface of the second insulating film 19 is formed to be lower than the surface of the semiconductor substrate 1 (inside the trench 18). Thus, an insulating film is formed by the first insulating film 4 and the second insulating film 19 formed on the side walls of the trench 18, and the insulating film is formed continuously.
When formed in this manner, the trench 18 has the structure shown in FIG.
As shown in (c), a void 54 surrounded by the insulating films (the first insulating film 4 and the second insulating film 19) is formed.

Next, the second insulating film 19 on the mask film 20 is removed by, for example, a polishing method or an etch-back method. Next, as shown in FIG. 16A, a resist film 21 is formed on the element isolation region A by lithography. Next, as shown in FIG. 16B, the second insulating film 19 and the mask film 20 are etched using the resist film 21 as a mask, and the second insulating film 19 and the mask film 20a are left only on the element isolation region. Let it. At this time, the mask film 20 remaining on the semiconductor substrate 1 in the element isolation region A sandwiched between the second insulating films 19 is used as a protective film 20a. The protective film 20a covers the element isolation region A interposed between the second insulating films 19 and prevents entry into an element isolation region such as a conductive film formed in a later step.

Thereafter, a transistor can be formed as shown in FIG. 17 through the same steps as in the above embodiments. Further, although not shown, it is needless to say that the upper wiring and the like can be formed in the same manner through the same steps as in the above embodiments.

The semiconductor device according to the fifth embodiment is configured as described above. When the element isolation region is wide, a trench having a desired width is provided in the element isolation region near the transistor forming region, so that the semiconductor device is flat. An element isolation region can be formed efficiently. Also, since a protective film is formed,
The formation in the subsequent wiring process becomes easy.

In the fifth embodiment, an example is shown in which trenches are provided on both sides of the element isolation region in the vicinity of the element formation region. However, the present invention is not limited to this, and the trench is provided only in one of the vicinity. Even if is formed, if a trench having a desired width is formed, it can function as an element isolation region.

[0085]

As described above, according to the first aspect of the present invention, a trench formed in an element isolation region formed so as to surround an element formation region on a semiconductor substrate, and a trench width is formed on the trench. Since the semiconductor device is formed with substantially the same width and has an insulating film that forms a gap in the trench, the gap formed in the trench can be minimized in the margin of the element isolation region. Can be provided.

According to a second aspect of the present invention, in the first aspect, a trench having a desired width is provided on at least one side of the element isolation region near the element formation region. It is possible to provide a semiconductor device in which a desired insulating film can be obtained even when the element isolation region is more than a desired width.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, when trenches are formed on both sides near the element formation region in the element isolation region, the trench is formed on each trench. Since the protective film is provided on the semiconductor substrate in the element isolation region sandwiched between the formed insulating films, it is possible to provide a semiconductor device in which subsequent wiring can be easily formed.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the upper surface of the gate electrode formed on the element formation region is substantially the same as the upper surface of the insulating film. Since the semiconductor device is formed at the height, a semiconductor device with excellent flatness can be provided.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects, since the bottom of the insulating film is formed in an overhanging shape, the insulating film can be reliably formed by the insulating film. It is possible to provide a semiconductor device capable of covering the upper part of the trench.

According to a sixth aspect of the present invention, in any one of the first to fourth aspects, the insulating film is formed to extend on the inner wall of the trench, so that the insulating film is formed by the insulating film. It is possible to provide a semiconductor device that can more reliably cover the upper portion of the trench.

According to a seventh aspect of the present invention, in the sixth aspect, the insulating film is formed to extend over the entire inner wall of the trench, so that the insulating performance of the element isolation region is ensured. A device can be provided.

According to the eighth aspect of the present invention, a mask film patterned in a desired pattern is formed on a semiconductor substrate, and the semiconductor substrate is etched to a predetermined depth using the mask film as a mask to form a trench. An insulating film that covers the mask film and covers the top of the trench to form an air gap in the trench is stacked, the insulating film stacked on the mask film is removed, and the insulating film remains only in the mask film pattern. Accordingly, the gap formed in the trench can be minimized in the margin of the element isolation region, so that a method for manufacturing a semiconductor device excellent in miniaturization can be provided.

According to a ninth aspect of the present invention, in the eighth aspect, the mask film is removed, a gate insulating film is formed on the semiconductor substrate, and a conductive film is laminated so as to cover the insulating film. Since the conductive film stacked on the film is removed, the conductive film is left only in a region sandwiched between the insulating films, and the conductive film is patterned and formed as a gate electrode. Can be provided.

According to the tenth aspect of the present invention, the trench is formed in the element isolation region formed to surround the element formation region on the semiconductor substrate, and the trench is formed near the element formation region of the element isolation region. When the mask film is formed on both sides with a desired width, the step of removing the mask film according to claim 9 is performed by removing only the mask film on the element formation region and leaving the mask film on the element isolation region. Since the protective film sandwiched between the semiconductor devices is formed, it is possible to provide a method for manufacturing a semiconductor device in which subsequent wiring can be easily formed.

According to the eleventh aspect of the present invention, in any one of the eighth to tenth aspects, the step of forming the insulating film is performed by forming a first insulating film on the inner wall of the trench by a thermal oxidation method. Then, a second insulating film is laminated so as to cover the mask film and close the trench inside the upper end of the trench, and the insulating film is formed by the first and second insulating films. It is possible to provide a method for manufacturing a semiconductor device capable of closing an upper portion of a trench.

According to a twelfth aspect of the present invention, in any of the eighth to tenth aspects, the step of forming the insulating film is performed by forming a thin film on the inner wall of the trench and the exposed surface of the mask film by the CVD method on the mask film. Stacking a first insulating film, and then stacking a second insulating film so as to cover the mask film and close the trench in the pattern of the mask film above the trench; Since an insulating film is formed using a film, a method for manufacturing a semiconductor device in which an insulating film can be easily formed can be provided.

According to a thirteenth aspect of the present invention, when the mask film is formed of a silicon film in any one of the eighth to tenth aspects, the step of forming the insulating film includes the steps of: Forming a first insulating film on the exposed surface of the mask film, and then laminating a second insulating film so as to cover the mask film and close the trench in the pattern of the mask film above the trench, Since the insulating film is formed using the first and second insulating films, a method for manufacturing a semiconductor device in which the insulating film can be formed reliably can be provided.

According to a fourteenth aspect of the present invention, in the thirteenth aspect, a protective insulating film is formed between the mask film and the semiconductor substrate, and the protective insulating film is patterned in the same manner as the mask film. Since the remaining protective insulating film after removing the mask film is used as a gate insulating film, it is possible to provide a method for manufacturing a semiconductor device which can be formed without deteriorating the performance of an element isolation region.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor device according to the third embodiment of the present invention;

FIG. 10 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention;

FIG. 11 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 12 is a sectional view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view illustrating the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 15 is a sectional view illustrating a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 16 is a sectional view illustrating the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 17 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 18 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 20 is a cross-sectional view illustrating another conventional method for manufacturing a semiconductor device.

FIG. 21 is a cross-sectional view showing a configuration of another conventional semiconductor device.

[Explanation of symbols]

1 semiconductor substrate, 2, 14, 20 mask film, 3, 18
Trench, 4, 12, 15 First insulating film, 5, 1
3, 19 second insulating film, 6 gate insulating film, 7 conductive film, 8 gate electrode, 12 second insulating film, 20a protective film, 50, 51, 52, 53 void, 140 protective insulating film, A element isolation Region, B Transistor formation region.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F032 AA16 AA35 AA54 AC02 BA01 BB01 CA05 CA07 CA17 DA02 DA04 DA23 DA24 DA25 DA30 DA33 DA43 DA53 DA74 DA78 5F040 DA00 DA15 DC01 EC04 EC07 ED03 ED04 EF02 EJ03 EK05 FA05 FA07 FB03 FC21 BD01 BD03 BF02

Claims (14)

[Claims] 1. A trench formed in an element isolation region formed to surround an element formation region on a semiconductor substrate; and a trench formed on the trench with substantially the same width as the trench width, and a void in the trench. A semiconductor device comprising: an insulating film that forms 2. The semiconductor device according to claim 1, further comprising a trench formed to have a desired width on at least one side near the element forming region, which is an element isolation region. 3. The semiconductor device according to claim 2, wherein
In the case where trenches are formed on both sides in the vicinity of the element formation region in the element isolation region, a protective film is provided on the semiconductor substrate in the element isolation region sandwiched between the insulating films formed on the trenches. A semiconductor device characterized by the above-mentioned. 4. The device according to claim 1, wherein an upper surface of the gate electrode formed on the element formation region and an upper surface of the insulating film are formed at substantially the same height. 13. A semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the bottom of the insulating film is formed in an overhang shape. 6. The semiconductor device according to claim 1, wherein the insulating film is formed to extend on an inner wall of the trench.
The semiconductor device according to any one of the above. 7. The semiconductor device according to claim 6, wherein the insulating film is formed to extend over the entire inner wall of the trench. 8. A step of forming a mask film patterned in a desired pattern on a semiconductor substrate, a step of forming a trench by etching the semiconductor substrate to a predetermined depth using the mask film as a mask, Laminating an insulating film covering the film and forming an air gap in the trench by closing an upper portion of the trench, removing the insulating film laminated on the mask film, and removing the insulating film only in a pattern of the mask film; And a step of leaving an insulating film. 9. A step of removing a mask film and forming a gate insulating film on a semiconductor substrate; a step of stacking a conductive film so as to cover the insulating film; 9. The method according to claim 8, further comprising: removing the conductive film, leaving the conductive film only in a region sandwiched between the insulating films; and patterning the conductive film to form a gate electrode. A method for manufacturing a semiconductor device. 10. A trench is formed in an element isolation region formed to surround an element formation region on a semiconductor substrate, and has a desired width on both sides of the element isolation region near the element formation region. When the mask film is formed by removing the mask film according to claim 9, only the mask film on the element formation region is removed, and the mask film on the element isolation region is left and sandwiched by an insulating film. Forming a protective film. 11. The step of forming an insulating film includes forming a first insulating film on an inner wall of the trench by a thermal oxidation method, and then covering the mask film and closing the trench inside the upper end of the trench. 11. The method of manufacturing a semiconductor device according to claim 8, wherein a second insulating film is laminated on the semiconductor device, and the insulating film is formed by the first and second insulating films. . 12. A method for forming an insulating film, comprising the steps of:
A thin first insulating film is laminated on the inner wall of the trench and the exposed surface of the mask film by the VD method, and then the mask film is covered and the trench is closed in the pattern of the mask film above the trench. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the second insulating film is laminated as described above, and the first and second insulating films form the insulating film. Method. 13. When the mask film is formed of a silicon film, the step of forming the insulating film includes forming a first insulating film on the inner wall of the trench and on the exposed surface of the mask film by a thermal oxidation method.
Next, a second step is performed so as to cover the mask film and close the trench in the pattern of the mask film above the trench.
11. The method of manufacturing a semiconductor device according to claim 8, wherein said insulating film is laminated, and said first and second insulating films form said insulating film. 14. A step of forming a protective insulating film between a mask film and a semiconductor substrate, patterning the protective insulating film in the same manner as the mask film, and a protective insulating film remaining after removing the mask film. 14. The method according to claim 13, wherein the semiconductor device is used as a gate insulating film.