JP2002095244A - Regulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily provide a regulator circuit only having a voltage increasing function with a voltage decreasing function without increase in chip size. SOLUTION: The regulator circuit is provided with a first voltage generating circuit 1 that uses transistors M3 and M4 of MOS structure as switching elements to generate desired voltage, and a second voltage generating circuit 13 that generates voltage to be applied to the gates of the transistors M3 and M4 of MOS structure and outputs the voltage. The second voltage generating circuit 13 varies voltage to be applied to the gates of the transistors M3 and M4 of MOS structure according to the voltage level of input voltage Vdd.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a regulator circuit, and more particularly to a switching regulator circuit using a MOS transistor as a switching element.

[0002]

2. Description of the Related Art In order to output a constant voltage irrespective of a change in an input voltage Vdd, a P with a step-up or step-down function is provided.
WM (Pulse Width Modulatio
A switching regulator circuit of the n) type is conventionally used. This switching regulator circuit
In recent years, it has been formed as a semiconductor integrated circuit.

FIG. 3 shows a PWM type switching regulator circuit having a step-up and step-down function and outputting a constant voltage Vout in response to a change in an input voltage Vdd. A MOS-structure transistor is used as a switching element, and a circuit for generating a voltage to be applied to the gate of the transistor is provided.

The NMOS transistors M1 and M2 perform the step-down operation of the switching regulator circuit, and the NMOS transistors M3 and M4 perform the step-up operation of the switching regulator circuit.

At this time, PWM waves having phases opposite to each other are input to the MOS transistors M1 and M2. The opposite-phase PWM waves are also input to the MOS transistors M3 and M4.

When output voltage Vout decreases, MOS
The duty (Duty) of the PWM wave input to the transistors M1 and M3 expands to increase the output voltage,
Conversely, when the output voltage Vout increases, the duty of the PWM wave is narrowed and the output voltage is reduced, so that a stable output voltage Vout can be obtained.

[0007] A sufficiently high voltage must be supplied to the gates of these MOS transistors M1 to M4 in order to increase the efficiency.
It is generated by a booster circuit using a MOS transistor M5 and a diode D1 and a low-pass filter (LPF).

FIG. 4 shows a PWM type switching regulator circuit having only a boosting function. The duty ratio of the PWM waveform input to the gate of the NMOS transistor M4 increases as the input voltage Vdd increases.
When dd = Vout, duty = 100
%, That is, the H level is constant.

When the input voltage further rises, the output voltage also rises. Therefore, when the input voltage greatly fluctuates with respect to a desired output voltage value, it is necessary to use a switching regulator circuit having a boosting and step-down function shown in FIG.

However, depending on the specification, Vdd ≦ V
It operates as out, and the input voltage may slightly exceed the output set value in rare cases. Even with such specifications, a desired output voltage cannot be obtained unless the configuration shown in FIG. 3 is used in the conventional method.

[0011]

When the switching regulator circuits of FIGS. 3 and 4 are compared, FIG. 3 shows that the MOS transistors M1, M2 and M require a large area.
It is necessary to provide a circuit for driving the MOS transistors M1 and M2, and to mount the MOS transistors M1 and M2, which operate very rarely, and the drive circuit for driving the MOS transistors M1 and M2, from the viewpoint of chip size There was a problem that I wanted to avoid.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a regulator circuit having only a boosting function and having a simplified step-down function without increasing the chip size.

[0013]

(First Solution) A regulator circuit according to the present invention comprises a first voltage generator for performing a boosting operation using a MOS transistor as a switching element to generate a desired voltage. And second voltage generation means for generating and outputting a voltage to be applied to the gate of the MOS transistor, wherein the second voltage generation means is configured to generate a voltage applied to the gate of the MOS transistor in accordance with an input voltage. Is characterized in that the voltage applied to is varied.

(Second Solution) A regulator circuit according to the present invention performs a boosting operation by using a MOS transistor as a switching element to generate a first voltage to generate a desired voltage.
And a second voltage generating means for generating and outputting a voltage to be applied to the gate of the MOS structure transistor, wherein the second voltage generating means responds to an increase in the input voltage. The voltage value of the voltage applied to the gate of the MOS transistor is reduced, and the first voltage generating means is operated as a series regulator.

[0015]

FIG. 1 shows an embodiment of a regulator circuit according to the present invention.

An input voltage Vdd is connected to one end of the coil L1. The other end of the coil L1 is connected to the drain of the NMOS transistor M3 and the source of the NMOS transistor M4. The source of the MOS transistor M3 is connected to GND. NMOS transistor M
The drain 4 is connected to one end of a low-pass filter (LPF) 3. The other end of the LPF 3 is connected to an output terminal (not shown).

A resistor R1 is connected between the other end of the LPF 3 and GND.
And R2 are connected in series.

The connection point between the resistors R1 and R2 is connected to the non-inverting input terminal of the first operational amplifier 5. One end of a reference voltage source Vref1 is connected to the inverting input terminal of the first operational amplifier 5. The other end of the reference voltage source Vref1 is connected to GND.

The first operational amplifier 5 supplies a difference voltage signal (ERR signal) between the voltage V1 at the connection point between the resistors R1 and R2 and the reference voltage source Vref1 to the inverting input terminal of the first comparison circuit 7.

The first comparison circuit 7 includes an ERR signal supplied to an inverting input terminal and a first ERR signal supplied to a non-inverting input terminal.
And outputs a PWM signal.

The buffer circuit 9 converts the PWM signal whose voltage level is set to VG into an NMOS transistor M
3 gate. The inverter circuit 11 supplies a PWM signal having a phase opposite to that of the buffer circuit 9 to the gate of the NMOS transistor M4.

The first voltage generation circuit 1 is configured as described above.

The input voltage Vdd is supplied to one end of the coil L2. The other end of the coil L2 is connected to the drain of the NMOS transistor M5 and the anode of the diode D1. The source of the MOS transistor M5 is connected to GND. Coil L2 and NMOS transistor M
5 and the diode D1 constitute a booster circuit.

The cathode of the diode D1 is connected to one end of a low-pass filter (LPF) 15. LPF
The voltage VG is output from the other end of the reference numeral 15.

A resistor R is connected between the other end of the LPF 15 and GND.
3 and the resistor R4 are connected in series.

The connection point between the resistors R3 and R4 is connected to the non-inverting input terminal of the second operational amplifier 17. One end of a variable voltage source Vref2 whose supply voltage changes according to the input voltage Vdd is connected to the inverting input terminal of the second operational amplifier 17. The other end of the variable voltage source Vref2 is connected to GND
It is connected to the.

The second operational amplifier 17 includes resistors R3 and R4
Is supplied to the inverting input terminal of the second comparison circuit 19.

The second comparison circuit 19 compares the ERR signal supplied to the inverting input terminal with the second sawtooth wave SS2 supplied to the non-inverting input terminal, and supplies the PWM signal to the gate of the NMOS transistor M5. I do.

Thus, the second voltage generating circuit 13 is configured.

Next, the operation will be described.

The case where Vdd ≦ Vout <VG will be described. When Vout falls below a desired value, V1 which is a partial voltage of the resistors R1 and R2 also falls. Then, since the voltage level of the ERR signal, which is the difference voltage between the voltages V1 and Vref1, decreases, the duty of the PWM signal input from the first comparison circuit 7 and the buffer circuit 9 to the gate of the NMOS transistor M3 increases, and the output voltage increases. V
out rises to a certain desired value. The output voltage V
Even if out falls below the desired value, VG is at the same voltage level.

Next, when Vout rises above a desired value, V1 which is a partial voltage of resistors R1 and R2 also rises. Then, the voltage level of the ERR signal, which is the difference voltage between the voltages V1 and Vref1, increases, so that the duty of the PWM signal input from the first comparison circuit 7 and the buffer circuit 9 to the gate of the NMOS transistor M3 becomes narrower, and the output becomes smaller. Voltage Vout
Decreases to a certain desired value. Note that the output voltage Vout
However, VG is at the same voltage level even if it rises above the desired value.

Under these conditions, the variable voltage source Vref
The voltage value of 2 is the maximum value. Further, the resistance component of the NMOS transistor M4 is sufficiently small, and the NMOS transistor M4 functions as a switching element.

Next, Vout ≦ Vdd ≦ Vou
The case under the condition of t + VF will be described. VF
Indicates a forward voltage drop of the parasitic diode of the NMOS transistor M4.

The input voltage Vdd changes from Vout to Vout +
When the voltage increases up to VF, the voltage value of the variable voltage source Vref2 decreases. Accordingly, voltage VG decreases. This voltage VG is supplied to the buffer circuit 9 and the inverter circuit 11. When the voltage VG decreases, the resistance component of the NMOS transistor M4 gradually increases. Even if the output voltage Vout increases due to the voltage drop of the resistance component of the NMOS transistor M4, the desired desired output voltage is obtained.

As described above, in the range where the conventional regulator circuit of FIG. 4 does not operate normally, the regulator function can be realized without adding a MOS transistor requiring a large area.

Under the condition of Vdd ≧ Vout + VF, the input voltage Vdd becomes Vout + VF because a parasitic diode exists in the NMOS transistor M4.
When the voltage rises further, the parasitic diode of the NMOS transistor M4 turns on. As a result, regardless of the value of the voltage VG, when the input voltage Vdd increases, the output voltage Vout also increases, and it is impossible to obtain a constant desired output voltage.

FIG. 2 shows the variable voltage source Vref2 shown in FIG.
A specific example of a circuit for setting the voltage values of the above will be described.

The input voltage Vdd is input to one end of the resistor R5. The other end of the resistor R5 is connected to one end of the resistor R6 and the gate of the NMOS transistor M6. The other end of the resistor R6 is connected to GND. The source of the NMOS transistor M6 is connected to the source of the NMOS transistor M7, and the reference current source Iref is connected between the common source and GND. NMOS transistor M
The gate of 7 is connected to one end of the reference voltage source Vref3. The other end of the reference voltage source Vref3 is connected to GND.

On the other hand, the drain of the NMOS transistor M7 is connected to the drain and gate of the PMOS transistor M8 and the gate of the PMOS transistor M9. The drain of the NMOS transistor M6 and the sources of the PMOS transistors M8 and M9 are connected to the input voltage Vdd.

The drain of the PMOS transistor M9 is
The drain and the gate of the NMOS transistor M10 are connected to the gate of the NMOS transistor M11. The sources of the NMOS transistors M10 and M11 are G
Connected to ND.

The MOS transistors M8 and M9 and M10 and M11 form a current mirror circuit, respectively.

The drain of the NMOS transistor M11 is connected to one end of the resistor R7 and the inverting input terminal of the operational amplifier 21. The other end of the resistor R7 is connected to the output terminal of the operational amplifier 21.

The reference voltage source Vref4 is input to the non-inverting input terminal of the operational amplifier 21.

Vdd <, which is the range in which the normal boosting operation is performed,
With respect to the voltage value of the input voltage Vdd serving as Vout, M
Resistance value R so that the gate voltage of V ≪ Vref3
5, R6 and reference voltage Vref3 are set. In this case, the reference current Iref is almost the MOS transistor M
7 and is turned back by the current mirror circuit and flows through the resistor R7 via the drain of the MOS transistor M11.

Since the inverting input terminal voltage of the operational amplifier 21 is almost the same as the non-inverting input terminal voltage, the output voltage Vr
ef2 is given by the following equation (1).

Vref2 = Vref4 + R7 × Iref (1) This voltage becomes Vref2 in FIG. And VG is
The following equation (2) is established, and the voltage is set to a value at which the on-resistance of the MOS transistor becomes sufficiently small.

VG = Vref2 × (1 + R3 / R4) (2) Next, when Vdd rises, the gate voltage of the MOS transistor M6 also rises. Then, Iref is divided by the difference between the MOS transistors M6 and M7, and the current value flowing through the MOS transistor M7 gradually decreases as the input voltage Vdd increases.

The current flowing through the resistor R7 is equal to the current Id (M7) flowing through the drain of the MOS transistor M7, and since Vref2 = Vref4 + R7 × Id (M7), Vref2 decreases and VG also decreases.

As a result, the gate-source voltage of the MOS transistor M4 decreases, and the on-resistance increases.

The switching regulator operates as a switch by sufficiently lowering the on-resistance of the MOS transistor.
The voltage drop across the transistor causes the system to operate as a series regulator.

By appropriately setting the relationship between the input Vdd and VG, it becomes possible to control the output voltage Vout to a constant desired value when the input Vdd rises.

Although FIG. 2 shows a circuit example of a MOS transistor, the same effect can be obtained by using a bipolar transistor.

[0054]

As described above, according to the present invention, in a circuit configuration having only the boosting function, it is possible to realize a regulator circuit having a simplified step-down function without increasing the chip size.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a regulator circuit of the present invention.

FIG. 2 is a diagram showing a specific example of a circuit for setting a voltage value of a variable voltage source Vref2 in FIG. 1;

FIG. 3 is a diagram showing a conventional PWM type switching regulator circuit having a step-up and step-down function.

FIG. 4 is a diagram illustrating a conventional PWM switching regulator circuit having a boosting function.

[Explanation of symbols]

Vdd ··· Input voltage, 1 ··· First voltage generating circuit, L1
..Coil, R1, R2 .. resistor, Vref1 .. reference voltage source, M3, M4 .. NMOS transistor, 3 ..
Low-pass filter (LPF), 5 first operational amplifier, 7 first comparator circuit, 9 buffer circuit, 11
..Inverter circuit, 13 second voltage generating circuit, L
2. Coil, M5 NMOS transistor, D1
・ Diode, 15 ・ ・ Low pass filter (LPF),
R3, R4: resistance, 17: second operational amplifier, 19
..The second comparison circuit, Vref2..the variable voltage source.

Claims (4)

[Claims] A first voltage generating means for performing a boosting operation using a MOS transistor as a switching element to generate a desired voltage; and a second voltage generating means for generating and outputting a voltage to be applied to a gate of the MOS structure transistor. 2 voltage generating means, wherein the second voltage generating means is configured to generate the M voltage according to an input voltage.
A regulator circuit which varies a voltage applied to a gate of an OS structure transistor. 2. The regulator circuit according to claim 1, wherein said second voltage generation means reduces a voltage value of a voltage applied to a gate of said MOS transistor as the input voltage increases. . 3. A first voltage generator for performing a boosting operation by using a MOS transistor as a switching element to generate a desired voltage, and a first voltage generator for generating and outputting a voltage to be applied to a gate of the MOS transistor. 2 voltage generation means, wherein the second voltage generation means responds to an increase in the input voltage,
A regulator circuit, wherein a voltage value of a voltage applied to a gate of the MOS transistor is reduced, and the first voltage generating means is operated as a series regulator. 4. The second voltage generating means includes: a voltage dividing means for dividing an input voltage; and a first voltage dividing means for inputting a divided voltage to a gate or a base.
A second transistor having a source or an emitter commonly connected to the first transistor; a reference current source commonly connected to a source or an emitter of the first and second transistors; A reference voltage source for supplying a reference voltage to the gate or base of the transistor; means for turning back a current flowing to the drain or collector of the second transistor; and means for converting this current into a voltage. The regulator circuit according to claim 1.