JP2002094375A - Pll device and optical disk unit having the pll device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that can reduce fluctuations which are caused when a 'Wobble' signal passes through a 'Sync' pattern and attain superior lock time and tracking performance. SOLUTION: The PLL device is provided with a 1st PLL, that receives an input signal and generates a 1st signal in following with the input signal, a 2nd PLL that generates a 2nd signal in following to the 1st signal outputted from the 1st PLL, and a frequency comparator that compares the frequency of the 1st signal generated by the 1st PLL with the frequency of the 2nd signal generated by the 2nd PLL. The frequency comparator is provided with a means, that compares the frequency of the 1st signal with the frequency of the 2nd signal and discriminates as to not only whether the 2nd signal is faster than the 1st signal but also it quantizes a relative quantity of the difference in the frequencies between those of the 1st and 2nd signals, to discriminate locked state of the 2nd PLL and a means that varies a filter characteristic of a loop filter of the 2nd PLL, on the basis of a value quantizing the relative amount of the difference of the frequencies.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PLL (Phase L
More particularly, the present invention relates to a PLL circuit suitable for use in an optical disk device.

[0002]

2. Description of the Related Art In a device for reproducing / recording an optical disk such as a compact disk (especially in the field of recording), a CLV (Constant Linear Velocity) has conventionally been used for writing data while passing a track on the disk surface at a constant speed (constant linear velocity).
A method called “city recording” is widely used.

However, in addition to the reduction in current consumption of the motor for driving the disk for rotation, and the need for high-speed writing and high-reliability recording, the CAV (constant rotation speed) which has not been realized until now has been realized. There is a demand for realizing recording at a constant angular velocity) and writing that follows disk rotation unevenness.

[0004] The CAV rotation control is a technique which has already been established by a reproducing system, and receives a FG signal indicating the number of rotations of the motor generated from the spindle motor and controls the spindle motor so that the FG signal becomes constant. I just need. In signal reading, an RF signal is reproduced based on the presence or absence of a pit detected by a pickup, and the RF signal is compared with a certain value to obtain an EFM (Eight).
to Fourteen Modulation (8-14 conversion modulation) signal.

In the CAV rotation control, since the rotational speed of the disk is constant, the linear velocity of the track is different between the inner circumference and the outer circumference of the disk (for example, the linear velocity corresponding to the quadruple speed on the inner circumference becomes Since this EFM signal is a signal capable of self-clocking, a PLL (“EFM”) that follows the EFM signal is used.
A PLL is used to generate a read channel clock, and this clock makes it possible to capture even the EFM signal having a variable rate into the device.

However, when this is applied to a recording system, even if the rotation control can inherit the technology of the reproduction system, since the pit does not exist on the unrecorded disk to be recorded, the EFM is naturally used. Demodulate the signal,
The read channel clock cannot be generated. In other words, the EFM signal cannot generate a channel clock that follows the writing rate that changes every moment depending on the rotation speed of the disk and the position of the pickup.

[0007] Therefore, W from a meandering guide groove (Wobble) also present on an unrecorded disk.
It is necessary to generate a clock in accordance with the rotation of the disk (angular velocity and position of the pickup) by newly providing a PLL (referred to as “Wobble PLL”) that follows the Wobble signal using the Oble signal.

In order to perform writing while reducing the time error of the pits recorded on the disk, a Wobble PLL that follows a meandering guide groove (Wobble signal) existing on the disk is configured, and a WobblePLL is formed.
A means for outputting an operation clock based on the output of L may be provided to absorb the rotational speed deviation.

As a publication related to a two-stage PLL device, for example, Japanese Patent Application Laid-Open No. 6-338128 proposes a configuration as shown in FIG. FIG.
Referring to FIG. 1, in this disc recording apparatus, FM
P using a 138 MHz VCO (voltage controlled oscillator) to generate an operation clock CK synchronized with the detection PLL 41
LL42, and outputs a write signal in synchronization with an operation clock CK generated by the PLL42. The write signal obtained from a signal processing circuit (not shown) allows recording on a disk via a laser power control circuit. It is done.

Japanese Unexamined Patent Publication (Kokai) No. 61-087427 discloses a PLL circuit having a phase detector, a loop filter, and a voltage controlled oscillator, in which the loop filter is divided into a wide band loop filter and a low band loop filter. A configuration including means for switching according to a phase locked state of a loop circuit is disclosed. FIG. 9 is a diagram showing an example of this conventional configuration. In FIG. 9, a heavy LPF 49 is a low-pass filter having a low cut-off frequency fc, and a light LPF 50 is a low-pass filter having a high cut-off frequency fc. One of these two filters is controlled by switches 47 and 48. , Charge pump 44 and voltage-controlled oscillator (or current-controlled oscillator) 45
Is inserted as a loop filter.

As a double PLL used for a digital audio device or the like that requires a high-precision clock with a small jitter component, for example, Japanese Patent Application Laid-Open No. 4-313817 discloses a first PLL which receives an input signal and synchronizes with the input signal. And a second PLL that receives the first signal and generates a second signal synchronized with the first signal, wherein the second PLL has a phase of the first signal. Phase comparator for comparing the phase of the second signal with the phase of the second signal, a filter for passing only a predetermined frequency component included in the comparison result output from the phase comparator, the phase of the first signal and the phase of the second signal A phase shift detection circuit for detecting a shift amount of the filter and outputting a detection result according to the shift amount; a cut-off frequency varying means for changing a cut-off frequency of the filter according to a detection result from the phase shift detection circuit; Configuration with a signal generating means for generating a second signal by receiving a force as a control signal is disclosed.

[0012]

SUMMARY OF THE INVENTION However, Wob
The use of the ble signal causes a new problem.
It is because this Wobble signal has a very long Syn
Since the c (synchronous) pattern exists,
L means that, for example, it swings about 5 to 10% when passing through a Sync (synchronous) pattern.

[0013] In order to prevent this shaking,
Although it is conceivable to lower the cut-off frequency fc of the PLL loop filter, the pull-in time can be reduced,
In order to improve the followability, the cutoff frequency fc cannot be lowered to a certain extent (decreasing the cutoff frequency fc is also referred to as “weighting”).

On the other hand, when the cutoff frequency fc of the loop filter of the Wobble PLL is high (light), Sync
In addition to the problem of shaking that occurs at the time of passing through the pattern, there is also a problem that the jitter of the clock increases.

Therefore, a PLL (CAV) in which a loop filter is set heavier is provided at the subsequent stage of the Wobble PLL.
A configuration is also conceivable in which the oscillation is prevented by applying a double PLL (PLL). However, if the filter is made heavy, the CAVPLL also causes problems such as an increase in the pull-in time and a deterioration in the follow-up performance. In this case, the problem of an increase in jitter will occur.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to reduce the fluctuation that occurs when a Wobble signal passes through a Sync pattern and to achieve a good pull-in time and follow-up performance. It is to provide a PLL circuit to achieve.

[0017]

According to the present invention, there is provided a first PLL for receiving an input signal and generating a first signal following the input signal, and an output signal from the first PLL. A second PLL that generates a second signal that follows the first signal, and the first signal that is generated by the first PLL and the second PLL that is generated by the second PLL. A frequency comparison circuit that compares the frequencies of the signals, wherein the frequency comparison circuit compares the frequency of the first signal with the frequency of the second signal.
Not only is the second signal earlier or later than the first signal, but also the frequency of the first signal and the second
Means for quantitatively determining the relative amount of the difference between the frequencies of the signals.

In the present invention, the frequency comparison circuit may include:
Means for variably setting a set value relating to a relative amount serving as a reference for the difference between the frequency of the first signal and the frequency of the second signal; and the frequency of the first signal and the frequency of the second signal. Is within the set value, it is determined that the second PLL is in the locked state, and the difference between the frequency of the first signal and the frequency of the second signal is equal to the set value. If the number exceeds the threshold value, it is determined that the vehicle is in the unlocked state, and the determination result is output as a lock signal of the second PLL.

In the present invention, the second PLL includes a plurality of filters having different filter characteristics as loop filters, and switching means for switching the plurality of filters. The switching means changes the filter characteristics of the loop filter by switching the plurality of filters based on the locked state of the PLL.

[0020]

Embodiments of the present invention will be described. In a preferred embodiment of the PLL device of the present invention, referring to FIG. 1, a first PLL (10) which receives a Wobble signal and a Wobble PLL are provided.
Of the second PLL (2
0) are connected in cascade, and not only does the frequency comparison of the two PLL outputs be fast or slow, but also the difference between the frequencies of the two outputs, such as what percentage of the frequency is higher or lower. Means (205) for quantitatively determining the relative amount within a predetermined range is provided.

More specifically, the PLL device comprises two PLs.
A means for externally variably setting a relative amount as a reference for the difference between the frequencies of the L output (register 30 in FIG. 1) and the difference between the frequencies of the two PLL outputs are within the set value. In such a case, it is determined that the subsequent PLL is in the locked state. Conversely, if there is a frequency difference exceeding the set value, it is determined to be in the unlocked state, and the comparison determination result is used as the lock (LOCK) signal of the second PLL. And a frequency comparison circuit (205) that outputs the result.

The second PLL (20) includes two filters and a means for switching the filters, and switches between the two filters using the lock signal of the second PLL, so that the cutoff frequency of the filters ( The filter characteristics such as fc) are varied.

Based on a lock signal indicating whether or not the second PLL (20) is locked, the second PLL (20)
If is locked, select (connect) a filter with a lower (heavy) cut-off frequency between the two filters.
In the unlocked state, switching control is performed to select (connect) a filter having a higher (lighter) cutoff frequency from the two filters.

The second PLL (20) includes two filters and means for switching between the two filters.
L lock signal and a lock signal (Wobble) indicating whether the first PLL (10) is locked to the input signal.
PLL lock signal) and a selection signal indicating which one of the two filters is currently connected is used to switch between the two filters using the values of the three signals. Frequency (f
c) is changed.

The lock signal (Wo) of the first PLL (10)
bble PLL lock signal) and a second PLL (2
Any one of the lock signals (0) (output of the frequency comparison circuit 205) indicates an unlocked state, and if a light filter is currently connected, the light filter is selected (the state of the light filter is maintained). ).

The lock signal (Wo) of the first PLL (10)
When both the bble PLL lock signal) and the lock signal of the second PLL indicate a locked state, and a light filter is currently connected, a heavy filter is selected (state change).

Regardless of the locked state of the first PLL (10), if the lock signal of the second PLL (20) indicates an unlocked state and a heavy filter is currently connected, a light filter is used. Select (change state).

Regardless of the locked state of the first PLL (10), if the lock signal of the second PLL (20) indicates the locked state and a heavy filter is currently connected, the heavy filter is switched off. Select (keep the heavy filter).

The frequency comparison circuit (205) comprises a first and a second
The frequency difference between the outputs of the PLLs (10, 20) may be determined by dividing the relative amount, that is, what percentage is higher or lower, in several stages. In this case, the means for switching a plurality of filters includes: The cutoff frequency (fc) of the filter may be changed stepwise by switching the plurality of filters stepwise according to the comparison result of the comparing means.

Means for controlling the switching of the filter based on the output of the frequency comparison circuit (205) and the lock signal of the first PLL (10) (hysteresis lock state machine 2)
06) is a sampling means for performing a filter switching determination interval at a certain cycle, a continuous number counting means for counting the result of continuous determination when the switching determination is made, and an external means. Means for setting the number of continuous times of the continuous number counting circuit, and the filter may be switched when the number of continuous times reaches an externally set value.

The frequency comparison circuit further includes a second P
A frequency at which the relative amount that the frequency difference between the clock generated by the LL (20) and the constant oscillation signal oscillating at a constant frequency such as a crystal oscillator is high or low is determined in several stages. A comparison circuit (205B), wherein even if the frequency of the clock generated by the first PLL (10) changes in accordance with the change in the frequency of the signal input from the outside, the plurality of the plurality The filter may be switched stepwise, and the cutoff frequency (fc) and time constant of the filter may be changed stepwise.

In one embodiment of the present invention, Wob
Not only whether the ble clock and CAV clock are early or late, but also quantitatively determine the relative amount such as what percentage of the frequency is high or low, and detect the lock state of the CAVPLL within a certain range (lock allowable range). By doing so, it is possible to prevent the CAVPLL from locking to the wrong frequency and to shorten the CAVPLL lock time.

For example, the difference between the frequency of the Wobble clock output from the first PLL (10) and the frequency of the CAV clock output from the second PLL (20) is 3
If it is 0%, then the second PLL (CA
If the loop filter of the VPLL is switched to a heavy filter, the pull-in sensitivity as the CAVPLL is reduced, and the frequency fluctuation of the CAVPLL becomes very large until the frequency difference becomes less than 5%. It takes a considerable amount of time for the movement to be slow. On the other hand, when the frequency difference between the Wobble clock and the CAV clock becomes 0.1%, the second PLL (CAV
When the loop filter of the PLL is switched to a heavy filter (the lock allowable range serving as a reference for switching is set to 0.1).
%), It is not known whether the second PLL is actually pulled in within 0.1%, and there is a possibility that the second PLL will not be switched forever. This is because both the two PLLs have high sensitivity and thus have large frequency fluctuations. That is,
When the frequency of the Wobble clock and the CAV clock are too far apart, it takes time to pull in even if the filter is switched, and conversely, the Wobble clock and the CAV clock
Even if it waits until the clock frequencies become infinitely long, there is a possibility that the switching of the filter will not be performed forever, and in one embodiment of the present invention, the quantitative range of the switching of the filter ( A value suitable for the system can be variably set by the microcomputer or the like via the register (30) by the microcomputer or the like.

Further, in the present invention, in order to more reliably perform the lock determination, the hysteresis lock state machine (206) sets the number of determinations (the number of continuous locks) to a plurality of times to control the filter switching. In this case, for example, each determination method of four consecutive times within a frequency difference of 1%, eight consecutive times within a frequency difference of 2%, and 16 consecutive times within a frequency difference of 4% is freely set.
Here, it can be said that the determination based on the quantitative value based on what percentage of the frequency difference defines the tracking characteristic of the PLL, and the number of consecutive times (number of determinations) defines the stability of the PLL. In a case where the difference between the frequency of the Wobble clock output from the first PLL and the frequency of the CAV clock output from the second PLL is 2% to 5%, the frequency may approach, but the fluctuation is large. And 3% ~
In the case of 4%, in the case where the distance is not so close but the fluctuation is small, whether to lock the two PLLs more is controlled by switching the filters based on the above-described condition.

[0035]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; First, the premise of an embodiment of the present invention will be described. In an optical disk reproducing / recording apparatus such as a compact disk, uneven rotation of the disk occurs due to eccentricity of the disk or turntable, cogging of a spindle motor, or the like. When performing writing while following the rotational speed deviation and reducing the time error of the pit recorded on the disk, a W-like signal that follows a meandering guide groove (Wobble signal) existing on the disk is used.
The rotational speed deviation may be absorbed by constructing an available PLL and providing a means for outputting an operation clock based on the output of the available PLL. However, since a very long Sync (synchronous) pattern exists in the available signal, the available PLL is used. When passing through it,
It shakes about 10%. To prevent this shaking,
To make the loop filter of the Wobble PLL heavy,
In order to shorten the pull-in time and improve the followability, there is a limit that the weight can only be increased to a certain extent,
Conversely, if the loop filter is light, there is a contradiction that jitter increases in addition to the problem of fluctuation occurring when the sync pattern passes.

Therefore, a configuration in which a PLL having a heavier loop filter is further applied to the subsequent stage of the Wobble PLL to prevent oscillation can be considered.
Similarly, in the subsequent PLL, if the filter is made heavier, the pull-in time is increased and the followability is deteriorated. Conversely, if the filter is made lighter, a problem of an increase in jitter occurs.

When CAV (constant angular velocity) recording is performed, a WobbleP for detecting a disc rotation speed deviation is used.
Since the output frequency of the LL fluctuates greatly, there is a problem that if the fluctuation is not immediately followed, time is required for generating an operation clock and the preparation for writing is delayed.

Therefore, in one embodiment of the present invention, a PLL (“CAVPL clock”) for generating an operation clock (referred to as “CAV clock”) synchronized with the output of the Wireless PLL (referred to as “Wobble clock”).
L)), a plurality of loop filters having different filter characteristics are provided, and the filters are switched based on the locked state of the Wobble PLL and the CAVPLL. This solves the above problem, and writes data using an operation clock generated by the CAVPLL. A signal is generated.

A configuration in which a plurality of filters are provided and switched is as follows.
As described above, Japanese Patent Application Laid-Open No. 4-313917 and the like (see FIG. 9) have also proposed,
In contrast to the configuration described in JP-A-13917, the PLL device according to one embodiment of the present invention has the following configuration.

Wo output from Wobble PLL
bble clock and CAV output from CAVPLL
Not only whether the clock is early or late, but also what percentage of the frequency is high or low, the relative amount is quantitatively determined and the filter is switched.

If the frequency difference between the Wobble clock and the CAV clock is within a reference value set externally via a microcomputer or the like, it is determined that the CAVPLL is in a locked (LOCK) state. If there is the above frequency difference, it is determined that the vehicle is in an unlocked (UNLOCK) state.

If the filters connected to the CAVPLL are of two different cutoff frequencies, the LOCK signal is used. If it is determined that the CAVPLL is in the locked state, the cutoff frequency is low. Control to select (connect) a (heavy) filter as a loop filter, and to select (connect) a filter with a high cutoff frequency (light) as a loop filter when it is determined that the filter is in an unlocked state. Is performed.

Further, a LOCK signal indicating the lock / unlock state of the CAVPLL, a LOCK signal indicating the lock / unlock state of the Wobble PLL, and which of the plurality of filters is currently connected as the loop filter. The two filters are switched using the values of the three selection signals shown.

The configuration for switching between the two filters using the values of these three signals is as follows: a LOCK signal of a WobblePLL and a CAVPLL
LOCK signal indicates an unlocked state, and if a light filter is currently connected, the light filter is selected (the state of the light filter is maintained). LOCK signal of the Wobble PLL And CAVPLL
LOCK signal indicates a locked state, and if a light filter is currently connected, a heavy filter is selected (state change). CA irrespective of the locked state of the Wobble PLL,
The LOCK signal of the VPLL indicates an unlocked state, and
If a heavy filter is currently connected, select a light filter (change the state). CA regardless of the locked state of the Wobble PLL
If the LOCK signal of the VPLL indicates a locked state and a heavy filter is currently connected, the heavy filter is selected (the state of the heavy filter is maintained).

When there are two or more filters connected to the CAVPLL, the relative amount that the frequency difference between the Wobble clock and the CAV clock is higher or lower by several percent is determined in several stages. Switches a plurality of filters.

Sampling means for performing a determination interval for switching a plurality of filters at a certain cycle, and a continuous number count for counting the determination result when the switching determination is made continuously and the same. Means, and means for setting the number of continuous times of the continuous number counting circuit from outside, and only when the number of continuous times reaches a value set from outside,
The point that two or a plurality of filters can be switched, the frequency difference between a CAV clock generated by a CAVPLL and a constant oscillation signal that oscillates at a constant frequency such as crystal oscillation is higher or lower by a certain percentage. The filter can be switched by frequency comparison means that determines the relative amount in several steps, and even if the frequency of the Wobble clock changes with the change in the frequency of the Wobble signal, the result of the frequency comparison means allows the plurality of filters to be switched. Switch the filter step by step.

One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, one embodiment of the present invention is:
In an optical disk reproducing / recording apparatus such as a compact disk, a first PLL (FM detection PLL: WobbleP) is used.
LL) 10 and a second PLL (138 MHz VCO: C
AVPLL) 20. The CAVPLL 20 includes a phase frequency comparison circuit (PFC) 201 and a charge pump (C
P) 202, a voltage controlled oscillator (VCO or current controlled oscillator) 203, and a frequency divider (DIV) 204,
Further, a programmable frequency comparison circuit (Program)
able FC) circuit 205 and a hysteresis lock state machine (Hysteresis Lock St).
ateMachine) circuit 206, two loop filters (LPF) 210 and 211 having different time constants, and switches 208 and 209, and two filters 21.
The configuration is such that the connections of 0 and 211 are switched. An output (control signal) from the hysteresis lock state machine circuit 206 is input to a control terminal of the switch 209.
The output from the hysteresis lock state machine circuit 206 is connected to the control terminal of the switch 208 by the inverter 207.
And the switches 208 and 209 are complementarily turned on and off.

The phase frequency comparison circuit 201 has two inputs and outputs the output signal Wo of the Wobble PLL 10.
bble clock as a reference clock (Reference)
clock), a frequency-divided signal of the CAV clock, which is an output signal of the CAVPLL, is input as a signal to be compared, and an error signal corresponding to a frequency difference and a phase difference between these two signals is output. In the PLL circuit, feedback control is performed to eliminate the phase difference.
When the PLL circuit 20 is locked, the changing points of the reference signal and the compared signal have a relationship of coincidence.

When a phase error signal output from the phase frequency comparison circuit 201 is input to the charge pump 202, the charge pump 202 converts the phase error signal into a desired voltage value and outputs it.

The loop filter selected by the switch among the two filters 210 and 211 smoothes the output voltage of the charge pump 202 and supplies the output to the voltage controlled oscillator 203 as a control voltage.

The loop filter plays an important role in determining the PLL type, next, and response, which determines the response of the PLL. A general loop filter includes a lag-lead filter and an active filter. In the present invention, any filter configuration can be used, and there is no particular limitation on the configuration.

The voltage-controlled oscillator 203 receives the output voltage of the loop filter as a control voltage signal and changes the output frequency according to the control voltage. If the output of the loop filter changes the current value, it may be constituted by an ICO (current control oscillator). Alternatively, the output voltage of the loop filter may be converted to a current by a voltage-current converter (VI converter), and the ICO may oscillate at a frequency corresponding to the current value.

The frequency divider 204 divides the output frequency of the voltage controlled oscillator 203 to a desired frequency.

Programmable frequency comparison circuit 205
Is the output clock of the Wobble PLL 10, ie, W
Within what percentage (ratio) of the frequency of the obble clock, C
The frequency difference relative amount of whether the frequency of the output clock of the AVPLL 20, that is, the CAV clock is included, is quantitatively detected.

Further, through a microcomputer (not shown) or the like,
A reference value is set in the register 30 from outside the PLL, and the programmable frequency comparison circuit 205
With reference to the reference value set in, if the relative amount of the frequency difference is within the reference value, the CAVPLL 20
It is determined that the clock is locked to the bble clock (LOCK), and if the relative amount of the frequency difference is not within the reference value, it is determined that the CAVPLL 20 is not locked to the wobble clock (UNLOCK), and the lock is determined. CAVLO of logical value according to state / unlock state
Outputs the CK signal.

Programmable frequency comparison circuit 205
Is the Wobble in quantifying the frequency difference.
A configuration may be adopted in which the number of CAV clocks is counted in one clock cycle obtained by dividing the clock, and the difference between the two frequencies is quantified. When the Wobble clock is divided by, for example, 128, and one cycle of the divided clock includes 128 CAV clocks,
Frequency difference is 0%, CAV clock is 127 (129)
In the case of the clock, it is quantified and calculated to be 0.008%. In this case, the Wobble clock is set to 1
The counter is reset at the rising edge of the signal divided by 28, and the CAV clock is counted as the clock of the counter. At this time, by latching how much the value of the counter was immediately before resetting, it is possible to know to which of 128 +/- the value has advanced.

On the other hand, a hysteresis lock state machine (Hysteresis LockState Mac)
hine) circuit 206, referring to FIG.
The LOCK signal output from the le PLL 10 and the CAV
Means 206-1 for determining the current optimum loop filter by using the LOCK signal of PLL 20 and the filter selection state immediately before (information on which filter is selected is held in a latch circuit or the like). And a sampling means 206-2 for controlling the loop filter switching determination interval at a certain cycle, and a continuous counting for counting the result when the determination result is continuously the same when the switching determination is made. A number counting means 206-3 and a means 206-4 for setting the number of continuous times of the continuous number counting means based on the number of locks and the number of unlocks set in the register 30 through a microcomputer or the like are provided to control switching of the loop filter. , A selection signal for switching. The sampling means 206-2 performs sampling of the LOCK signal by a reset signal or the like of the programmable frequency comparison circuit 205. In this case, the cycle of performing the comparison determination of the programmable frequency comparison circuit 205 is the same as that of the continuous number counting means 206-3. This is the sampling period.

For example, when “select a light filter”,
When the number of consecutive times is detected, a signal for actually switching to a light loop filter is output when the number of continuous times is detected, and when "heavy filter is selected", a signal for actually switching to a heavy loop filter is output when the number of continuous times is detected for eight consecutive times. Thus, it is configured such that it can be set individually depending on the switching direction. With such a configuration, a reliable filter switching signal can be generated.

When two types of filters are used, a light LPF is set to have a time constant almost the same as that of the Wobble PLL, so that the WLP can quickly follow the Wobble PLL (that is, the followability is improved and the pull-in time is shortened). FIG. 4 shows that the heavy LPF is set to be about five times the cutoff frequency fc of the light LPF (the cutoff frequency fc is about １ ／) to reduce the jitter and to smoothly follow the rotation unevenness. In this way, it has been verified from actual simulation results. As shown in FIG. 4, when unlocked, a clock (CL
K), the jitter (variation of edges) is reduced by connecting to a heavy filter at the time of locking.

The loop filter is made lighter by reducing the value of R (resistance) or C (capacitance) from fc = 1 / (2πRC) [Hz] for the cutoff frequency fc. Increasing the off-frequency is equivalent to increasing the off-frequency, and conversely, increasing the value of R (resistance) or C (capacitance) is equivalent to decreasing the cut-off frequency. In FIG. 1, it is a matter of course that instead of providing the two filters 210 and 211, the filter constant of one loop filter may be varied to vary the filter characteristics such as the cutoff frequency.

According to the present invention, the programmable frequency comparison circuit 205, the hysteresis lock state machine circuit 206, and the two types of loop filters 210 and 211 having different time constants are newly added to the present invention. It is possible to select an optimal loop filter even for fluctuations caused by passing through a Sync pattern and the like, thereby solving the problems of pull-in time, followability, and jitter.

The operation of one embodiment of the present invention will be described.

First, the programmable frequency comparison circuit 20
5 will be described. In the programmable frequency comparison circuit 205, the output of Wobble PLL 10, W
OBLL clock and CA which is the output of CAPLL 20
The frequency of the V clock is compared. This frequency comparison is
Not only whether the CAV clock is earlier or later than the available clock, but also the frequency difference relative amount as to what percentage (ie, a quantitative value such as a ratio) of the available clock is included in the CAV clock is quantitatively detected.

Further, a reference value can be variably set in the register 30 from outside through a microcomputer or the like.
If the relative amount of the frequency difference is within the reference value, CAV
PLL 20 Locks to Wobble Clock (LOC
K) (frequency match: CAVPLL LOCK)
Or if the relative amount of the frequency difference is not within the reference value, the CAVPLL 20
e is not locked (LOCK) to the clock (frequency mismatch: CAVPLL UNLOCK) and CAV
Outputs a LOCK signal. In other words, what percentage of frequency shift
It is possible to judge whether to consider LOCK from within,
The frequency error allowable range (lock allowable range) can be freely set externally through a microcomputer or the like.

This plays an important role in generating a filter selection signal in the hysteresis lock state machine circuit 206.

Next, the hysteresis lock state machine circuit 206 will be described. The hysteresis lock state machine circuit 206 is an LC of the Wobble PLL 10.
OK determination signal and programmable frequency comparison circuit 205
A selection signal for selecting an optimum loop filter to be connected is generated based on the quaternary state obtained from the LOCK determination signal of the CAVPLL 20 and the connection state of the currently selected filter.

The hysteresis lock state machine circuit 206 detects the number of consecutive times of the selection signal for making the filter heavier or lighter. The number of consecutive times is determined by a filter or the like which can be freely and externally switched by a microcomputer or the like. Each weight can be set individually. The hysteresis lock state machine circuit 206 having such a configuration can generate an optimum filter selection signal.

FIG. 2 shows two types of filters, a currently selected state, a locked state of the Wobble PLL,
FIG. 9 is a state transition diagram for explaining how a loop filter is switched according to a locked state of CAVPLL. FIG. 3 is a flowchart for switching a filter according to an embodiment of the present invention. The hysteresis lock state machine circuit 206 is a state machine (logic circuit) that changes the state (state) according to the state transition diagram shown in FIG.

With the light filter currently selected, the Wobble PLL 10 is unlocked,
In addition, when the CAVPLL 20 is also in the unlocked state, it is a state that can be seen in the initial state and the like, but at this time, it is a state that follows the Wobble PLL and wants to be locked quickly, so that a light filter is selected (the light filter is left as it is) State). The entire reset default state is set so as to be in this state in order to improve follow-up performance and shorten the pull-in time.

When the CAVPLL 20 is in the locked state while the light filter is currently selected and the Wobble PLL 10 is in the unlocked state, the Wobble PLL 10 is following the Wobble signal, and the fluctuating Wobble PLL 10 Since the user wants to follow up quickly, a light filter is selected (the state of the light filter is maintained).

If the CAVPLL 20 is in the unlocked state while the light filter is currently selected and the Wobble PLL 10 is in the locked state, it follows the Wobble PLL 10 promptly,
Since it is necessary to lock the VPLL 20, a light filter is selected (the state of the light filter is maintained).

When the Wobble PLL 10 is locked and the CAVPLL 20 is also locked in a state where the light filter is currently selected, both are in the state of following accurately and should be in a stable state. Since the state is the state, the light filter is switched to the heavy filter (state change).

In short, when stable writing becomes possible, the LPF is switched to a heavy LPF and writing to the disk is started.

Actually, a heavy LP set by the microcomputer
Since the filter is switched to the heavy filter for the first time when the number of consecutive times for switching to F becomes equal to or more, erroneous switching determination can be prevented.

With the heavy filter currently selected, the Wobble PLL 10 is unlocked,
In addition, when the CAVPLL 20 is also in the unlocked state, it is necessary to return to the initial state, for example, when the Wobble signal is suddenly disturbed, and to apply the phase locked loop again, so that the heavy filter is switched to the light filter (state change). ). In short, the fact that the CAVPLL 20 is out of synchronization means that stable writing cannot be assured.
This is because it is necessary to quickly follow an available PLL and make the frequencies coincide.

If the CAVPLL 20 is in a locked state while the heavy filter is currently selected and the Wobble PLL 10 is in an unlocked state, the Wobble signal may be momentarily disturbed or the like.
Since it is conceivable that the blePLL may come off for a moment, a heavy filter is selected (maintaining the state of the heavy filter) without switching the filter unnecessarily.

If the CAVPLL 20 is in the unlocked state while the heavy filter is currently selected and the Wobble PLL 10 is in the locked state, it can be considered that the Wobble PLL 10 is in the stable state and is following correctly. So, WobblePLL1
Select a light filter (change state) because it is desired to quickly follow 0 and lock the CAVPLL 20.
I am trying to do it.

In short, the fact that the CAVPLL has come off means that stable writing cannot be guaranteed, and the connection to the light LPF is made by using the WobblePLL1.
This is because it is necessary to quickly follow 0 and match the frequencies.

When the heavy filter is currently selected, the Wobble PLL 10 is locked, and
When the CAVPLL 20 is also in the locked state, both of them are in a state to follow accurately and are to be in a stable state. Therefore, a heavy filter is selected (a state in which the heavy filter remains as it is).

Once a heavy LPF is connected, Wobb
The locked / unlocked state of the lePLL 10 has no effect on the switching of the filter. At this time, C
When the number of consecutive unlocks of the AVPLL 20 is detected, and when the number of consecutive unlocks of the CAVPLL 20 becomes equal to or greater than the number of consecutive switches for switching to the light LPF set by the microcomputer, the selection signal is generated for the first time. Therefore, an unlock error can be prevented.

Referring to FIG. 3, the hysteresis lock state machine circuit 206 resets the number of continuous locks (step S1), selects a light LPF 211 (step S1), and locks the lock signal of the Wobble PLL 10 and C
The lock signal of the AVPLL 20 is determined (step S
3) If both are locked, the number of consecutive locks is incremented (steps S4 and S5), and if both are not locked, the process returns to step S1.

The number of consecutive locks is compared with the number of consecutive locks set in the register 30 by the microcomputer. If the number of consecutive locks is equal to or greater than the set number of locks (steps S6 and S7), the connection to the heavy LPF 210 is switched (step S8). If the number is equal to or less than the set number of consecutive locks, the process returns to step S1.

Hysteresis lock state machine circuit 2
In step 06, the number of consecutive unlocks is reset (step S
11), select a heavy LPF 210 (step S1)
2) The lock signal of the CAVPLL 20 is determined (step S13). If unlocked, the number of consecutive unlocks is incremented (step S14). If locked, the process returns to step S11.

The number of consecutive unlocks is compared with the number of consecutive unlocks set in the register 30 by the microcomputer. If the number of consecutive unlocks is equal to or greater than the set number of consecutive unlocks (step S1)
6, S17), the connection is switched to the light LPF 211 (step S18), and if the number of locks is equal to or less than the set number of consecutive locks, the process returns to step S11.

For example, at the timing of the reset signal of the frequency comparison circuit 205, the frequency difference between the two clocks is 0.1
%, It is determined that CAVPLL is Wobble.
Since it follows the frequency of the PLL 10, it is determined that locking has been performed, and the lock continuation number counter is incremented to 1; as a result of the next frequency comparison, if the frequency difference between the two clocks is within 0.1%, The lock continuation number counter is further incremented to 2; conversely, if the frequency difference is 0.5%, the lock continuation number counter is reset and the unlock continuation number counter is incremented by one.

As described above, the frequency allowable range, the lock /
The configuration in which the number of consecutive unlocks is freely and individually set from the outside through a microcomputer can reduce lock and unlock errors, thereby improving the processing performance of the system. It is possible to generate an optimum filter selection signal.

Next, a second embodiment of the present invention will be described. FIG. 6 is a diagram showing the configuration of the second exemplary embodiment of the present invention. Referring to FIG. 6, a second embodiment of the present invention employs C
When there are two or more types of filters connected to the AVPLL 20, a plurality of filters are switched by determining the relative amount that the frequency difference between the Wobble clock and the CAV clock is higher or lower by several steps in several stages. .

In programmable frequency comparison circuit 205, Wobbl which is the output of Wobble PLL 10
When comparing the frequency of the e-clock with the CAV clock output from the CAPLL 20, the relative amount of the frequency difference is set to, for example, 1
%, Within 2%, and within 4%, and if it is within 1%, the filter is switched to the heaviest filter, and if within 2%, the filter is switched to the next heaviest filter. Which filter is connected within which percentage can be freely set through a microcomputer or the like.

In the second embodiment of the present invention, by providing three or more filters having different characteristics,
In this embodiment, the most suitable filter can be selected as needed.

Next, a third embodiment of the present invention will be described. FIG. 7 is a diagram showing the configuration of the third exemplary embodiment of the present invention. Referring to FIG. 7, in the third embodiment of the present invention, Wobb output from Wobble PLL 10 is used.
le clock and C generated by CAVPLL 20
A programmable frequency comparison circuit 205B is provided in addition to the programmable frequency comparison circuit 205A for comparing the difference between the frequencies of the AV clocks.
The frequency of the AV clock (output of the frequency divider 204) is compared with the frequency of a constant oscillation signal that oscillates at a constant frequency such as the crystal oscillator Xtal, and the frequency difference is determined by what percentage is higher or lower. The relative amount is determined in several stages.

The result of stepwise detection of the CAV clock and the constant oscillation signal by the programmable frequency comparison circuit 205B and Wob by the programmable frequency comparison circuit 205A
ble clock and CAV clock frequency comparison result,
In the mixer (Mix) 250, the plurality of filters 241 to 245 are switched using the result of mixing. The mixer 250 includes a programmable frequency comparison circuit 205A,
A predetermined weight is given to the comparison result of 05B, and a filter is selected.

That is, even when the frequency of the Wobble clock changes with the change in the frequency of the Wobble signal, the mixer (Mix) 250 keeps the constant frequency and the CA
The plurality of filters 241 to 245 are switched stepwise according to the frequency comparison result of the programmable frequency comparison circuit 205B that compares the frequency of the V clock.

Two programmable frequency comparison circuits 20
The allowable frequency error ranges of 5A and 205B are separately set from the outside through a register 30 through a microcomputer (not shown) or the like.

The filter is selected not only by the relative frequency difference between the Wobble clock and the CAV clock but also by the CAV clock and a constant frequency (absolute frequency). In this case, the optimum filter can be selected as appropriate.

[0095]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention is that the W of the first PLL is
Not only is it possible to determine whether the frequency of the obble clock and the CAV clock of the second PLL is early or late, but also to determine the relative amount quantitatively, such as what percentage of the frequency is high or low, and lock and unlock by referring to the frequency range. The detection means that locking and unlocking errors can be reduced.

The second advantage of the present invention is that
CAV of frequency comparison between clock and CAV clock
By adopting a configuration in which the LOCK determination condition (within what percentage) is freely set externally through a microcomputer or the like, it is possible to reduce lock and unlock errors and improve the system performance. .

The third effect of the present invention is that the cut-off frequency of the filter of the second PLL is switched using the lock signal of the second PLL, and it is determined that the second PLL (CAVPLL) is in the locked state. In this case, by selecting (connecting) a filter having a low (heavy) cutoff frequency, Wo
It operates to reduce the jitter of the bble signal when passing through Sync and reduces the jitter. When it is determined that the unlocked state is established, a filter having a high (light) cutoff frequency is selected (connected). That is, it is possible to shorten the pull-in time and improve the followability.

The fourth effect of the present invention is that the second PLL (C
APLL lock signal and a first PLL (Wobb)
lePLL) and an optimum loop filter can be selected by using the values of three signals of a lock signal and a selection signal indicating which filter is currently connected.

The fifth effect of the present invention is that the second PLL (C
When two or more types of filters are connected to the AVPLL, the relative difference that the frequency difference between the Wobble clock and the CAV clock is higher or lower by several percents is determined in several stages to determine a plurality of filters. Can be switched.

The sixth effect of the present invention is that when two or more filter switching judgments are made, if the judgment result is the same continuously, the number of the consecutive times is counted, and the number of continuous times is counted through a microcomputer or the like. By enabling the threshold to be set freely and individually from the outside, a reliable filter selection signal can be generated.

A seventh effect of the present invention is to realize an optical disk device that can follow the rotation unevenness and reduce the jitter.

The eighth effect of the present invention is that the relative amount that the frequency difference between the output (CAV clock) of the second PLL and the constant oscillation signal oscillating at a constant frequency is higher or lower by several% is determined in several steps. By separately judging, according to the frequency change of the Wobble signal, Wob which is the output of the first PLL is output.
That is, even if the frequency of the ble clock changes, the plurality of filters can be switched in a stepwise manner.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining a state transition in one embodiment of the present invention.

FIG. 3 is a flowchart illustrating a filter switching process according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining filter characteristics in one embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a hysteresis state machine in one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional PLL.

FIG. 9 is a diagram showing a configuration of a conventional PLL.

[Explanation of symbols]

10 Wobble PLL 20 CAV PLL 201 Phase Frequency Comparison Circuit 202 Charge Pump 203 Voltage Controlled Oscillator (Current Controlled Oscillator) 204 Divider 205, 205A, 205B Programmable Frequency Comparison Circuit 206 Hysteresis Lock State Machine 206-1 Filter Switching Determination Means 206- 2 Sampling unit 206-3 Continuous number counting unit 206-4 Continuous number setting unit 207 Inverter 208, 209, 221-225 Switch 210 Heavy LPF 211 Light LPF 231-235, 241-245 LPF 250 Mixer 30 Register 41 FM detection PLL 42 138 MHz VCO PLL 43 Phase frequency comparison circuit 44 Charge pump 45 Voltage controlled oscillator (current controlled oscillator) 46 Divider 47, 48 Switch 49 heavy LPF 50 light LPF

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5D044 AB05 AB07 BC04 CC06 GK12 GL02 GM02 GM12 GM18 GM31 5J106 AA04 BB03 CC01 CC24 CC31 CC38 CC41 DD32 DD43 DD44 EE08 FF02 FF09 GG07 HH10 KK03 KK30

Claims (25)

[Claims] A first PLL circuit that receives an input signal and generates a first signal that follows the input signal; and a second PLL circuit that follows the first signal output from the first PLL circuit. And a frequency of the first signal generated by the first PLL circuit is compared with a frequency of the second signal generated by the second PLL circuit. A frequency comparison circuit;
The frequency comparison circuit, when comparing the frequency of the first signal and the second signal, not only whether the second signal is earlier or later than the first signal, Means for quantifying a relative amount of a difference between the frequencies of the first signal and the second signal, wherein the second amount is determined based on a value obtained by quantifying the relative amount of the difference between the frequencies by the frequency comparing circuit. A PLL device comprising means for varying a filter characteristic of a loop filter of a PLL circuit. 2. The method according to claim 1, wherein said input signal inputted to said first PLL circuit includes a case where a constant period or a transition edge timing thereof is not constant. PLL device. 3. A means for variably setting a set value of a relative amount serving as a reference to a relative amount of a difference between the frequency of the first signal and the frequency of the second signal, When the relative amount of the difference between the frequency of the first signal and the frequency of the second signal is within the given set value,
When it is determined that the second PLL circuit is in the locked state, and when the difference between the frequency of the first signal and the frequency of the second signal exceeds the set value, the unlocked state is determined. 3. The PLL according to claim 1, further comprising: a unit that determines that the second PLL circuit is a lock signal and outputs a result of the determination as a lock signal of the second PLL circuit.
apparatus. 4. The second PLL circuit includes, as a loop filter, a plurality of filters having different filter characteristics, and switching means for switching the plurality of filters, and whether the second PLL circuit is locked. The PLL according to any one of claims 1 to 3, wherein the switching unit switches the plurality of filters based on a lock signal indicating whether or not the switching filter changes, thereby changing a filter characteristic of the loop filter. apparatus. 5. The second PLL circuit includes at least two filters having different cutoff frequencies as loop filters, and the switching unit is configured to switch the two PLL circuits based on the lock signal of the second PLL circuit. Switching of filters is controlled. At this time, when the lock signal of the second PLL circuit indicates a locked state, a filter having a lower cutoff frequency (referred to as a “heavy filter”) among the two filters is used. And selecting, when the lock signal of the second PLL circuit indicates an unlocked state, a filter having a higher cutoff frequency (referred to as a “light filter”) among the two filters. The PLL device according to claim 4, wherein: 6. The apparatus according to claim 1, wherein the second PLL circuit includes a plurality of filters having different filter characteristics as the loop filter;
Switching means for switching the plurality of filters, wherein the switching means outputs a lock signal indicating whether or not the second PLL circuit is locked, and the first PLL circuit outputs the lock signal to the first PLL circuit. A lock signal indicating whether or not the input signal is locked, and information indicating which filter is currently connected among the plurality of filters, the plurality of filters are switched, and the loop filter is switched. 4. The PLL device according to claim 1, wherein a filter characteristic is varied. 7. The switching means according to claim 1, wherein said switching means is configured to determine whether said first PLL circuit is locked or not, based on said first PLL circuit lock signal and said second PLL circuit lock signal. A switch for controlling the switching between the two filters; and when it is determined that the first PLL circuit and the second PLL circuit are in a locked state, a filter having a lower cutoff frequency among the two filters. ("Heavy filter") is selected, and when it is determined that the unlocked state is established, a filter having a higher cutoff frequency ("light filter") is selected from the two filters. The PLL device according to claim 5, wherein: 8. A case where at least one of the lock signal of the first PLL circuit and the lock signal of the second PLL circuit indicates an unlocked state and a light filter is currently connected. In the switching means, the state in which the light filter is kept selected is maintained in the switching means, and the lock signal of the first PLL circuit and the second PLL
If both of the circuit lock signals indicate a locked state and a light filter is currently connected, the switching means switches to select a heavy filter, and the locked state of the first PLL circuit is selected. Regardless, when the lock signal of the second PLL circuit indicates an unlocked state and a heavy filter is currently connected, switching is performed by the switching means so as to select a light filter. Regardless of the lock state of the first PLL circuit, when the lock signal of the second PLL circuit indicates the lock state and a heavy filter is currently connected, the heavy filter 6. The method according to claim 5, wherein
LL device. 9. The frequency comparison circuit of the second PLL circuit, wherein a frequency difference between the first signal and the second signal is:
Means for determining the relative amount of what percentage is higher or lower by several percentages in a plurality of stages, wherein the second PLL circuit includes a plurality of filters as a loop filter; Switching means, and means for switching the plurality of filters in a stepwise manner according to the comparison result of the frequency comparison circuit, so that the cutoff frequency (fc) of the filter can be changed stepwise.
The PLL device according to claim 1, wherein: 10. A sampling means for making a judgment interval for switching said plurality of filters at a predetermined period, and a method for judging when a judgment of switching is made continuously is the same. A continuous number counting means for counting the result, and a means for externally setting the number of continuous times of the continuous number counting circuit. When the number of continuous times reaches a predetermined value, two or more 10. The PLL device according to claim 1, wherein the filter is switched. 11. The second PLL circuit according to claim 2, wherein:
The frequency difference between the second signal generated by the LL circuit and the constant oscillation signal from the oscillation circuit that oscillates at a constant frequency is:
A second frequency comparison circuit that determines the relative amount of how high or low the ratio is divided into several stages, and further includes a plurality of filters, and a unit that switches the plurality of filters, A first PLL circuit generated by the first PLL circuit according to a frequency change of a signal input to the first PLL circuit;
Even if the frequency of the signal changes, the filter characteristics including the cutoff frequency of the filter are changed stepwise by switching the plurality of filters stepwise according to the result of the second frequency comparison circuit, and always changing. 10. The PLL device according to claim 9, wherein optimal followability can be guaranteed. 12. A first PLL circuit for receiving an input signal and generating a first signal following the input signal, and receiving the first signal output from the first PLL device as an input. A second PL that generates a second signal that follows the first signal
An L circuit, wherein the second PLL circuit divides an output signal of the signal oscillator by a signal oscillator including a voltage controlled oscillator or a current controlled oscillator oscillating at a frequency corresponding to a given control signal. A frequency divider, a phase frequency comparison circuit for comparing a phase difference and a frequency between the output of the first PLL circuit and the output of the frequency divider, and a signal corresponding to the phase difference detected by the phase frequency comparison circuit And a loop filter for smoothing the output of the charge pump. The output of the loop filter is supplied to the signal oscillator as the control signal, and the second PLL circuit further includes: The first signal from the first PLL circuit and the output signal of the frequency divider are input and the relative difference between the frequencies is determined by determining the difference between the frequencies. A frequency comparison circuit that determines whether or not the second PLL circuit is in a locked state by referring to a lock allowable setting range in which the value is variably set; and a plurality of loop filters having different filter characteristics as the loop filter. A filter, a switch connecting any one of the plurality of filters as the loop filter between an output terminal of the charge pump and an input terminal of the signal oscillator, and whether the first PLL circuit is locked. Controlling the switch based on a first lock signal indicating whether the second PLL circuit is locked or not, and a second lock signal indicating whether the second PLL circuit is locked, which is output from the frequency comparison circuit. Switching control means for switching a filter serving as a loop filter of the second PLL circuit from among the plurality of filters. Apparatus. 13. The switching control means according to claim 1, wherein:
Based on a lock signal from the circuit, a lock signal of the second PLL circuit, and information on a currently selected filter,
Means for selecting a filter to be connected as a loop filter; sampling means for making a determination of the switching of the loop filter at a predetermined cycle; and when the determination result when the switching is determined is continuously the same, A continuous number counting means for counting the result, and a means for setting the number of continuous times of the continuous number counting means, wherein the locked state continues for a predetermined number of times, or the unlock state continues for a predetermined number of times. 13. The PLL device according to claim 12, wherein the PLL device generates a switching signal of the loop filter with respect to the switch, by managing the loop filter and providing hysteresis. 14. A filter having a relatively high cutoff frequency (referred to as a "light filter").
And a filter having a relatively low cut-off frequency (referred to as a “heavy filter”), wherein the switching control means includes a lock signal of the first PLL circuit and a lock signal of the second PLL circuit. If any one of them indicates an unlocked state and a light filter is currently connected, the switch maintains the state in which the light filter is selected, and the first PLL Circuit lock signal and said second PLL
When both lock signals of the circuit indicate a lock state and a light filter is currently connected, the connection of the switch is switched so as to select a heavy filter, and the lock of the first PLL circuit is performed. Regardless of the state, if the lock signal of the second PLL circuit indicates an unlocked state and a heavy filter is currently connected, the connection of the switch is switched so as to select a light filter. Irrespective of the lock state of the first PLL circuit, when the lock signal of the second PLL circuit indicates the lock state and a heavy filter is currently connected, the heavy filter is directly selected. The connection of the switch is switched so as to perform the connection.
3. The PLL device according to 3. 15. A first PLL circuit for receiving an input signal and generating a first signal following the input signal, and receiving the first signal output from the first PLL device as an input. A second PL that generates a second signal that follows the signal of the first
An L circuit, wherein the second PLL circuit divides an output signal of the signal oscillator by a signal oscillator including a voltage controlled oscillator or a current controlled oscillator oscillating at a frequency corresponding to a given control signal. A frequency divider, a phase frequency comparison circuit for comparing a phase difference and a frequency between the output of the first PLL circuit and the output of the frequency divider, and a signal corresponding to the phase difference detected by the phase frequency comparison circuit And a loop filter for smoothing the output of the charge pump. The output of the loop filter is supplied to the signal oscillator as the control signal, and the second PLL circuit further includes: A lock permitting device which receives the first signal from the first PLL circuit and the output of the frequency divider and variably sets a value of a frequency difference between the first signal and the output of the frequency divider. A frequency comparison circuit for quantitatively comparing and judging with reference to the range; a plurality of filters having different filter characteristics as loop filters; and an output terminal of the charge pump, wherein one of the plurality of filters is used as the loop filter. A switch connected between the input terminals of the signal oscillator; and controlling the switch based on a comparison result of the frequency comparison circuit, from among the plurality of filters, a loop filter of the second PLL circuit. A PLL device for switching a filter. 16. A first PLL circuit for receiving an input signal and generating a first signal following the input signal, and receiving the first signal output from the first PLL device as an input. A second PL that generates a second signal that follows the first signal
An L circuit, wherein the second PLL circuit divides an output signal of the signal oscillator by a signal oscillator including a voltage controlled oscillator or a current controlled oscillator oscillating at a frequency corresponding to a given control signal. A frequency divider, a phase frequency comparison circuit for comparing a phase difference and a frequency between the output of the first PLL circuit and the output of the frequency divider, and a signal corresponding to the phase difference detected by the phase frequency comparison circuit And a loop filter for smoothing the output of the charge pump. The output of the loop filter is supplied to the signal oscillator as the control signal, and the second PLL circuit includes:
Further, the first signal from the first PLL circuit and the output of the frequency divider are input, the difference between the frequencies is determined, and the relative amount of the difference between the frequencies is derived. A first frequency comparing circuit for determining whether or not the second PLL circuit is in a locked state with reference to a lock allowable setting range in which a value is variably set; a signal of a constant frequency; The output of the device is input, and the magnitude of the frequency difference is referred to, and the relative amount of the frequency difference is quantitatively compared and determined with reference to the lock allowable setting range in which the value is variably set. A second frequency comparison circuit; a plurality of filters having different filter characteristics as the loop filter; and the plurality of filters based on a comparison result of the first frequency comparison circuit and a comparison result of the second frequency comparison circuit. Select one of PLL apparatus characterized by comprising said charge pump as a serial loop filter and a means for connecting between the signal oscillator. 17. A phase frequency comparing circuit, a charge pump for generating a signal corresponding to a phase difference detected by the phase frequency comparing circuit, a loop filter for smoothing an output of the charge pump, and an output of the loop filter. A signal oscillator including a voltage-controlled oscillator or a current-controlled oscillator that inputs as a control signal and outputs an output clock having an oscillation frequency according to the control signal, and a frequency divider that divides an output clock of the signal oscillator The phase frequency comparison circuit includes two PLL circuits for detecting a phase difference between the output of the frequency divider and an input reference signal, and the second PLL circuit at the subsequent stage is connected to the first PLL circuit at the previous stage. Is output as a reference signal, and the filter characteristic of the loop filter of the second PLL circuit is changed to the locked state of the first PLL circuit. Wherein the switching is performed according to a locked state of the second PLL circuit. 18. The first PLL circuit and the second PLL circuit
18. The PL according to claim 17, wherein a filter characteristic of the second PLL circuit is switched depending on whether a current state of the L circuit is a locked state or an unlocked state.
L device. 19. The PLL device according to claim 17, further comprising means for giving hysteresis to the transition between the locked state and the unlocked state of the second PLL circuit. 20. A frequency comparison circuit for measuring a difference between a frequency of an output clock of the first PLL circuit and a frequency of an output clock of the second PLL circuit to determine a lock state of the second PLL circuit. The frequency comparison circuit quantitatively determines how fast or slow the difference of the frequencies is, and determines that the second PLL circuit is in a locked state if the difference is within an error allowable range. The PLL device according to claim 17, wherein: 21. A condition for judging the frequency measurement result is as follows:
3. The method according to claim 2, wherein the relative amount is variably designated as a locked state if the frequency difference is within what percentage.
0. The PLL device according to item 0. 22. A condition for judging the frequency measurement result is as follows:
21. The PLL device according to claim 20, wherein the number of times the continuous condition is satisfied is set to the locked state or the unlocked state, or the number of continuous times is variably designated. 23. The PLL device according to claim 22, wherein the designation of the number of consecutive times is individually set according to lock and unlock determination conditions. 24. A plurality of filters having different cutoff frequencies are provided as the loop filter, and a loop filter inserted between the charge pump and the voltage controlled oscillator or the current controlled oscillator is included in the plurality of filters. 18. The PLL device according to claim 17, further comprising a switch for selecting from the following. 25. The PLL according to any one of claims 1 to 24.
The first PLL circuit receives a Wobble signal and
An optical disk device, wherein the second PLL circuit generates an internal clock from the reference clock by generating a reference clock following an obble signal.