JP2002094003A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with which residual film thickness of an interlayer insulating film on a thin-film resistor can be controlled accurately. SOLUTION: After a field oxide film 3 is formed on the surface of a silicon wafer 1, a thin-film resistor 5 and dummy patterns 6 are formed ((a-1), (b-1)), and further a BPSG/NSG film 7, plasma CVD film 9, PSG film 15, organic SOG film 11, plasma CVD film 13, PSG film 15, and silicon nitride film 17 are formed thereon ((a-2), (b-2)). By forming the dummy patterns 6 in the peripheries of the thin-film resistor 5, film thickness 31 of the interlayer insulating film on the thin-film resistor 5 is made to be identical with film thickness 25 of the interlayer insulating film in an opening-forming region for film-thickness monitoring. A trimming-window opening 19 and an opening 21 for film-thickness monitoring are formed simultaneously through dry etching ((a-3), (b-3)). The residual film thickness 33 of the interlayer insulating film on the thin-film resistor 5 is identical with the residual film thickness 35 of the interlayer insulating film in the opening 21 for film-thickness monitoring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film resistor (an element whose resistance can be adjusted by being blown by irradiation with a laser beam) formed on a semiconductor substrate via an insulating film. A trimming window opening for laser trimming is formed in which the thickness of the insulating film is formed thinner than the surroundings, and a method of manufacturing a semiconductor device in which laser trimming is performed on a thin-film resistor through the trimming window opening. In particular, the present invention relates to performing etching for forming a trimming window opening with high accuracy.

[0002]

2. Description of the Related Art Conventionally, in some semiconductor devices, a thin film resistor is provided in advance, and laser trimming for adjusting the resistance value by fusing the thin film resistor by laser irradiation is performed. As a semiconductor device to be subjected to laser trimming, there is a semiconductor device having a material having a high absorptivity of laser light in a part of the thin film resistor irradiated with laser light in order to perform stable laser trimming. See JP-A-9-246468).

In a manufacturing process of such a semiconductor device, a trimming window for irradiating a laser to the thin film resistor is applied to one or more interlayer insulating films formed on the thin film resistor to be laser trimmed. When forming the opening, from the viewpoint of performing stable and accurate laser trimming and the reliability of the semiconductor device, by appropriately forming the trimming window opening, the residual film thickness of the interlayer insulating film existing on the thin film resistor is appropriately adjusted. You need to control the value.

As a method for controlling the residual film thickness of the interlayer insulating film existing on the thin film resistor after forming the trimming window opening,
A metal film pattern is formed on the surface of the interlayer insulating film directly above the thin-film resistor at a position corresponding to the trimming window opening forming region, and the metal film pattern is used as an etching stopper when the trimming window opening is formed. A method has been proposed in which a trimming window opening is formed by removing the metal film pattern after removing the metal film.
1-1135730). However, in that method, when forming the trimming window opening, it is necessary to remove the interlayer insulating film and the metal film pattern by separate etching steps, so that there is a problem that the number of steps increases.

As another method of controlling the remaining thickness of the interlayer insulating film existing on the thin film resistor after forming the trimming window opening, there is a method of measuring the remaining thickness of the interlayer insulating film. However, thin film resistors are typically only a few microns wide. This width is
To measure the film thickness using an interference film thickness meter that is commonly used, it is too narrow and the positional accuracy cannot be secured. Therefore, the residual film thickness of the interlayer insulating film on the thin film resistor after the formation of the trimming window opening is directly measured. Can not do. Therefore, an opening for monitoring the thickness of the interlayer insulating film is formed at a position different from the opening for the trimming window at the same time as the opening for the trimming window so that the remaining thickness of the interlayer insulating film can be measured. The residual film thickness of the interlayer insulating film on the thin film resistor is indirectly controlled by measuring the film residual film thickness.

FIG. 9 is a plan view of a part of a semiconductor device formed by a conventional method of manufacturing a semiconductor device to be subjected to laser trimming, wherein (a) is a plan view around a thin film resistor.
(B) is a plan view around the film thickness monitoring opening. FIG.
0 is a process sectional view showing a conventional method for manufacturing a semiconductor device to be subjected to laser trimming, and the process will be described below. (A-1) is a cross-sectional view around the thin film resistor before the trimming window opening is formed, (b-1) is a cross-sectional view around the film formation monitoring opening forming region before the trimming window opening is formed, (a).
2B is a cross-sectional view around the thin film resistor after the trimming window opening is formed, and (b-2) is a cross-sectional view around the film thickness monitoring opening after the trimming window opening is formed. (A-1) and (a-2) are cross-sectional views taken along the line AA ′ in FIG.
(B-1) and (b-2) are cross-sectional views at the position BB 'in FIG. 9 (b).

(1) After a field oxide film 3 for element isolation is formed on the surface of a silicon substrate 1, a polysilicon film is deposited, and the polysilicon film is patterned to form a thin film resistor 5 on the field oxide film 3. Form. Thereafter, a BPSG (upper layer) / NSG (lower layer) film 7, a plasma CVD film 9, an organic SOG film 11, a plasma CVD film 13, a PSG film 15, and a nitride film 17 are sequentially formed on the silicon substrate 1 ((a- 1), (b-1)). The PSG film 15 and the nitride film 17 form a passivation film. Here, a wiring forming step is omitted.

(2) After forming a resist pattern having openings in the trimming window opening forming region and the film thickness monitoring opening forming region on the nitride film 17, the thin film is etched by using the resist pattern as a mask. The nitride film 17, the PSG film 15, the plasma CVD film 13, the organic SOG film 11, the plasma CVD film 9, and the BPSG / NS so that the BPSG / NSG film 7 on the resistance element has a desired thickness.
The G film 7 is sequentially etched to simultaneously form the trimming window opening 19 and the film thickness monitoring opening 21.

Generally, BPSG / NSG film 7, plasma C
The VD film 9, the organic SOG film 11, and the plasma CVD film 13 are flattened. At a position where a step such as the thin film resistor 5 exists, the thickness of an interlayer insulating film formed thereover is determined according to the wiring width. Are different. As shown in FIGS. 10 (a-1) and 10 (b-1), in the conventional method, the interlayer insulating film thickness 23 and the film thickness monitoring opening forming region on the thin film resistor 5 in the trimming window opening forming region. The thickness 25 of the interlayer insulating film differs greatly due to the effect of flattening. In particular, in the trimming window opening forming region and the film thickness monitoring opening forming region, BPSG /
The thicknesses of the NSG film 7 and the plasma CVD film 9 are different. Further, the organic SOG film 11 exists in the concave portion of the step in the trimming window opening forming region, but does not exist in the flat film thickness monitoring opening forming region.

The trimming window opening 19 and the film thickness monitoring opening 21 are formed by forming the passivation films 17 and 19 and then etching to a desired film thickness by a single etching, but with different etch rates. Since the film on which the insulating film is laminated is to be etched, and the interlayer insulating film thicknesses 23 and 25 are different, if the etching amount is the same in the trimming window opening forming region and the film thickness monitoring opening forming region. However, the remaining thickness 27 of the interlayer insulating film on the thin film resistor 5 after the etching is different from the remaining thickness 29 of the interlayer insulating film in the opening 21 for monitoring the thickness.

FIG. 11 is a diagram schematically showing the relationship between the residual film thickness of the interlayer insulating film and the etching time when the trimming window opening and the film thickness monitoring opening are formed. The vertical axis indicates the remaining thickness of the interlayer insulating film, and the horizontal axis indicates the etching time. A broken line 30 indicates the relationship between the remaining film thickness of the interlayer insulating film at the film thickness monitoring opening and the etching time. The solid line 32
Shows the relationship between the residual film thickness of the interlayer insulating film on the thin film resistor 5 having a certain wiring width and the etching time. The remaining film thickness 27 of the interlayer insulating film on the thin film resistor 5 after the etching (FIG. 1)
0) is desired to be the film thickness A, the interlayer insulating film remaining film thickness 29 in the film monitoring opening 21 becomes the film thickness a (film thickness A ≠ film thickness a). Therefore, it is necessary to grasp in advance the correlation between the interlayer insulating film remaining thicknesses 27 and 29 with respect to the etching time.

However, even if the remaining thickness 27 of the interlayer insulating film on the thin film resistor 5 can be indirectly and accurately monitored under the certain conditions by the remaining thickness 29 of the interlayer insulating film in the opening 21 for monitoring the thickness. If the line width of the thin-film resistor 5 is different, or if the wiring layers are multi-layered and the process of forming the interlayer insulating film is changed, the balance of the thickness of each interlayer insulating film is lost and the interlayer insulating film thicknesses 23 and 25 are reduced. The film thickness difference changes, and the correlation between the interlayer insulating film remaining film thicknesses 27 and 29 with respect to the etching time also changes, so that the film thickness at the time of etching for forming the trimming window opening 19 and the film thickness monitoring opening 21 each time. It is necessary to optimize the etching amount of the thickness monitor opening formation region or the residual film thickness 29 of the interlayer insulating film after the etching.

An example of the optimization will be described below. The etching time is varied for a product having the corresponding structure, processing is performed, and the interlayer insulating film remaining film thickness 29 after the etching of the film thickness monitoring opening 21 at that time is measured by an interference film thickness meter.
The remaining film thickness 27 of the interlayer insulating film on the thin film resistor 5 in the trimming window opening 19 is obtained by cross-sectional SEM (scanning electron microscope) observation. A correlation diagram similar to that of FIG. 11 was obtained from the obtained interlayer insulating film remaining film thickness 29 after etching of the film thickness monitoring opening 21 and the interlayer insulating film remaining film thickness 27 on the thin film resistor 5 to obtain a desired thin film resistance. Film thickness 27 of interlayer insulating film on body 5
The remaining film thickness 29 of the interlayer insulating film in the opening 21 for monitoring the film thickness and the etching time are optimized so that

Since the remaining thickness 27 of the interlayer insulating film on the thin-film resistor 5 depends on the wiring width of the thin-film resistor 5, the wiring width of the thin-film resistor 5 shows the relationship indicated by the solid line 32 in FIG. When the width is wider than the wiring width, the relationship between the one-dot chain lines 34 is shown. When it is desired to set the remaining thickness 27 of the interlayer insulating film on the thin film resistor 5 to A, the etching time is different for the solid line 32, the dashed-dotted line 34, and the dashed-dotted line 36. , The time c ′ in the alternate long and two short dashes line 36, and the time a ′ ≠ the time b ≠ the time c. Therefore, the interlayer insulating film remaining film thickness 29 of the film thickness monitoring opening 21 is also different, and the time a ′
The relationship between the film thickness a for the time, the film thickness b for the time b ′, and the film thickness c for the time c ′ is as follows: film thickness a 膜厚 film thickness b ≠ film thickness c
Becomes Therefore, it is necessary to grasp the correlation between the etching time and the remaining thicknesses 27 and 29 of the interlayer insulating film according to the wiring width of the thin film resistor 5.

As described above, if the thickness 23 of the interlayer insulating film on the thin film resistor 5 is different from the thickness 25 of the interlayer insulating film in the region for forming the thickness monitoring opening, the remaining thickness of the interlayer insulating film on the thin film resistor 5 27 is susceptible to process variations and pattern dependencies, not only is the etching time optimization for forming the trimming window opening 19 complicated, but also the residual film thickness of the interlayer insulating film on the thin film resistor 5 27 cannot be controlled with high accuracy, and it is difficult to obtain stable quality and reliability of the semiconductor device. Also, if over-etching is excessively performed during the etching for the trimming window opening for some reason, the silicon substrate 1 is exposed in the conventional structure (see FIG. 12), and the reliability of the semiconductor device is significantly reduced. There is also.

[0016]

SUMMARY OF THE INVENTION Therefore, the present invention can easily optimize the etching time in the etching for forming the trimming window opening, and can reduce the residual film thickness of the interlayer insulating film on the thin film resistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be controlled with high accuracy.

[0017]

SUMMARY OF THE INVENTION According to the present invention, a thin film resistor is formed on a semiconductor substrate via an insulating film, and the thickness of the insulating film on the thin film resistor is formed smaller than the surrounding area. A method of manufacturing a semiconductor device in which a trimming window opening is formed, and the thin film resistor is subjected to laser trimming through the trimming window opening, wherein the interlayer insulating film on the thin film resistor is formed before the formation. Forming a dummy pattern around the thin film resistor.

By forming a dummy pattern around the thin film resistor, the interlayer insulating film formed immediately above the thin film resistor can be subjected to a flattening process in a region including the thin film resistor and the dummy pattern. The thickness can be made large, and can be the same as the film thickness in the film formation monitoring opening forming region. Then, in the region including the thin film resistor and the dummy pattern, and in the film formation monitoring opening forming region, the film thicknesses of the respective interlayer insulating films formed on those regions and the sum of the film thicknesses are the same. This allows
Regarding the etching at the time of forming the trimming window opening and the film thickness monitoring opening, the relationship between the remaining thickness of the interlayer insulating film and the etching time in the trimming window opening forming region and the film thickness monitoring opening forming region becomes the same. That is, the remaining thickness of the interlayer insulating film on the thin-film resistor in the etching at the time of forming the trimming window opening and the thickness monitoring opening is equal to the remaining thickness of the interlayer insulating film in the thickness monitoring opening. By measuring the remaining thickness of the interlayer insulating film in the opening for monitoring the thickness, the remaining thickness can be obtained as the remaining thickness of the interlayer insulating film on the thin film resistor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The process of forming a dummy pattern is the same as that of a thin-film resistor, and the dummy pattern is preferably formed of the same material and the same thickness as the thin-film resistor. As a result, it is not necessary to separately provide a dummy pattern forming step, and the upper surfaces of the thin film resistor and the dummy pattern can be formed on the same plane, and the thickness of the interlayer insulating film on the thin film resistor before the trimming window opening is formed. In addition, the thickness of the interlayer insulating film in the region for forming the film thickness monitoring opening can be easily controlled to be the same.

The area including the thin film resistor and the dummy pattern is preferably formed to be larger than the area of the trimming window opening. As a result, since the film thickness of the interlayer insulating film in the trimming window opening forming region is formed thick in all the regions, exposure of the semiconductor substrate due to over-etching in the etching of the trimming window opening can be suppressed. Further, the margin of the trimming window opening forming position can be increased.

The short side width of the region including the thin film resistor and the dummy pattern is preferably at least 8 μm. As a result, even if the interlayer insulating film immediately above the thin film resistor is subjected to the flattening process, the thickness of the interlayer insulating film on the thin film resistor can be prevented from being reduced by the flattening process.

The interval between the thin-film resistor and the dummy pattern, and when the dummy pattern is composed of a plurality of patterns, the maximum interval S of the intervals including the pattern intervals is determined by the following equation. Preferably it is indicated. Interval S ≦ (thickness of interlayer insulating film immediately above thin-film resistor) × (coverage) × 2 Here, coverage refers to FIG.
As shown in FIG. 3, the relationship between the thickness a of the interlayer insulating film formed on the side wall of the protruding portion such as the dummy pattern and the thickness b of the interlayer insulating film formed on the flat portion is referred to as a / b.
Indicated by

[0023]

FIG. 1 is a sectional view showing a process according to an embodiment of the present invention, wherein (a-1), (a-2), and (a-3) show a trimming window opening forming region, and (b) -1), (b-2),
(B-3) shows an opening forming region for a film thickness monitor. (1) After a field oxide film 3 for element isolation is formed on the surface of the silicon wafer 1, a polysilicon film is deposited on the silicon wafer 1 to a thickness of 350 nm, and the polysilicon film is patterned to form a semiconductor device. A gate electrode (not shown) is formed, and a thin film resistor 5 and a dummy pattern 6 are formed (see (a-1) and (b-1)).

FIG. 2 is a top view showing the thin film resistor 5 and the dummy pattern 6 formed in the step (1). FIG. 1A-1 is a cross-sectional view taken along the line XX ′ in FIG.
The line width A of the thin film resistor 5 is 2 μm, and the length B is 1
1 μm. A dummy pattern 6 is formed around the thin film resistor 5 with an interval S of 1 μm from the thin film resistor 5. The line width C of the dummy pattern 6 is 4 μm, and the length dimension D is 13 μm. Here, the area including the thin film resistor 5 and the dummy pattern 6 has a width of 12 μm and a length of 13 μm. Reference numeral 19 denotes a trimming window opening formed in a later step. The width and length of the region including the thin film resistor 5 and the dummy pattern 6 are larger than the width and length of the trimming window opening 19. It is set as follows.

(2) Returning to FIG. 1, the silicon substrate 1 after the thin film resistor 5 and the dummy pattern 6 are formed
An NSG film is deposited thereon with a thickness of 100 nm using normal pressure CVD, and a BPSG film is further deposited thereon with a thickness of 700 nm, and then heat-treated at 850 ° C. under a nitrogen atmosphere. BPSG film is reflowed and BPSG
An (upper layer) / NSG (lower layer) film 7 is formed. Here, since the distance S between the thin film resistor 5 and the dummy pattern 6 is 1 μm, the NSG film and the BPSG film are deposited on the surface of the NSG film and the BPSG film in the region including the thin film resistor 5 and the dummy pattern 6 when the NSG film and the BPSG film are deposited. No irregularities are formed.
Further, since the size of the region including the thin film resistor 5 and the dummy pattern 6 is 12 μm × 13 μm, the BPSG film on the region is not thinned in the flattening process of the BPSG film. The thickness of the BPSG / NSG film 7 in the monitor opening forming region is the same.

After the BPSG / NSG film 7 is formed,
A wiring connection hole (not shown) for connecting a first metal wiring pattern formed on the surface of the SG / NSG film 7 and a polysilicon wiring including the thin film resistor 5 formed immediately below the BPSG / NSG film 7 is formed. It is formed on the BPSG / NSG film 7.
Next, a metal layer mainly composed of Al (aluminum) is deposited on the BPSG / NSG film 7 by sputtering, and the metal layer is patterned to form a first metal wiring pattern (not shown). ) Are formed.

After forming the first metal wiring pattern, B
A plasma CVD film 9 having a thickness of 400 nm is deposited on the PSG / NSG film 7 by plasma CVD. First
The organic SOG film 11 is spin-coated so as to have a thickness of 400 nm in order to flatten the wiring steps of the metal wiring pattern of FIG.
The film 11 is baked, and the organic SOG film 11 is etched back with an oxide film etcher so that the organic SOG film 11 does not remain in a region where a wiring connection hole is formed in a later step.

The organic SOG film 11 is formed by plasma CVD.
A plasma CVD film 13 is deposited thereon with a thickness of 400 nm. Thereafter, wiring connection holes (not shown) for connecting the second metal wiring pattern formed on the surface of the plasma CVD film 13 and the first wiring pattern are formed in the plasma CVD films 13 and 9. Next, a second metal wiring pattern (not shown) is formed by depositing a metal layer mainly containing Al as a main component on the plasma CVD film 13 by using a sputtering method, and then patterning the metal layer. I do.

After forming the second metal wiring pattern, the PS is formed on the plasma CVD film 13 by plasma CVD.
A G film 15 is deposited with a thickness of 200 nm, and a silicon nitride film 17 is further deposited thereon with a thickness of 700 nm. The PSG film 15 and the silicon nitride film 17 form a passivation film. Here, the thickness 31 of the interlayer insulating film on the thin film resistor 5 is the same as the thickness 25 of the interlayer insulating film in the region where the film thickness monitoring opening is formed ((a-2), (b-
2)).

(3) A resist is applied on the silicon nitride film 17, and the resist layer is exposed to a portion corresponding to a trimming window opening forming region and a film thickness monitoring opening forming region, and then subjected to a development process for trimming. A resist pattern having an opening at a position corresponding to the window opening forming region and the film thickness monitoring opening forming region is formed. At this time, as shown in FIG.
Then, a resist pattern is formed so as to be smaller than a region including the dummy pattern 6.

Using the resist pattern as a mask, the silicon nitride film 17, the PSG film 15, the plasma CVD film 13, the plasma CVD film 9 and the BPSG / NSG film 7 are sequentially etched by dry etching to form a trimming window opening 19. Then, an opening 21 for film thickness monitoring is formed. At this time, by controlling the etching time, the remaining thickness of the interlayer insulating film in the film thickness monitoring opening 21 is controlled so that the remaining thickness 33 of the interlayer insulating film above the thin film resistor 5 becomes a desired thickness, for example, 200 nm. Etch while monitoring 35.

FIG. 3 is a diagram schematically showing the relationship between the remaining film thickness of the interlayer insulating film and the etching time when the trimming window opening 19 and the film thickness monitoring opening 21 are formed. The vertical axis indicates the remaining thickness of the interlayer insulating film, and the horizontal axis indicates the etching time. A broken line 24 indicates the relationship between the remaining film thickness 29 of the interlayer insulating film in the film thickness monitoring opening 21 and the etching time.
The solid line 26 indicates the relationship between the remaining thickness 33 of the interlayer insulating film on the thin film resistor 5 and the etching time.

As shown in FIGS. 1 (a-2) and 1 (b-2), the structure of the multilayer interlayer insulating film on the film forming monitor opening forming region and the thin film resistor 5 and the film thickness of each interlayer insulating film Are the same, and the thickness 25 of the interlayer insulating film in the thickness monitor opening forming region is the same as the thickness 31 of the interlayer insulating film on the thin film resistor 5. Therefore, as shown in FIG. 3, the relationship between the remaining thickness of the interlayer insulating film and the etching time in the trimming window opening 19 forming region and the film thickness monitoring opening 21 forming region coincides. That is, when the thickness of the interlayer insulating film remaining on the thin film resistor 5 is to be set to the film thickness A, the etching time is set to the time d.
The film thickness of the film thickness monitoring opening 21 is also the same as the film thickness A.
Becomes Further, the thicknesses of the interlayer insulating films 25 and 31 are the same without being affected by process variations and pattern dependence.

The remaining film thickness 33 of the interlayer insulating film on the thin film resistor 5
Is the remaining thickness 35 of the interlayer insulating film in the opening 21 for film thickness monitoring.
Therefore, there is no need to grasp the correlation between the remaining thickness of the interlayer insulating film on the thin film resistor 5 and the remaining thickness of the interlayer insulating film in the film thickness monitoring opening 21 as in the prior art.
By measuring the remaining thickness 35 of the interlayer insulating film in the opening 21 for monitoring the thickness, the remaining thickness 33 of the interlayer insulating film on the thin film resistor 5 can be known. Thereby, the thin film resistor 5
The thickness 33 of the remaining interlayer insulating film can be controlled stably and with good controllability.

In FIG. 1A-2, by forming a dummy pattern 6 around the thin film resistor 5,
BPS in the area including the thin film resistor 5 and the dummy pattern 6
The thickness of the G / NSG film 7 is larger than that of the prior art. As a result, as shown in FIG.
Even if over-etching occurs during dry etching for formation, exposure of the silicon wafer 1 can be suppressed, and reduction in reliability of the semiconductor device can be suppressed.

FIG. 5 is a process sectional view showing another embodiment of the present invention, in which (a-1), (a-2) and (a-3) show a trimming window opening forming region, and (b) -1), (b-
2) and (b-3) show the opening forming regions for film thickness monitoring. Here, the thin film resistor 5 and the dummy pattern 6 are shown in FIG.
This is the same as the embodiment. (1) After a field oxide film 3 for element isolation is formed on the surface of the silicon wafer 1, a polysilicon film is deposited on the silicon wafer 1 to a thickness of 350 nm, and the polysilicon film is patterned to form a semiconductor device. A gate electrode (not shown) is formed, and a thin film resistor 5, a dummy pattern 6, and a film thickness monitoring pattern 10 are formed (see (a-1) and (b-1)).

FIG. 6 is a top view showing the film thickness monitoring pattern 10 formed in the step (1) of FIG. FIG.
(B-1) is a sectional view taken along the line YY 'in FIG. The width E of the film thickness monitoring pattern 10 is 100 μm, and the length F is 100 μm. Reference numeral 21 denotes a film thickness monitoring window opening formed in a later step, and the film thickness monitoring pattern 10 is set to be larger than the film thickness monitoring opening 21.

(2) Returning to FIG. 5, the description will be continued.
The BPSG / NSG film 7 is formed in the same manner as in the embodiment. Here, the film thickness of the BPSG / NSG film 7 formed on the thin film resistor 5 and the film thickness monitoring pattern 10 is the same. Subsequently, similarly to the embodiment of FIG. 1, the plasma CVD film 9, the organic SOG film 11, the plasma CVD film 1
3. A PSG film 15 and a silicon nitride film 17 are formed.
In FIG. 3, as in the embodiment of FIG. 1, the illustration of the wiring connection holes and the metal wiring patterns is omitted. After the formation of the silicon nitride film 17, the thickness 31 of the interlayer insulating film on the thin film resistor 5 is the same as the thickness 37 of the interlayer insulating film on the thickness monitoring pattern 10 (a-2), (b-). 2)).

(3) A resist is applied on the silicon nitride film 17, and the resist layer is exposed to a portion corresponding to a trimming window opening forming region and a film thickness monitoring opening forming region, and is subjected to a developing process to perform trimming. A resist pattern having an opening at a position corresponding to the window opening forming region and the film thickness monitoring opening forming region is formed. At this time, as shown in FIG. 6, a resist pattern is formed such that the film thickness monitoring opening 21 is smaller than the film thickness monitoring pattern 10.

Using the resist pattern as a mask, the silicon nitride film 17, the PSG film 15, the plasma CVD film 13, the plasma CVD film 9, and the BPSG / NSG film 7 are sequentially etched by dry etching to form a trimming window opening 19. Then, an opening 21 for film thickness monitoring is formed. At this time, by controlling the etching time, the etching is performed such that the residual film thickness 33 of the interlayer insulating film above the thin film resistor 5 becomes a desired film thickness, for example, 200 nm. The remaining film thickness 33 of the interlayer insulating film on the thin film resistor 5 is the thickness monitoring pattern 1
Since the remaining thickness 39 of the interlayer insulating film on the thin film resistor 5 is the same as the remaining thickness 39 of the interlayer insulating film on the thin film resistor 5, You can know.

FIG. 7 is a process sectional view showing still another embodiment of the present invention, in which (a-1), (a-2) and (a-3).
Indicates a trimming window opening forming region, and (b-1),
(B-2) and (b-3) show the film formation monitoring opening forming regions. Here, the film thickness monitoring pattern 10 is the same as that of the embodiment of FIG. (1) After a field oxide film 3 for element isolation is formed on the surface of the silicon wafer 1, a polysilicon film is deposited on the silicon wafer 1 to a thickness of 350 nm, and the polysilicon film is patterned to form a semiconductor device. A gate electrode (not shown) is formed, and a thin film resistor 5, a dummy pattern 6a and a film thickness monitoring pattern 10 are formed (see (a-1) and (b-1)).

FIG. 8 is a top view showing a region including the dummy pattern 6a formed in the step (1) of FIG.
FIG. 7A-1 is a cross-sectional view taken along the line XX ′ in FIG. The thin film resistor 5 is the same as the embodiment of FIG.
Is 2 μm and the length B is 11 μm. Thin film resistor 5
, A dummy pattern 6a is formed at a distance S1 of 1 μm from the thin film resistor 5. Dummy pattern 6
The line width C of a is 7 μm, and the length dimension D is 13 μm. The dummy pattern 6a is composed of a plurality of patterns having a width dimension c of 1 μm arranged at a pattern interval S2 of 1 μm. Here, the region including the thin film resistor 5 and the dummy pattern 6a has a width of 18 μm and a length of 13 μm. Reference numeral 19 denotes a trimming window opening formed in a later step, and includes a thin film resistor 5 and a dummy pattern 6a.
The width and length of the area including the trimming window opening 1
9 are set to be larger than the width and length dimensions.

(2) Returning to FIG. 7, the description will be continued.
The BPSG / NSG film 7 is formed in the same manner as in the embodiment. Here, the interval S1 between the thin film resistor 5 and the dummy pattern 6a is 1 μm, and the pattern interval S2 between the dummy pattern 6a is 1 μm, so that the thin film resistor 5 and the dummy pattern 6a are included when the NSG film and the BPSG film are deposited. In the region, no irregularities are formed on the surfaces of the NSG film and the BPSG film. Further, since the size of the region including the thin film resistor 5 and the dummy pattern 6a is 18 μm × 13 μm, the BPSG film on the region is not thinned in the flattening process of the BPSG film. BPSG / NSG formed on monitor pattern 10
The thickness of the film 7 is the same.

Subsequently, in the same manner as in the embodiment of FIG.
An SG / NSG film 7, a plasma CVD film 9, an organic SOG film 11, a plasma CVD film 13, a PSG film 15, and a silicon nitride film 17 are formed. In FIG. 7, as in the embodiment of FIG. 1, illustration of the wiring connection holes and the metal wiring patterns is omitted. After the formation of the silicon nitride film 17, the thickness 31 of the interlayer insulating film on the thin film resistor 5 is the same as the thickness 37 of the interlayer insulating film on the thickness monitoring pattern (a-2), (b-).
2)).

(3) A resist is applied on the silicon nitride film 17, and the resist layer is exposed to a portion corresponding to a trimming window opening forming region and a film thickness monitoring opening forming region, and is subjected to a developing process to perform trimming. A resist pattern having an opening at a position corresponding to the window opening forming region and the film thickness monitoring opening forming region is formed. At this time, as shown in FIG. 8, a resist pattern is formed such that the trimming window opening 19 is smaller than a region including the thin film resistor 5 and the dummy pattern 6a.

Using the resist pattern as a mask, the silicon nitride film 17, the PSG film 15, the plasma CVD film 13, the plasma CVD film 9 and the BPSG / NSG film 7 are sequentially etched by dry etching to form a trimming window opening 19. Then, an opening 21 for film thickness monitoring is formed. At this time, by controlling the etching time, the etching is performed such that the residual film thickness 33 of the interlayer insulating film above the thin film resistor 5 becomes a desired film thickness, for example, 200 nm. The remaining film thickness 33 of the interlayer insulating film on the thin film resistor 5 is the thickness monitoring pattern 1
Since the remaining thickness 39 of the interlayer insulating film on the thin film resistor 5 is the same as the remaining thickness 39 of the interlayer insulating film on the thin film resistor 5, You can know.

In the present invention, the dummy pattern is not limited to a trapezoidal planar shape as shown in FIG. 2, but may be another shape, or a plurality of patterns as shown in FIG. It may be. However, the maximum distance S among the intervals between the thin film resistor and the dummy pattern, and when the dummy pattern is composed of a plurality of patterns, including the pattern intervals, is determined by the interval S in the interlayer insulating film. In order to prevent the formation of the concave portion, it is preferable that the interval S ≦ (the thickness of the interlayer insulating film immediately above the thin film resistor) × (coverage) × 2.

In the above embodiment, the thin film resistor is made of poly.
Although a silicon film is used, the present invention is not limited to this.
For example, W (tungsten), WSi / Po
Resilicon (WSi indicates tungsten silicide,
WSi_Two, W_FiveSi_Three), TiSi / polysilicon (Ti
Si indicates titanium silicide, TiSi, TiSi_Two, Ti_FiveSi _Three
Other materials may be used. Also, the above
In the embodiment, manufacture of a semiconductor device having a two-layer metal wiring structure
The method is shown, but the present invention is not limited to this.
Rather than a semiconductor device having a multilayer wiring structure of three or more layers.
It can be applied to a manufacturing method. Also, a thin film resistor
Dimensions, dummy pattern dimensions, thin film resistors and
The size of the area including the Mie pattern is limited to the above example
It is not something to be done. Preferably, the thin film resistor and the dummy
The short side width of the region including the pattern is 8 μm or more.

[0049]

In the method of manufacturing a semiconductor device according to the present invention, a dummy pattern is formed around a thin film resistor before an interlayer insulating film is formed on the thin film resistor, so that a trimming window opening is not formed. The thickness of the interlayer insulating film on the thin film resistor is made the same as the thickness of the interlayer insulating film in the opening for monitoring the thickness, and the remaining thickness of the interlayer insulating film in the opening for monitoring the thickness during the etching for forming the trimming window opening. Measurement, the remaining film thickness can be obtained as the remaining film thickness of the interlayer insulating film on the thin-film resistor, so that the etching time in the etching for forming the trimming window opening can be easily optimized. Therefore, the remaining film thickness of the interlayer insulating film on the thin film resistor can be controlled with high accuracy.

If the dummy pattern is formed of the same material and the same thickness as the thin film resistor in the same step as the thin film resistor, it is not necessary to separately provide a dummy pattern forming step, so that the processing time can be shortened. In addition, the upper surfaces of the thin film resistor and the dummy pattern can be formed on the same plane, and the thickness of the interlayer insulating film on the thin film resistor before the formation of the trimming window opening and the interlayer insulating film in the film forming monitor opening forming region are formed. It becomes easier to control the film thickness to the same.

By forming the region including the thin film resistor and the dummy pattern larger than the area of the trimming window opening, the thickness of the interlayer insulating film in the trimming window opening forming region is increased in all the regions. if,
Exposure of the semiconductor substrate due to over-etching in the etching of the trimming window opening can be suppressed,
Further, the margin of the trimming window opening forming position can be increased.

If the short side width of the region including the thin film resistor and the dummy pattern is set to 8 μm or more, even if the interlayer insulating film immediately above the thin film resistor is subjected to a flattening process, the film of the interlayer insulating film on the thin film resistor It is possible to prevent the thickness from being reduced by the planarization process.

When the distance between the thin film resistor and the dummy pattern, and when the dummy pattern is composed of a plurality of patterns, the maximum distance S among the distances including the pattern distance is defined as the distance S ≦ (thin film) If the dummy pattern is formed so as to be expressed by the following formula, the thickness of the interlayer insulating film immediately above the resistor) × (coverage) × 2, in the region including the thin-film resistor and the dummy pattern, Irregularities on the surface of the insulating film can be suppressed.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing one embodiment, in which (a-
1), (a-2) and (a-3) show the trimming window opening forming regions, and (b-1), (b-2) and (b-3) show the film thickness monitoring opening forming regions. Is shown.

FIG. 2 is a top view showing a thin film resistor and a dummy pattern formed in a step (1) of the embodiment.

FIG. 3 is a diagram schematically showing a relationship between an interlayer insulating film remaining film thickness and an etching time when a trimming window opening and a film thickness monitoring opening in the embodiment are formed.

FIG. 4 is a sectional view showing a case where over-etching occurs in the embodiment.

FIG. 5 is a process sectional view showing another embodiment, in which (a-
1), (a-2) and (a-3) show the trimming window opening forming regions, and (b-1), (b-2) and (b-3) show the film thickness monitoring opening forming regions. Is shown.

FIG. 6 is a top view showing a film thickness monitoring pattern formed in step (1) of the embodiment.

FIG. 7 is a process sectional view showing still another embodiment,
(A-1), (a-2) and (a-3) show the trimming window opening forming regions, and (b-1), (b-2) and (b-
3) indicates a film formation monitoring opening forming region.

FIG. 8 is a top view showing a region including a dummy pattern formed in step (1) of the embodiment.

9A and 9B are partial plan views of a semiconductor device formed by a conventional method of manufacturing a semiconductor device to be subjected to laser trimming, wherein FIG. 9A is a plan view around a thin-film resistor, and FIG. It is a top view of a periphery.

FIG. 10 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device subjected to laser trimming.

FIG. 11 is a diagram schematically showing a relationship between a remaining thickness of an interlayer insulating film and an etching time when a trimming window opening and a film thickness monitoring opening are formed in a conventional example.

FIG. 12 is a cross-sectional view showing a case where over-etching occurs in a conventional technique.

FIG. 13 is a cross-sectional view for explaining coverage.

[Explanation of symbols]

 Reference Signs List 1 silicon wafer 3 field oxide film 5 thin film resistor 6 dummy pattern 7 BPSG / NSG film 9, 13 plasma CVD film 11 organic SOG film 15 PSG film 17 silicon nitride film source 19 trimming window opening 21 film thickness monitoring opening 25 , 31,33,35 Interlayer insulating film remaining film thickness

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 HH08 JJ01 KK04 MM01 PP15 QQ01 QQ09 QQ10 QQ11 QQ31 QQ37 QQ53 QQ68 QQ75 RR06 RR09 RR14 RR15 RR25 SS12 SS15 SS22 VV02 VV09 VV11 XX37 5F038 AR06 AR06

Claims (5)

[Claims] A thin-film resistor is formed on a semiconductor substrate via an insulating film, and the thickness of the insulating film on the thin-film resistor is formed to be thinner than the surroundings, thereby forming a trimming window opening for laser trimming. A method of manufacturing a semiconductor device in which a thin film resistor is subjected to laser trimming through the trimming window opening, wherein a dummy pattern is formed around the thin film resistor before forming an interlayer insulating film on the thin film resistor. Forming a semiconductor device. 2. The method according to claim 1, wherein the step of forming the dummy pattern is the same as the step of forming the thin film resistor, and the dummy pattern is formed of the same material and the same thickness as the thin film resistor. 3. The manufacturing method according to claim 1, wherein a region including the thin film resistor and the dummy pattern is formed larger than an area of the trimming window opening. 4. The area including the thin film resistor and the dummy pattern has a short side width of 8 μm or more.
The production method according to any one of the above. 5. The maximum distance S between the thin-film resistor and the dummy pattern, and when the dummy pattern is composed of a plurality of patterns, including the pattern intervals. The manufacturing method according to any one of claims 1 to 4, wherein an interval S ≤ (film thickness of an interlayer insulating film immediately above the thin film resistor) x (coverage) x 2.